OpenCores
URL https://opencores.org/ocsvn/neural_net_perceptron/neural_net_perceptron/trunk

Subversion Repositories neural_net_perceptron

[/] [neural_net_perceptron/] [trunk/] [rtl/] [vhdl/] [p0300_m00025_s_v02_init_fsm.vhd] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 fpga_is_fu 
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
2 
-- (email: opencores@vivare-services.com)
3 
--
4 
-- This program is free software: you can redistribute it and/or modify it
5 
-- under the terms of the GNU General Public License as published by
6 
-- the Free Software Foundation, either version 3 of the License, or any
7 
-- later version.
8 
--
9 
-- This program is distributed in the hope that it will be useful, but
10 
-- WITHOUT ANY WARRANTY; without even the implied warranty of
11 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 
-- See the GNU General Public License for more details.
13 
--
14 
-- You should have received a copy of the GNU General Public License
15 
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
16 
--
17 
--
18 
LIBRARY ieee;
19 
USE ieee.std_logic_1164.all;
20 
USE ieee.std_logic_arith.all;
21 
--USE ieee.numeric_std.all;
22 
LIBRARY work;
23 
USE work.memory_vhd_v03_pkg.ALL;
24 
 
25 
ENTITY p0300_m00025_s_v02_init_fsm IS
26 
   PORT(
27 
      clk_i        : IN     std_logic;
28 
      cnti_end_i   : IN     std_logic;
29 
      cntj_end_i   : IN     std_logic;
30 
      ctrl_bias_i  : IN     DATA_T;
31 
      ctrl_rdlat_i : IN     MEM_LAT_CNT_WIDTH_T;
32 
      ctrl_rdy7_i  : IN     std_logic;
33 
      ctrl_start_i : IN     std_logic;
34 
      ctrl_wrlat_i : IN     MEM_LAT_CNT_WIDTH_T;
35 
      rst_n_i      : IN     std_logic;
36 
      cnteni_o     : OUT    std_logic;
37 
      cntenj_o     : OUT    std_logic;
38 
      ctrl_rdy_o   : OUT    std_logic;
39 
      dout_o       : OUT    DATA_T;
40 
      we_bias_o    : OUT    std_logic;
41 
      we_s_o       : OUT    std_logic;
42 
      we_t_o       : OUT    std_logic;
43 
      we_w_o       : OUT    std_logic;
44 
      we_y_o       : OUT    std_logic
45 
   );
46 
 
47 
-- Declarations
48 
 
49 
END p0300_m00025_s_v02_init_fsm ;
50 
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
51 
-- VIVARE GmbH Switzerland
52 
-- (email: opencores@vivare-services.com)
53 
--
54 
-- Versions:
55 
-- Revision 2.0  2022/07/03
56 
-- - Introduced latency for write
57 
-- Revision 1.0  2022/06/12
58 
-- -- First draft
59 
--
60 
LIBRARY ieee;
61 
USE ieee.std_logic_1164.all;
62 
USE ieee.std_logic_arith.all;
63 
--USE ieee.numeric_std.all;
64 
LIBRARY work;
65 
USE work.memory_vhd_v03_pkg.ALL;
66 
 
67 
ARCHITECTURE fsm OF p0300_m00025_s_v02_init_fsm IS
68 
 
69 
   -- Architecture Declarations
70 
   SIGNAL ctrl_rdlat_reg : MEM_LAT_CNT_WIDTH_T;
71 
   SIGNAL ctrl_start_reg : std_logic;
72 
   SIGNAL ctrl_wrlat_reg : MEM_LAT_CNT_WIDTH_T;
73 
 
74 
   TYPE STATE_TYPE IS (
75 
      S00,
76 
      S06,
77 
      S02,
78 
      S03,
79 
      S04,
80 
      S01,
81 
      S08,
82 
      S07,
83 
      S05
84 
   );
85 
 
86 
   -- Declare current and next state signals
87 
   SIGNAL current_state : STATE_TYPE;
88 
   SIGNAL next_state : STATE_TYPE;
89 
 
90 
BEGIN
91 
 
92 
   -----------------------------------------------------------------
93 
   clocked_proc : PROCESS (
94 
      clk_i
95 
   )
96 
   -----------------------------------------------------------------
97 
   BEGIN
98 
      IF (clk_i'EVENT AND clk_i = '1') THEN
99 
         IF (rst_n_i = '0') THEN
100 
            current_state <= S00;
101 
            -- Default Reset Values
102 
            ctrl_rdlat_reg <= (others => '0');
103 
            ctrl_start_reg <= '0';
104 
            ctrl_wrlat_reg <= (others => '0');
105 
         ELSE
106 
            current_state <= next_state;
107 
            -- Default Assignment To Internals
108 
            ctrl_rdlat_reg <= ctrl_rdlat_reg;
109 
            ctrl_start_reg <= ctrl_start_i;
110 
            ctrl_wrlat_reg <= ctrl_wrlat_reg;
111 
 
112 
            -- Combined Actions
113 
            CASE current_state IS
114 
               -- Write W, S. Next i.
115 
               -- S also on j-path
116 
               WHEN S04 =>
117 
                  ctrl_rdlat_reg <= ctrl_rdlat_i;
118 
                  ctrl_wrlat_reg <= ctrl_wrlat_i;
119 
               -- Dummy cycles to
120 
               -- equalize latency.
121 
               -- End-path
122 
               WHEN S08 =>
123 
                  ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
124 
               -- Dummy cycles to
125 
               -- equalize latency.
126 
               -- j-path
127 
               WHEN S07 =>
128 
                  ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
129 
               -- Dummy cycles to
130 
               -- equalize latency.
131 
               -- i-path
132 
               WHEN S05 =>
133 
                  ctrl_rdlat_reg <= '0' & ctrl_rdlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
134 
                  ctrl_wrlat_reg <= '0' & ctrl_wrlat_reg ( MEM_LAT_CNT_WIDTH - 1 downto 1 );
135 
               WHEN OTHERS =>
136 
                  NULL;
137 
            END CASE;
138 
         END IF;
139 
      END IF;
140 
   END PROCESS clocked_proc;
141 
 
142 
   -----------------------------------------------------------------
143 
   nextstate_proc : PROCESS (
144 
      cnti_end_i,
145 
      cntj_end_i,
146 
      ctrl_rdlat_reg,
147 
      ctrl_rdy7_i,
148 
      ctrl_start_reg,
149 
      ctrl_wrlat_reg,
150 
      current_state
151 
   )
152 
   -----------------------------------------------------------------
153 
   BEGIN
154 
      CASE current_state IS
155 
         -- Reset state
156 
         WHEN S00 =>
157 
            IF (ctrl_rdy7_i = '1') THEN
158 
               next_state <= S01;
159 
            ELSE
160 
               next_state <= S00;
161 
            END IF;
162 
         -- Next j
163 
         WHEN S06 =>
164 
            IF (cntj_end_i = '1') THEN
165 
               next_state <= S08;
166 
            ELSE
167 
               next_state <= S07;
168 
            END IF;
169 
         -- Write BIAS
170 
         WHEN S02 =>
171 
            next_state <= S03;
172 
         -- Write T and Y
173 
         WHEN S03 =>
174 
            next_state <= S04;
175 
         -- Write W, S. Next i.
176 
         -- S also on j-path
177 
         WHEN S04 =>
178 
            IF (cnti_end_i = '1') THEN
179 
               next_state <= S06;
180 
            ELSE
181 
               next_state <= S05;
182 
            END IF;
183 
         -- Wait for next
184 
         -- INIT request
185 
         WHEN S01 =>
186 
            IF (ctrl_start_reg = '1') THEN
187 
               next_state <= S02;
188 
            ELSE
189 
               next_state <= S01;
190 
            END IF;
191 
         -- Dummy cycles to
192 
         -- equalize latency.
193 
         -- End-path
194 
         WHEN S08 =>
195 
            IF (unsigned ( ctrl_rdlat_reg ) <= 7) THEN
196 
               next_state <= S01;
197 
            ELSE
198 
               next_state <= S08;
199 
            END IF;
200 
         -- Dummy cycles to
201 
         -- equalize latency.
202 
         -- j-path
203 
         WHEN S07 =>
204 
            IF (unsigned ( ctrl_rdlat_reg ) <= 7) THEN
205 
               next_state <= S02;
206 
            ELSE
207 
               next_state <= S07;
208 
            END IF;
209 
         -- Dummy cycles to
210 
         -- equalize latency.
211 
         -- i-path
212 
         WHEN S05 =>
213 
            IF (unsigned ( ctrl_rdlat_reg ) <= 7 AND
214 
                unsigned ( ctrl_wrlat_reg ) <= 7) THEN
215 
               next_state <= S04;
216 
            ELSE
217 
               next_state <= S05;
218 
            END IF;
219 
         WHEN OTHERS =>
220 
            next_state <= S00;
221 
      END CASE;
222 
   END PROCESS nextstate_proc;
223 
 
224 
   -----------------------------------------------------------------
225 
   output_proc : PROCESS (
226 
      ctrl_bias_i,
227 
      current_state
228 
   )
229 
   -----------------------------------------------------------------
230 
   BEGIN
231 
      -- Default Assignment
232 
      cnteni_o <= '0';
233 
      cntenj_o <= '0';
234 
      ctrl_rdy_o <= '0';
235 
      dout_o <= (others => '0');
236 
      we_bias_o <= '0';
237 
      we_s_o <= '0';
238 
      we_t_o <= '0';
239 
      we_w_o <= '0';
240 
      we_y_o <= '0';
241 
 
242 
      -- Combined Actions
243 
      CASE current_state IS
244 
         -- Next j
245 
         WHEN S06 =>
246 
            cntenj_o <= '1';
247 
         -- Write BIAS
248 
         WHEN S02 =>
249 
            dout_o <= ctrl_bias_i;
250 
            we_bias_o <= '1';
251 
         -- Write T and Y
252 
         WHEN S03 =>
253 
            dout_o <= (others => '0');
254 
            we_t_o <= '1';
255 
            we_y_o <= '1';
256 
         -- Write W, S. Next i.
257 
         -- S also on j-path
258 
         WHEN S04 =>
259 
            dout_o <= (others => '0');
260 
            we_w_o <= '1';
261 
            we_s_o <= '1';
262 
            cnteni_o <= '1';
263 
         -- Wait for next
264 
         -- INIT request
265 
         WHEN S01 =>
266 
            ctrl_rdy_o <= '1';
267 
         WHEN OTHERS =>
268 
            NULL;
269 
      END CASE;
270 
   END PROCESS output_proc;
271 
 
272 
END fsm;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.