OpenCores
URL https://opencores.org/ocsvn/neural_net_perceptron/neural_net_perceptron/trunk

Subversion Repositories neural_net_perceptron

[/] [neural_net_perceptron/] [trunk/] [rtl/] [vhdl/] [p0300_m00033_s_v01_for_loop_memwi_fsm.vhd] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 fpga_is_fu 
-- COPYRIGHT (C) 2022 by Jens Gutschmidt / VIVARE GmbH Switzerland
2 
-- (email: opencores@vivare-services.com)
3 
--
4 
-- This program is free software: you can redistribute it and/or modify it
5 
-- under the terms of the GNU General Public License as published by
6 
-- the Free Software Foundation, either version 3 of the License, or any
7 
-- later version.
8 
--
9 
-- This program is distributed in the hope that it will be useful, but
10 
-- WITHOUT ANY WARRANTY; without even the implied warranty of
11 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 
-- See the GNU General Public License for more details.
13 
--
14 
-- You should have received a copy of the GNU General Public License
15 
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
16 
--
17 
--
18 
LIBRARY ieee;
19 
USE ieee.std_logic_1164.all;
20 
USE ieee.std_logic_arith.all;
21 
--USE ieee.numeric_std.all;
22 
LIBRARY work;
23 
USE work.memory_vhd_v03_pkg.ALL;
24 
 
25 
ENTITY p0300_m00033_s_v01_for_loop_memwi_fsm IS
26 
   PORT(
27 
      clk_i        : IN     std_logic;
28 
      cnten1_i     : IN     std_logic;
29 
      cnten2_i     : IN     std_logic;
30 
      cnten3_i     : IN     std_logic;
31 
      cnten4_i     : IN     std_logic;
32 
      cnten5_i     : IN     std_logic;
33 
      cnten7_i     : IN     std_logic;
34 
      rst_n_i      : IN     std_logic;
35 
      set_init_i   : IN     std_logic;
36 
      start_vali_i : IN     ADDRESS_S_T;
37 
      stop_vali_i  : IN     ADDRESS_S_T;
38 
      cnt_end_o    : OUT    std_logic;
39 
      cnt_rdy_o    : OUT    std_logic;
40 
      cnt_val_o    : OUT    ADDRESS_S_T
41 
   );
42 
 
43 
-- Declarations
44 
 
45 
END p0300_m00033_s_v01_for_loop_memwi_fsm ;
46 
-- COPYRIGHT (C) 2022 Jens Gutschmidt /
47 
-- VIVARE GmbH Switzerland
48 
-- (email: opencores@vivare-services.com)
49 
--
50 
-- Versions:
51 
-- Revision 1.0  2022/06/09
52 
-- -- First draft
53 
--
54 
LIBRARY ieee;
55 
USE ieee.std_logic_1164.all;
56 
USE ieee.std_logic_arith.all;
57 
--USE ieee.numeric_std.all;
58 
LIBRARY work;
59 
USE work.memory_vhd_v03_pkg.ALL;
60 
 
61 
ARCHITECTURE fsm_behv OF p0300_m00033_s_v01_for_loop_memwi_fsm IS
62 
 
63 
   -- Architecture Declarations
64 
   SIGNAL cnt_end_reg : std_logic;
65 
   SIGNAL cnt_reg : ADDRESS_S_T;
66 
   SIGNAL cnten_reg : std_logic;
67 
   SIGNAL set_init_reg : std_logic;
68 
 
69 
   TYPE STATE_TYPE IS (
70 
      S01,
71 
      S02,
72 
      S03,
73 
      S06,
74 
      S04,
75 
      S05,
76 
      S00
77 
   );
78 
 
79 
   -- Declare current and next state signals
80 
   SIGNAL current_state : STATE_TYPE;
81 
   SIGNAL next_state : STATE_TYPE;
82 
 
83 
BEGIN
84 
 
85 
   -----------------------------------------------------------------
86 
   clocked_proc : PROCESS (
87 
      clk_i
88 
   )
89 
   -----------------------------------------------------------------
90 
   BEGIN
91 
      IF (clk_i'EVENT AND clk_i = '1') THEN
92 
         IF (rst_n_i = '0') THEN
93 
            current_state <= S00;
94 
            -- Default Reset Values
95 
            cnt_end_reg <= '0';
96 
            cnt_reg <= (others => '0');
97 
            cnten_reg <= '0';
98 
            set_init_reg <= '0';
99 
         ELSE
100 
            current_state <= next_state;
101 
            -- Default Assignment To Internals
102 
            cnt_end_reg <= '0';
103 
            cnt_reg <= cnt_reg;
104 
            cnten_reg <= cnten1_i OR cnten2_i OR cnten3_i OR cnten4_i OR cnten5_i OR cnten7_i;
105 
            set_init_reg <= set_init_i;
106 
 
107 
            -- Combined Actions
108 
            CASE current_state IS
109 
               -- Start loop
110 
               WHEN S01 =>
111 
                  cnt_reg <= start_vali_i;
112 
               -- COUNT +
113 
               WHEN S02 =>
114 
                  cnt_reg <= unsigned (cnt_reg) + 1;
115 
                  IF (cnt_reg = unsigned (stop_vali_i) - 1 OR
116 
                      set_init_reg = '1') THEN
117 
                     cnt_end_reg <= '1';
118 
                  END IF;
119 
               -- Wait for next
120 
               -- count enable.
121 
               WHEN S03 =>
122 
                  IF (set_init_reg = '1') THEN
123 
                     cnt_end_reg <= '1';
124 
                  END IF;
125 
               -- COUNT -
126 
               WHEN S04 =>
127 
                  cnt_reg <= unsigned (cnt_reg) - 1;
128 
                  IF (cnt_reg = unsigned (stop_vali_i) + 1 OR
129 
                      set_init_reg = '1') THEN
130 
                     cnt_end_reg <= '1';
131 
                  END IF;
132 
               -- Wait for next
133 
               -- count enable.
134 
               WHEN S05 =>
135 
                  IF (set_init_reg = '1') THEN
136 
                     cnt_end_reg <= '1';
137 
                  END IF;
138 
               WHEN OTHERS =>
139 
                  NULL;
140 
            END CASE;
141 
         END IF;
142 
      END IF;
143 
   END PROCESS clocked_proc;
144 
 
145 
   -----------------------------------------------------------------
146 
   nextstate_proc : PROCESS (
147 
      cnt_reg,
148 
      cnten_reg,
149 
      current_state,
150 
      set_init_reg,
151 
      start_vali_i,
152 
      stop_vali_i
153 
   )
154 
   -----------------------------------------------------------------
155 
   BEGIN
156 
      CASE current_state IS
157 
         -- Start loop
158 
         WHEN S01 =>
159 
            IF (cnten_reg = '1' AND
160 
                unsigned (stop_vali_i) > unsigned (start_vali_i)) THEN
161 
               next_state <= S02;
162 
            ELSIF (cnten_reg = '1' AND
163 
                   unsigned (stop_vali_i) < unsigned (start_vali_i)) THEN
164 
               next_state <= S04;
165 
            ELSE
166 
               next_state <= S01;
167 
            END IF;
168 
         -- COUNT +
169 
         WHEN S02 =>
170 
            IF (cnt_reg = unsigned (stop_vali_i) - 1 OR
171 
                set_init_reg = '1') THEN
172 
               next_state <= S06;
173 
            ELSIF (cnten_reg = '0') THEN
174 
               next_state <= S03;
175 
            ELSE
176 
               next_state <= S02;
177 
            END IF;
178 
         -- Wait for next
179 
         -- count enable.
180 
         WHEN S03 =>
181 
            IF (set_init_reg = '1') THEN
182 
               next_state <= S06;
183 
            ELSIF (cnten_reg = '1') THEN
184 
               next_state <= S02;
185 
            ELSE
186 
               next_state <= S03;
187 
            END IF;
188 
         -- End-of-count
189 
         -- or cancel.
190 
         WHEN S06 =>
191 
            IF (cnten_reg = '1' OR
192 
                set_init_reg = '1') THEN
193 
               next_state <= S01;
194 
            ELSE
195 
               next_state <= S06;
196 
            END IF;
197 
         -- COUNT -
198 
         WHEN S04 =>
199 
            IF (cnt_reg = unsigned (stop_vali_i) + 1 OR
200 
                set_init_reg = '1') THEN
201 
               next_state <= S06;
202 
            ELSIF (cnten_reg = '0') THEN
203 
               next_state <= S05;
204 
            ELSE
205 
               next_state <= S04;
206 
            END IF;
207 
         -- Wait for next
208 
         -- count enable.
209 
         WHEN S05 =>
210 
            IF (set_init_reg = '1') THEN
211 
               next_state <= S06;
212 
            ELSIF (cnten_reg = '1') THEN
213 
               next_state <= S04;
214 
            ELSE
215 
               next_state <= S05;
216 
            END IF;
217 
         -- Reset state
218 
         WHEN S00 =>
219 
            next_state <= S01;
220 
         WHEN OTHERS =>
221 
            next_state <= S00;
222 
      END CASE;
223 
   END PROCESS nextstate_proc;
224 
 
225 
   -----------------------------------------------------------------
226 
   output_proc : PROCESS (
227 
      cnt_end_reg,
228 
      cnt_reg,
229 
      current_state
230 
   )
231 
   -----------------------------------------------------------------
232 
   BEGIN
233 
      -- Default Assignment
234 
      cnt_end_o <= cnt_end_reg;
235 
      cnt_rdy_o <= '0';
236 
      cnt_val_o <= cnt_reg;
237 
 
238 
      -- Combined Actions
239 
      CASE current_state IS
240 
         -- Start loop
241 
         WHEN S01 =>
242 
            cnt_rdy_o <= '1';
243 
         -- End-of-count
244 
         -- or cancel.
245 
         WHEN S06 =>
246 
            cnt_end_o <= '1';
247 
         WHEN OTHERS =>
248 
            NULL;
249 
      END CASE;
250 
   END PROCESS output_proc;
251 
 
252 
END fsm_behv;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.