OpenCores
URL https://opencores.org/ocsvn/next186/next186/trunk

Subversion Repositories next186

[/] [next186/] [trunk/] [sample/] [boot.asm] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 ndumitrach
; this is the bootstrap code contained in SRAM.coe initialization file
2
 
3
.186
4
.model tiny
5
.code
6
      org 0
7
start:
8
      mov ax,0ff80h
9
        mov ss,ax
10
        mov ds,ax
11
        mov es,ax
12
        mov sp,100h
13
 
14
        mov si,com
15
        call srecb
16
        mov bh,ah
17
        call srecb
18
        mov bl,ah
19
 
20
sloop:
21
        call srecb
22
        mov [si],ah
23
        inc si
24
        dec bx
25
        jnz sloop
26
        jmp exec
27
 
28
; ----------------  serial receive byte 115200 bps --------------
29
srecb:
30
      mov ah,80h
31
        mov cx,56h
32
srstb:
33
        in al,0
34
        and al,1
35
        jnz srstb
36
      nop
37
l1:
38
        loop l1
39
 
40
rnxtb:
41
        mov cl,adh
42
l2:
43
        loop l2
44
        test al,80h
45
        jnz return
46
        in al,0
47
        ror ax,1
48
        jmp rnxtb
49
return:
50
        ret
51
exec: jmp com
52
 
53
      org 100h
54
com:
55
 
56
 
57
end start

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.