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[/] [next186_soc_pc/] [trunk/] [HW/] [PIC_8259.v] - Blame information for rev 7

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1 2 ndumitrach
//////////////////////////////////////////////////////////////////////////////////
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//
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// This file is part of the Next186 Soc PC project
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// http://opencores.org/project,next186
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//
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// Filename: PIC_8259.v
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// Description: Part of the Next186 SoC PC project, PIC controller
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//      8259 simplified interrupt controller (only interrupt mask can be read, not IRR or ISR, no EOI required)
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// Version 1.0
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// Creation date: May2012
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//
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// Author: Nicolae Dumitrache 
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// e-mail: ndumitrache@opencores.org
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//
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/////////////////////////////////////////////////////////////////////////////////
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// 
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// Copyright (C) 2012 Nicolae Dumitrache
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// 
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// This source file may be used and distributed without 
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// restriction provided that this copyright statement is not 
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// removed from the file and that any derivative work contains 
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// the original copyright notice and the associated disclaimer.
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// 
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// This source file is free software; you can redistribute it 
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// and/or modify it under the terms of the GNU Lesser General 
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any 
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// later version. 
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// 
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// This source is distributed in the hope that it will be 
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// useful, but WITHOUT ANY WARRANTY; without even the implied 
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
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// PURPOSE. See the GNU Lesser General Public License for more 
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// details. 
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// 
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// You should have received a copy of the GNU Lesser General 
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// Public License along with this source; if not, download it 
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// from http://www.opencores.org/lgpl.shtml 
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// 
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///////////////////////////////////////////////////////////////////////////////////
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// Additional Comments: 
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// http://wiki.osdev.org/8259_PIC
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//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module PIC_8259(
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    input CS,
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         input WR,
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         input [7:0]din,
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         output OE,
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         output wire [7:0]dout,
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         output reg [7:0]ivect,
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         input clk,             // cpu CLK
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         output reg INT = 0,
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         input IACK,
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         input [3:0]I    // 0:timer, 1:keyboard, 2:RTC, 3:mouse
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    );
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        reg [3:0]ss_I = 0;
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        reg [3:0]s_I = 0;
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        reg [3:0]IMR = 4'b1111;
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        reg [3:0]IRR = 0;
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        assign dout = {3'b000, IMR[3:2], 1'b0, IMR[1:0]};
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        assign OE = CS & ~WR;
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        always @ (posedge clk) begin
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                ss_I <= I;
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                s_I <= ss_I;
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                IRR <= (IRR | (~s_I & ss_I)) & ~IMR;    // front edge detection
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                if(~INT) begin
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                        if(IRR[0]) begin //timer
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                                INT <= 1;
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                                ivect <= 8'h08;
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                                IRR[0] <= 0;
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                        end else if(IRR[1]) begin  // keyboard
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                                INT <= 1;
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                                ivect <= 8'h09;
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                                IRR[1] <= 0;
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                        end else if(IRR[2]) begin  // RTC
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                                INT <= 1;
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                                ivect <= 8'h70;
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                                IRR[2] <= 0;
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                        end else if(IRR[3]) begin // mouse
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                                INT <= 1;
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                                ivect <= 8'h74;
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                                IRR[3] <= 0;
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                        end
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                end else if(IACK) INT <= 0;      // also act as Auto EOI
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                if(CS & WR) IMR <= {din[4:3], din[1:0]};
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        end
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endmodule
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