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[/] [next186_soc_pc/] [trunk/] [HW/] [ddr/] [user_design/] [datasheet.txt] - Blame information for rev 2

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                            Datasheet
Generated by mig Version 3.6.1
Sat Jan 28 16:23:16 2012
 
CORE Generator Options:
   FPGA Family                : spartan3a
   FPGA Part                  : xc3s700an-fgg484
   Speed Grade                : -4
   Synthesis Tool             : ISE
   HDL                        : verilog
 
MIG Output Options:
   Component Name              : ddr
   No of Controllers           : 1
   Selected Compatible Devices : --
   Hardware Test Bench           : disabled
 
Controller Options :
   Frequency                  : 133.00 MHz(7519 ps)
   Write Pipe Stages          : 4
   Memory                     : DDR2_SDRAM
   Memory Type                : Components
   Memory Part                : MT47H32M16XX-3
   Equivalent Part(s)         : MT47H32M16BN-3;MT47H32M16CC-3;MT47H32M16FN-3;MT47H32M16GC-3
   Row Address                : 13
   Column Address             : 10
   Bank Address               : 2
   Data Width                 : 16
   Data Mask                  : enabled
 
Memory Options :
   Burst Length                       : 4(010)
   Burst Type                         : sequential(0)
   CAS Latency                        : 3(011)
   DLL Reset                          : yes(1)
   Mode                               : normal(0)
   Write Recovery                     : 3(010)
 
   DQS# Enable                        : Enable(0)
   DLL Enable                         : Enable-Normal(0)
   OCD Operation                      : OCD Exit(000)
   Output Drive Strength              : Fullstrength(0)
   Outputs                            : Enable(0)
   RDQS Enable                        : Disable(0)
   RTT (nominal) - ODT                : RTT Disabled(00)
 
FPGA Options :
   DCM option                           : disabled
   SSTL Class for Address/Control       : Class II
   SSTL Class for Data                  : Class II
   Debug Signals for Memory Controller  : Disable
   System Clock                         : Single-Ended
 
Reserved Pins :
   --
 
    Banks for Data           : 3
    WASSO for Data banks     : 69,
    WASSO for all banks      : Bank 0 - 0
                               Bank 1 - 0
                               Bank 2 - 0
                               Bank 3 - 69
                               Bank 4 - 0
                               Bank 5 - 0
                               Bank 6 - 0
                               Bank 7 - 0
    Data bits                : 16
    Banks for Address/Control: 3
    Banks for System Control : 3
    Banks for System Clock   :
 
 
    ********************************************

Line No.	Rev	Author	Line
1	2	ndumitrach	`Datasheet`
2			`Generated by mig Version 3.6.1`
3			`Sat Jan 28 16:23:16 2012`
4
5			`CORE Generator Options:`
6			`FPGA Family : spartan3a`
7			`FPGA Part : xc3s700an-fgg484`
8			`Speed Grade : -4`
9			`Synthesis Tool : ISE`
10			`HDL : verilog`
11
12			`MIG Output Options:`
13			`Component Name : ddr`
14			`No of Controllers : 1`
15			`Selected Compatible Devices : --`
16			`Hardware Test Bench : disabled`
17
18			`Controller Options :`
19			`Frequency : 133.00 MHz(7519 ps)`
20			`Write Pipe Stages : 4`
21			`Memory : DDR2_SDRAM`
22			`Memory Type : Components`
23			`Memory Part : MT47H32M16XX-3`
24			`Equivalent Part(s) : MT47H32M16BN-3;MT47H32M16CC-3;MT47H32M16FN-3;MT47H32M16GC-3`
25			`Row Address : 13`
26			`Column Address : 10`
27			`Bank Address : 2`
28			`Data Width : 16`
29			`Data Mask : enabled`
30
31			`Memory Options :`
32			`Burst Length : 4(010)`
33			`Burst Type : sequential(0)`
34			`CAS Latency : 3(011)`
35			`DLL Reset : yes(1)`
36			`Mode : normal(0)`
37			`Write Recovery : 3(010)`
38
39			`DQS# Enable : Enable(0)`
40			`DLL Enable : Enable-Normal(0)`
41			`OCD Operation : OCD Exit(000)`
42			`Output Drive Strength : Fullstrength(0)`
43			`Outputs : Enable(0)`
44			`RDQS Enable : Disable(0)`
45			`RTT (nominal) - ODT : RTT Disabled(00)`
46
47			`FPGA Options :`
48			`DCM option : disabled`
49			`SSTL Class for Address/Control : Class II`
50			`SSTL Class for Data : Class II`
51			`Debug Signals for Memory Controller : Disable`
52			`System Clock : Single-Ended`
53
54			`Reserved Pins :`
55			`--`
56
57			`Banks for Data : 3`
58			`WASSO for Data banks : 69,`
59			`WASSO for all banks : Bank 0 - 0`
60			`Bank 1 - 0`
61			`Bank 2 - 0`
62			`Bank 3 - 69`
63			`Bank 4 - 0`
64			`Bank 5 - 0`
65			`Bank 6 - 0`
66			`Bank 7 - 0`
67			`Data bits : 16`
68			`Banks for Address/Control: 3`
69			`Banks for System Control : 3`
70			`Banks for System Clock :`
71
72
73			`********************************************`

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Subversion Repositories next186_soc_pc

[/] [next186_soc_pc/] [trunk/] [HW/] [ddr/] [user_design/] [datasheet.txt] - Blame information for rev 2