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ndumitrach |
//*****************************************************************************
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// DISCLAIMER OF LIABILITY
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//
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// This file contains proprietary and confidential information of
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// Xilinx, Inc. ("Xilinx"), that is distributed under a license
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// from Xilinx, and may be used, copied and/or disclosed only
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// pursuant to the terms of a valid license agreement with Xilinx.
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//
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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// does not warrant that functions included in the Materials will
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// meet the requirements of Licensee, or that the operation of the
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// Materials will be uninterrupted or error-free, or that defects
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// in the Materials will be corrected. Furthermore, Xilinx does
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// not warrant or make any representations regarding use, or the
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// results of the use, of the Materials in terms of correctness,
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// accuracy, reliability or otherwise.
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//
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// Xilinx products are not designed or intended to be fail-safe,
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// or for use in any application requiring fail-safe performance,
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// such as life-support or safety devices or systems, Class III
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// medical devices, nuclear facilities, applications related to
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// the deployment of airbags, or any other applications that could
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// lead to death, personal injury or severe property or
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// environmental damage (individually and collectively, "critical
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// applications"). Customer assumes the sole risk and liability
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// of any use of Xilinx products in critical applications,
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// subject only to applicable laws and regulations governing
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// limitations on product liability.
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//
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// Copyright 2005, 2006, 2007 Xilinx, Inc.
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// All rights reserved.
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//
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// This disclaimer and copyright notice must be retained as part
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// of this file at all times.
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 3.6.1
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// \ \ Application : MIG
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// / / Filename : ddr_infrastructure.v
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// /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:41 $
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// \ \ / \ Date Created : Mon May 2 2005
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// \___\/\___\
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// Device : Spartan-3/3A/3A-DSP
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// Design Name : DDR2 SDRAM
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// Purpose :
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//*****************************************************************************
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`timescale 1ns/100ps
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module ddr_infrastructure
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(
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input clk_int,
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input rst_calib1,
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input [4:0] delay_sel_val,
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output [4:0] delay_sel_val1_val,
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// debug_signals
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output [4:0] dbg_delay_sel,
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output dbg_rst_calib
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);
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reg [4:0] delay_sel_val1;
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reg rst_calib1_r1;
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reg rst_calib1_r2;
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assign dbg_delay_sel = delay_sel_val1;
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assign dbg_rst_calib = rst_calib1_r2;
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assign delay_sel_val1_val = delay_sel_val1;
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always@(negedge clk_int)
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rst_calib1_r1 <= rst_calib1;
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always@(posedge clk_int)
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rst_calib1_r2 <= rst_calib1_r1;
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always@(posedge clk_int) begin
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if( rst_calib1_r2 == 1'b0 )
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delay_sel_val1 <= delay_sel_val;
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else
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delay_sel_val1 <= delay_sel_val1;
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end
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endmodule
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