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--     design files limited to Xilinx devices or technologies. Use            --

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-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.

-- Interfaces:

--    AXI4_SLAVE_S_AXI

--    AXILite_SLAVE_S_AXI

-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG

COMPONENT cache

  PORT (

    clka : IN STD_LOGIC;

    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);

    addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);

    dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);

    douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);

    clkb : IN STD_LOGIC;

    web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);

    addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);

    dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

    doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

  );

END COMPONENT;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture

-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG

your_instance_name : cache

  PORT MAP (

    clka => clka,

    wea => wea,

    addra => addra,

    dina => dina,

    douta => douta,

    clkb => clkb,

    web => web,

    addrb => addrb,

    dinb => dinb,

    doutb => doutb

  );

-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file cache.vhd when simulating

-- the core, cache. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".