URL https://opencores.org/ocsvn/next186_soc_pc/next186_soc_pc/trunk

Subversion Repositories next186_soc_pc

[/] [next186_soc_pc/] [trunk/] [HW/] [ipcore_dir/] [coregen.cgp] - Blame information for rev 2

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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc3s700an
SET devicefamily = spartan3a
SET flowvendor = Other
SET package = fgg484
SET speedgrade = -4
SET verilogsim = true
SET vhdlsim = false

Line No.	Rev	Author	Line
1	2	ndumitrach	`SET busformat = BusFormatAngleBracketNotRipped`
2			`SET designentry = Verilog`
3			`SET device = xc3s700an`
4			`SET devicefamily = spartan3a`
5			`SET flowvendor = Other`
6			`SET package = fgg484`
7			`SET speedgrade = -4`
8			`SET verilogsim = true`
9			`SET vhdlsim = false`

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Subversion Repositories next186_soc_pc

[/] [next186_soc_pc/] [trunk/] [HW/] [ipcore_dir/] [coregen.cgp] - Blame information for rev 2