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//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the Next186 Soc PC project
// http://opencores.org/project,next186
//
// Filename: vga.v
// Description: Part of the Next186 SoC PC project, VGA module
//              customized VGA, only modes 3 (25x80x256 text), 13h (320x200x256 graphic) 
//              and VESA 101h (640x480x256) implemented
// Version 1.0
// Creation date: Jan2012
//
// Author: Nicolae Dumitrache 
// e-mail: ndumitrache@opencores.org
//
/////////////////////////////////////////////////////////////////////////////////
// 
// Copyright (C) 2012 Nicolae Dumitrache
// 
// This source file may be used and distributed without 
// restriction provided that this copyright statement is not 
// removed from the file and that any derivative work contains 
// the original copyright notice and the associated disclaimer.
// 
// This source file is free software; you can redistribute it 
// and/or modify it under the terms of the GNU Lesser General 
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any 
// later version. 
// 
// This source is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied 
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
// PURPOSE. See the GNU Lesser General Public License for more 
// details. 
// 
// You should have received a copy of the GNU Lesser General 
// Public License along with this source; if not, download it 
// from http://www.opencores.org/lgpl.shtml 
// 
///////////////////////////////////////////////////////////////////////////////////
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
 
`timescale 1 ns / 1 ps
 
module VGA_SG
  (
  input  wire   [9:0]    tc_hsblnk,
  input  wire   [9:0]    tc_hssync,
  input  wire   [9:0]    tc_hesync,
  input  wire   [9:0]    tc_heblnk,
 
  output reg    [9:0]    hcount = 0,
  output reg                    hsync,
  output reg                    hblnk = 0,
 
  input  wire   [9:0]    tc_vsblnk,
  input  wire   [9:0]    tc_vssync,
  input  wire   [9:0]    tc_vesync,
  input  wire   [9:0]    tc_veblnk,
 
  output reg    [9:0]    vcount = 0,
  output reg                    vsync,
  output reg                    vblnk = 0,
 
  input  wire                   clk,
  input  wire                   ce
  );
 
  //******************************************************************//
  // This logic describes a 10-bit horizontal position counter.       //
  //******************************************************************//
  always @(posedge clk)
                if(ce) begin
                        if(hcount >= tc_heblnk) begin
                                hcount <= 0;
                                hblnk <= 0;
                        end else begin
                                hcount <= hcount + 1;
                                hblnk <= (hcount >= tc_hsblnk);
                        end
                        hsync <= (hcount >= tc_hssync) && (hcount < tc_hesync);
                end
 
  //******************************************************************//
  // This logic describes a 10-bit vertical position counter.         //
  //******************************************************************//
        always @(posedge clk)
                if(ce && hcount == tc_heblnk) begin
                        if (vcount >= tc_veblnk) begin
                                vcount <= 0;
                                vblnk <= 0;
                        end else begin
                                vcount <= vcount + 1;
                                vblnk <= (vcount >= tc_vsblnk);
                        end
                        vsync <= (vcount >= tc_vssync) && (vcount < tc_vesync);
                end
 
  //******************************************************************//
  // This is the logic for the horizontal outputs.  Active video is   //
  // always started when the horizontal count is zero.  Example:      //
  //                          
  //
  // tc_hsblnk = 03                                                   //
  // tc_hssync = 07                                                   //
  // tc_hesync = 11                                                   //
  // tc_heblnk = 15 (htotal)                                          //
  //                                                                  //
  // hcount   00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15         //
  // hsync    ________________________------------____________        //
  // hblnk    ____________------------------------------------        //
  //                                                                  //
  // hsync time  = (tc_hesync - tc_hssync) pixels                     //
  // hblnk time  = (tc_heblnk - tc_hsblnk) pixels                     //
  // active time = (tc_hsblnk + 1) pixels                             //
  //                                                                  //
  //******************************************************************//
 
  //******************************************************************//
  // This is the logic for the vertical outputs.  Active video is     //
  // always started when the vertical count is zero.  Example:        //
  //                                                                  //
  // tc_vsblnk = 03                                                   //
  // tc_vssync = 07                                                   //
  // tc_vesync = 11                                                   //
  // tc_veblnk = 15 (vtotal)                                          //
  //                                                                  //
  // vcount   00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15         //
  // vsync    ________________________------------____________        //
  // vblnk    ____________------------------------------------        //
  //                                                                  //
  // vsync time  = (tc_vesync - tc_vssync) lines                      //
  // vblnk time  = (tc_veblnk - tc_vsblnk) lines                      //
  // active time = (tc_vsblnk + 1) lines                              //
  //                                                                  //
  //******************************************************************//
 
 
endmodule
 
 
module VGA_DAC(
    input CE,
         input WR,
    input [3:0]addr,
         input [7:0]din,
         output OE,
         output [7:0]dout,
         input CLK,
         input VGA_CLK,
         input [7:0]vga_addr,
         input setindex,
         output [11:0]color,
         output reg vgatext = 1,
         output reg vga400 = 1,
         output reg vgaflash = 0
    );
 
        reg [7:0]mask = 8'hff;
        reg [9:0]index = 0;
        reg mode = 0;
        reg a0mode = 0;
        reg a0data = 0;
        wire [7:0]pal_dout;
        wire [31:0]pal_out;
        wire addr6 = addr == 6;
        wire addr7 = addr == 7;
        wire addr8 = addr == 8;
        wire addr9 = addr == 9;
        wire addr0 = addr == 0;
 
        DAC_SRAM vga_dac
        (
          .clka(CLK), // input clka
          .wea(CE & WR & addr9), // input [0 : 0] wea
          .addra(index), // input [9 : 0] addra
          .dina(din), // input [7 : 0] dina
          .douta(pal_dout), // output [7 : 0] douta
          .clkb(VGA_CLK), // input clkb
          .web(1'b0), // input [0 : 0] web
          .addrb(vga_addr & mask), // input [7 : 0] addrb
          .dinb(32'hxxxxxxxx), // input [31 : 0] dinb
          .doutb(pal_out) // output [31 : 0] doutb
        );
 
        assign color = {pal_out[21:18], pal_out[13:10], pal_out[5:2]};
        assign dout = addr6 ? mask : addr7 ? {6'bxxxxxx, mode, mode} : addr8 ? index[9:2] : pal_dout;
        assign OE = CE & (addr6 | addr7 | addr8 | addr9);
 
        always @(posedge CLK) begin
 
                if(setindex) a0data <= 0;
                else if(CE && addr0 && WR) a0data <= ~a0data;
 
                if(CE) begin
                        if(addr0) begin
                                if(WR) begin
                                        if(~a0data && (din[4:0] == 5'h10)) a0mode <= 1;
                                        else a0mode <= 0;
                                        if(a0mode) begin
                                                vgatext <= ~din[0];
                                                vga400 <= din[6];
                                                vgaflash <= din[3];
                                        end
                                end
                        end
                        if(addr6 && WR) mask <= din;
                        if(addr7 | addr8) begin
                                if(WR) index <= {din, 2'b00};
                                mode <= addr8;
                        end else if(addr9) index <= index + (index[1:0] == 2'b10 ? 2 : 1);
                end
        end
 
endmodule
 
 
 
module VGA_CRT(
    input CE,
         input WR,
         input [7:0]din,
         input addr,
         output [7:0]dout,
         input CLK,
         output reg oncursor,
         output wire [11:0]cursorpos,
         output wire [15:0]scraddr
    );
 
        reg [7:0]crtc[3:0];
        reg [2:0]index = 0;
        assign dout = crtc[index[1:0]];
        assign cursorpos = {crtc[2][3:0], crtc[3]};
        assign scraddr = {crtc[0], crtc[1]};
 
        always @(posedge CLK) if(CE && WR) begin
                if(addr) begin
                        if(index[2]) crtc[index[1:0]] <= din;
                        else if(index[1:0] == 2'b10) oncursor <= din[5];
                end else index <= din[2:0];
        end
endmodule

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[/] [next186_soc_pc/] [trunk/] [HW/] [vga.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ndumitrach	`//////////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// This file is part of the Next186 Soc PC project`
4			`// http://opencores.org/project,next186`
5			`//`
6			`// Filename: vga.v`
7			`// Description: Part of the Next186 SoC PC project, VGA module`
8			`// customized VGA, only modes 3 (25x80x256 text), 13h (320x200x256 graphic)`
9			`// and VESA 101h (640x480x256) implemented`
10			`// Version 1.0`
11			`// Creation date: Jan2012`
12			`//`
13			`// Author: Nicolae Dumitrache`
14			`// e-mail: ndumitrache@opencores.org`
15			`//`
16			`/////////////////////////////////////////////////////////////////////////////////`
17			`//`
18			`// Copyright (C) 2012 Nicolae Dumitrache`
19			`//`
20			`// This source file may be used and distributed without`
21			`// restriction provided that this copyright statement is not`
22			`// removed from the file and that any derivative work contains`
23			`// the original copyright notice and the associated disclaimer.`
24			`//`
25			`// This source file is free software; you can redistribute it`
26			`// and/or modify it under the terms of the GNU Lesser General`
27			`// Public License as published by the Free Software Foundation;`
28			`// either version 2.1 of the License, or (at your option) any`
29			`// later version.`
30			`//`
31			`// This source is distributed in the hope that it will be`
32			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
33			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
34			`// PURPOSE. See the GNU Lesser General Public License for more`
35			`// details.`
36			`//`
37			`// You should have received a copy of the GNU Lesser General`
38			`// Public License along with this source; if not, download it`
39			`// from http://www.opencores.org/lgpl.shtml`
40			`//`
41			`///////////////////////////////////////////////////////////////////////////////////`
42			`// Additional Comments:`
43			`//`
44			`//////////////////////////////////////////////////////////////////////////////////`
45
46			`timescale 1 ns / 1 ps
47
48			`module VGA_SG`
49			`(`
50			`input wire [9:0] tc_hsblnk,`
51			`input wire [9:0] tc_hssync,`
52			`input wire [9:0] tc_hesync,`
53			`input wire [9:0] tc_heblnk,`
54
55			`output reg [9:0] hcount = 0,`
56			`output reg hsync,`
57			`output reg hblnk = 0,`
58
59			`input wire [9:0] tc_vsblnk,`
60			`input wire [9:0] tc_vssync,`
61			`input wire [9:0] tc_vesync,`
62			`input wire [9:0] tc_veblnk,`
63
64			`output reg [9:0] vcount = 0,`
65			`output reg vsync,`
66			`output reg vblnk = 0,`
67
68			`input wire clk,`
69			`input wire ce`
70			`);`
71
72			`//******************************************************************//`
73			`// This logic describes a 10-bit horizontal position counter. //`
74			`//******************************************************************//`
75			`always @(posedge clk)`
76			`if(ce) begin`
77			`if(hcount >= tc_heblnk) begin`
78			`hcount <= 0;`
79			`hblnk <= 0;`
80			`end else begin`
81			`hcount <= hcount + 1;`
82			`hblnk <= (hcount >= tc_hsblnk);`
83			`end`
84			`hsync <= (hcount >= tc_hssync) && (hcount < tc_hesync);`
85			`end`
86
87			`//******************************************************************//`
88			`// This logic describes a 10-bit vertical position counter. //`
89			`//******************************************************************//`
90			`always @(posedge clk)`
91			`if(ce && hcount == tc_heblnk) begin`
92			`if (vcount >= tc_veblnk) begin`
93			`vcount <= 0;`
94			`vblnk <= 0;`
95			`end else begin`
96			`vcount <= vcount + 1;`
97			`vblnk <= (vcount >= tc_vsblnk);`
98			`end`
99			`vsync <= (vcount >= tc_vssync) && (vcount < tc_vesync);`
100			`end`
101
102			`//******************************************************************//`
103			`// This is the logic for the horizontal outputs. Active video is //`
104			`// always started when the horizontal count is zero. Example: //`
105			`//`
106			`//`
107			`// tc_hsblnk = 03 //`
108			`// tc_hssync = 07 //`
109			`// tc_hesync = 11 //`
110			`// tc_heblnk = 15 (htotal) //`
111			`// //`
112			`// hcount 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 //`
113			`// hsync ________________________------------____________ //`
114			`// hblnk ____________------------------------------------ //`
115			`// //`
116			`// hsync time = (tc_hesync - tc_hssync) pixels //`
117			`// hblnk time = (tc_heblnk - tc_hsblnk) pixels //`
118			`// active time = (tc_hsblnk + 1) pixels //`
119			`// //`
120			`//******************************************************************//`
121
122			`//******************************************************************//`
123			`// This is the logic for the vertical outputs. Active video is //`
124			`// always started when the vertical count is zero. Example: //`
125			`// //`
126			`// tc_vsblnk = 03 //`
127			`// tc_vssync = 07 //`
128			`// tc_vesync = 11 //`
129			`// tc_veblnk = 15 (vtotal) //`
130			`// //`
131			`// vcount 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 //`
132			`// vsync ________________________------------____________ //`
133			`// vblnk ____________------------------------------------ //`
134			`// //`
135			`// vsync time = (tc_vesync - tc_vssync) lines //`
136			`// vblnk time = (tc_veblnk - tc_vsblnk) lines //`
137			`// active time = (tc_vsblnk + 1) lines //`
138			`// //`
139			`//******************************************************************//`
140
141
142			`endmodule`
143
144
145			`module VGA_DAC(`
146			`input CE,`
147			`input WR,`
148			`input [3:0]addr,`
149			`input [7:0]din,`
150			`output OE,`
151			`output [7:0]dout,`
152			`input CLK,`
153			`input VGA_CLK,`
154			`input [7:0]vga_addr,`
155			`input setindex,`
156			`output [11:0]color,`
157			`output reg vgatext = 1,`
158			`output reg vga400 = 1,`
159			`output reg vgaflash = 0`
160			`);`
161
162			`reg [7:0]mask = 8'hff;`
163			`reg [9:0]index = 0;`
164			`reg mode = 0;`
165			`reg a0mode = 0;`
166			`reg a0data = 0;`
167			`wire [7:0]pal_dout;`
168			`wire [31:0]pal_out;`
169			`wire addr6 = addr == 6;`
170			`wire addr7 = addr == 7;`
171			`wire addr8 = addr == 8;`
172			`wire addr9 = addr == 9;`
173			`wire addr0 = addr == 0;`
174
175			`DAC_SRAM vga_dac`
176			`(`
177			`.clka(CLK), // input clka`
178			`.wea(CE & WR & addr9), // input [0 : 0] wea`
179			`.addra(index), // input [9 : 0] addra`
180			`.dina(din), // input [7 : 0] dina`
181			`.douta(pal_dout), // output [7 : 0] douta`
182			`.clkb(VGA_CLK), // input clkb`
183			`.web(1'b0), // input [0 : 0] web`
184			`.addrb(vga_addr & mask), // input [7 : 0] addrb`
185			`.dinb(32'hxxxxxxxx), // input [31 : 0] dinb`
186			`.doutb(pal_out) // output [31 : 0] doutb`
187			`);`
188
189			`assign color = {pal_out[21:18], pal_out[13:10], pal_out[5:2]};`
190			`assign dout = addr6 ? mask : addr7 ? {6'bxxxxxx, mode, mode} : addr8 ? index[9:2] : pal_dout;`
191			`assign OE = CE & (addr6 \| addr7 \| addr8 \| addr9);`
192
193			`always @(posedge CLK) begin`
194
195			`if(setindex) a0data <= 0;`
196			`else if(CE && addr0 && WR) a0data <= ~a0data;`
197
198			`if(CE) begin`
199			`if(addr0) begin`
200			`if(WR) begin`
201			`if(~a0data && (din[4:0] == 5'h10)) a0mode <= 1;`
202			`else a0mode <= 0;`
203			`if(a0mode) begin`
204			`vgatext <= ~din[0];`
205			`vga400 <= din[6];`
206			`vgaflash <= din[3];`
207			`end`
208			`end`
209			`end`
210			`if(addr6 && WR) mask <= din;`
211			`if(addr7 \| addr8) begin`
212			`if(WR) index <= {din, 2'b00};`
213			`mode <= addr8;`
214			`end else if(addr9) index <= index + (index[1:0] == 2'b10 ? 2 : 1);`
215			`end`
216			`end`
217
218			`endmodule`
219
220
221
222			`module VGA_CRT(`
223			`input CE,`
224			`input WR,`
225			`input [7:0]din,`
226			`input addr,`
227			`output [7:0]dout,`
228			`input CLK,`
229			`output reg oncursor,`
230			`output wire [11:0]cursorpos,`
231			`output wire [15:0]scraddr`
232			`);`
233
234			`reg [7:0]crtc[3:0];`
235			`reg [2:0]index = 0;`
236			`assign dout = crtc[index[1:0]];`
237			`assign cursorpos = {crtc[2][3:0], crtc[3]};`
238			`assign scraddr = {crtc[0], crtc[1]};`
239
240			`always @(posedge CLK) if(CE && WR) begin`
241			`if(addr) begin`
242			`if(index[2]) crtc[index[1:0]] <= din;`
243			`else if(index[1:0] == 2'b10) oncursor <= din[5];`
244			`end else index <= din[2:0];`
245			`end`
246			`endmodule`