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//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the Next186 Soc PC project
// http://opencores.org/project,next186
//
// Filename: vga.v
// Description: Part of the Next186 SoC PC project, VGA module
//              customized VGA, only modes 3 (25x80x256 text), 13h (320x200x256 graphic) 
//              and VESA 101h (640x480x256) implemented
// Version 1.0
// Creation date: Jan2012
//
// Author: Nicolae Dumitrache 
// e-mail: ndumitrache@opencores.org
//
/////////////////////////////////////////////////////////////////////////////////
// 
// Copyright (C) 2012 Nicolae Dumitrache
// 
// This source file may be used and distributed without 
// restriction provided that this copyright statement is not 
// removed from the file and that any derivative work contains 
// the original copyright notice and the associated disclaimer.
// 
// This source file is free software; you can redistribute it 
// and/or modify it under the terms of the GNU Lesser General 
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any 
// later version. 
// 
// This source is distributed in the hope that it will be 
// useful, but WITHOUT ANY WARRANTY; without even the implied 
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
// PURPOSE. See the GNU Lesser General Public License for more 
// details. 
// 
// You should have received a copy of the GNU Lesser General 
// Public License along with this source; if not, download it 
// from http://www.opencores.org/lgpl.shtml 
// 
///////////////////////////////////////////////////////////////////////////////////
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
 
`timescale 1 ns / 1 ps
 
module VGA_SG
  (
  input  wire   [9:0]    tc_hsblnk,
  input  wire   [9:0]    tc_hssync,
  input  wire   [9:0]    tc_hesync,
  input  wire   [9:0]    tc_heblnk,
 
  output reg    [9:0]    hcount = 0,
  output reg                    hsync,
  output reg                    hblnk = 0,
 
  input  wire   [9:0]    tc_vsblnk,
  input  wire   [9:0]    tc_vssync,
  input  wire   [9:0]    tc_vesync,
  input  wire   [9:0]    tc_veblnk,
 
  output reg    [9:0]    vcount = 0,
  output reg                    vsync,
  output reg                    vblnk = 0,
 
  input  wire                   clk,
  input  wire                   ce
  );
 
  //******************************************************************//
  // This logic describes a 10-bit horizontal position counter.       //
  //******************************************************************//
  always @(posedge clk)
                if(ce) begin
                        if(hcount >= tc_heblnk) begin
                                hcount <= 0;
                                hblnk <= 0;
                        end else begin
                                hcount <= hcount + 1;
                                hblnk <= (hcount >= tc_hsblnk);
                        end
                        hsync <= (hcount >= tc_hssync) && (hcount < tc_hesync);
                end
 
  //******************************************************************//
  // This logic describes a 10-bit vertical position counter.         //
  //******************************************************************//
        always @(posedge clk)
                if(ce && hcount == tc_heblnk) begin
                        if (vcount >= tc_veblnk) begin
                                vcount <= 0;
                                vblnk <= 0;
                        end else begin
                                vcount <= vcount + 1;
                                vblnk <= (vcount >= tc_vsblnk);
                        end
                        vsync <= (vcount >= tc_vssync) && (vcount < tc_vesync);
                end
 
  //******************************************************************//
  // This is the logic for the horizontal outputs.  Active video is   //
  // always started when the horizontal count is zero.  Example:      //
  //                          
  //
  // tc_hsblnk = 03                                                   //
  // tc_hssync = 07                                                   //
  // tc_hesync = 11                                                   //
  // tc_heblnk = 15 (htotal)                                          //
  //                                                                  //
  // hcount   00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15         //
  // hsync    ________________________------------____________        //
  // hblnk    ____________------------------------------------        //
  //                                                                  //
  // hsync time  = (tc_hesync - tc_hssync) pixels                     //
  // hblnk time  = (tc_heblnk - tc_hsblnk) pixels                     //
  // active time = (tc_hsblnk + 1) pixels                             //
  //                                                                  //
  //******************************************************************//
 
  //******************************************************************//
  // This is the logic for the vertical outputs.  Active video is     //
  // always started when the vertical count is zero.  Example:        //
  //                                                                  //
  // tc_vsblnk = 03                                                   //
  // tc_vssync = 07                                                   //
  // tc_vesync = 11                                                   //
  // tc_veblnk = 15 (vtotal)                                          //
  //                                                                  //
  // vcount   00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15         //
  // vsync    ________________________------------____________        //
  // vblnk    ____________------------------------------------        //
  //                                                                  //
  // vsync time  = (tc_vesync - tc_vssync) lines                      //
  // vblnk time  = (tc_veblnk - tc_vsblnk) lines                      //
  // active time = (tc_vsblnk + 1) lines                              //
  //                                                                  //
  //******************************************************************//
 
 
endmodule
 
 
module VGA_DAC(
    input CE,
         input WR,
    input [3:0]addr,
         input [7:0]din,
         output [7:0]dout,
         input CLK,
         input VGA_CLK,
         input [7:0]vga_addr,
         input setindex,
         output [17:0]color,
         output reg vgatext = 1,
         output reg vga400 = 1,
         output reg vgaflash = 0,
         output reg half = 0,
         output reg [3:0]hrzpan = 0
    );
 
        reg [7:0]mask = 8'hff;
        reg [9:0]index = 0;
        reg mode = 0;
        reg [1:0]a0mode = 0;
        reg a0data = 0;
        wire [7:0]pal_dout;
        wire [31:0]pal_out;
        wire addr6 = addr == 6;
        wire addr7 = addr == 7;
        wire addr8 = addr == 8;
        wire addr9 = addr == 9;
        wire addr0 = addr == 0;
 
 
        DAC_SRAM vga_dac
        (
          .clka(CLK), // input clka
          .wea(CE & WR & addr9), // input [0 : 0] wea
          .addra(index), // input [9 : 0] addra
          .dina(din), // input [7 : 0] dina
          .douta(pal_dout), // output [7 : 0] douta
          .clkb(VGA_CLK), // input clkb
          .web(1'b0), // input [0 : 0] web
          .addrb(vga_addr & mask), // input [7 : 0] addrb
          .dinb(32'h00000000), // input [31 : 0] dinb
          .doutb(pal_out) // output [31 : 0] doutb
        );
 
        assign color = {pal_out[21:16], pal_out[13:8], pal_out[5:0]};
        assign dout = addr6 ? mask : addr7 ? {6'bxxxxxx, mode, mode} : addr8 ? index[9:2] : pal_dout;
 
        always @(posedge CLK) begin
 
                if(setindex) a0data <= 0;
                else if(CE && addr0 && WR) a0data <= ~a0data;
 
                if(CE) begin
                        if(addr0) begin
                                if(WR) begin
                                        if(a0data) case(a0mode)
                                                2'b01: {vga400, half, vgaflash, vgatext} <= {din[6], din[4:3], ~din[0]};
                                                2'b10: hrzpan <= din[3:0];
                                        endcase else case(din[4:0])
                                                5'h10: a0mode <= 2'b01;
                                                5'h13: a0mode <= 2'b10;
                                                default: a0mode <= 2'b00;
                                        endcase
                                end
                        end
                        if(addr6 && WR) mask <= din;
                        if(addr7 | addr8) begin
                                if(WR) index <= {din, 2'b00};
                                mode <= addr8;
                        end else if(addr9) index <= index + (index[1:0] == 2'b10 ? 2 : 1);
                end
        end
 
endmodule
 
 
 
module VGA_CRT(
    input CE,
         input WR,
         input WORD,
         input [15:0]din,
         input addr,
         output reg [7:0]dout,
         input CLK,
         output reg oncursor,
         output wire [11:0]cursorpos,
         output wire [15:0]scraddr,
         output reg v240 = 1'b0,
         output reg [7:0]offset = 8'h28
    );
 
        reg [7:0]crtc[3:0];
        reg [4:0]index = 0;
        assign cursorpos = {crtc[2][3:0], crtc[3]};
        assign scraddr = {crtc[0], crtc[1]};
 
        always @(posedge CLK) begin
                if(CE && WR) begin
                        if(addr) begin
                                if(index == 5'h6) v240 <= ~din[7];
                                if(index == 5'ha) oncursor <= din[5];
                                if(index >= 5'hc && index <= 5'hf) crtc[index[1:0]] <= din[7:0];
                                if(index == 5'h13) offset <= din[7:0];
                        end else begin
                                if(WORD) begin
                                        if(din[4:0] == 5'h6) v240 <= ~din[15];
                                        if(din[4:0] == 5'ha) oncursor <= din[13];
                                        if(din[4:0] >= 5'hc && din[4:0] <= 5'hf) crtc[din[1:0]] <= din[15:8];
                                        if(din[4:0] == 5'h13) offset <= din[15:8];
                                end
                                index <= din[4:0];
                        end
                end
                dout <= crtc[index[1:0]];
        end
endmodule
 
 
module VGA_SC(
    input CE,
         input WR,
         input WORD,
         input [15:0]din,
         output reg [7:0]dout,
         input addr,
         input CLK,
         output reg planarreq,
         output reg[3:0]wplane
    );
 
        reg [2:0]index = 0;
 
        always @(posedge CLK) begin
                if(CE && WR) begin
                        if(addr) begin
                                if(index == 2) wplane <= din[3:0];
                                if(index == 4) planarreq <= ~din[3];
                        end else begin
                                if(WORD) begin
                                        if(din[2:0] == 2) wplane <= din[11:8];
                                        if(din[2:0] == 4) planarreq <= ~din[11];
                                end
                                index <= din[2:0];
                        end
                end
                dout <= {4'b0000, index == 2 ? wplane : {~planarreq, 3'b000}};
        end
endmodule
 
 
module VGA_GC(
    input CE,
         input WR,
         input WORD,
         input [15:0]din,
         output reg [7:0]dout,
         input addr,
         input CLK,
         output reg [1:0]rplane = 2'b00,
         output reg[7:0]bitmask = 8'b11111111,
         output reg [2:0]rwmode = 3'b000,
         output reg [3:0]setres = 4'b0000,
         output reg [3:0]enable_setres = 4'b0000,
         output reg [1:0]logop = 2'b00,
         output reg [3:0]color_compare,
         output reg [3:0]color_dont_care
    );
 
        reg [3:0]index = 0;
 
        always @(posedge CLK) begin
                if(CE && WR) begin
                        if(addr) begin
                                case(index)
                                        0: setres <= din[3:0];
                                        1: enable_setres <= din[3:0];
                                        2: color_compare <= din[3:0];
                                        3: logop <= din[4:3];
                                        4: rplane <= din[1:0];
                                        5: rwmode <= {din[3], din[1:0]};
                                        7: color_dont_care <= din[3:0];
                                        8: bitmask <= din[7:0];
                                endcase
                        end else begin
                                if(WORD) case(din[3:0])
                                        0: setres <= din[11:8];
                                        1: enable_setres <= din[11:8];
                                        2: color_compare <= din[11:8];
                                        3: logop <= din[12:11];
                                        4: rplane <= din[9:8];
                                        5: rwmode <= {din[11], din[9:8]};
                                        7: color_dont_care <= din[11:8];
                                        8: bitmask <= din[15:8];
                                endcase
                                index <= din[3:0];
                        end
                end
                case(index)
                        0: dout[3:0] <= setres;
                        1: dout[3:0] <= enable_setres;
                        2: dout[3:0] <= color_compare;
                        3: dout[4:3] <= logop;
                        4: dout[1:0] <= rplane;
                        5: dout[3:0] <= {rwmode[2], 1'bx, rwmode[1:0]};
                        7: dout[3:0] <= color_dont_care;
                        8: dout[7:0] <= bitmask;
                endcase
        end
endmodule
 

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[/] [next186mp3/] [trunk/] [HW/] [vga.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ndumitrach	`//////////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// This file is part of the Next186 Soc PC project`
4			`// http://opencores.org/project,next186`
5			`//`
6			`// Filename: vga.v`
7			`// Description: Part of the Next186 SoC PC project, VGA module`
8			`// customized VGA, only modes 3 (25x80x256 text), 13h (320x200x256 graphic)`
9			`// and VESA 101h (640x480x256) implemented`
10			`// Version 1.0`
11			`// Creation date: Jan2012`
12			`//`
13			`// Author: Nicolae Dumitrache`
14			`// e-mail: ndumitrache@opencores.org`
15			`//`
16			`/////////////////////////////////////////////////////////////////////////////////`
17			`//`
18			`// Copyright (C) 2012 Nicolae Dumitrache`
19			`//`
20			`// This source file may be used and distributed without`
21			`// restriction provided that this copyright statement is not`
22			`// removed from the file and that any derivative work contains`
23			`// the original copyright notice and the associated disclaimer.`
24			`//`
25			`// This source file is free software; you can redistribute it`
26			`// and/or modify it under the terms of the GNU Lesser General`
27			`// Public License as published by the Free Software Foundation;`
28			`// either version 2.1 of the License, or (at your option) any`
29			`// later version.`
30			`//`
31			`// This source is distributed in the hope that it will be`
32			`// useful, but WITHOUT ANY WARRANTY; without even the implied`
33			`// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
34			`// PURPOSE. See the GNU Lesser General Public License for more`
35			`// details.`
36			`//`
37			`// You should have received a copy of the GNU Lesser General`
38			`// Public License along with this source; if not, download it`
39			`// from http://www.opencores.org/lgpl.shtml`
40			`//`
41			`///////////////////////////////////////////////////////////////////////////////////`
42			`// Additional Comments:`
43			`//`
44			`//////////////////////////////////////////////////////////////////////////////////`
45
46			`timescale 1 ns / 1 ps
47
48			`module VGA_SG`
49			`(`
50			`input wire [9:0] tc_hsblnk,`
51			`input wire [9:0] tc_hssync,`
52			`input wire [9:0] tc_hesync,`
53			`input wire [9:0] tc_heblnk,`
54
55			`output reg [9:0] hcount = 0,`
56			`output reg hsync,`
57			`output reg hblnk = 0,`
58
59			`input wire [9:0] tc_vsblnk,`
60			`input wire [9:0] tc_vssync,`
61			`input wire [9:0] tc_vesync,`
62			`input wire [9:0] tc_veblnk,`
63
64			`output reg [9:0] vcount = 0,`
65			`output reg vsync,`
66			`output reg vblnk = 0,`
67
68			`input wire clk,`
69			`input wire ce`
70			`);`
71
72			`//******************************************************************//`
73			`// This logic describes a 10-bit horizontal position counter. //`
74			`//******************************************************************//`
75			`always @(posedge clk)`
76			`if(ce) begin`
77			`if(hcount >= tc_heblnk) begin`
78			`hcount <= 0;`
79			`hblnk <= 0;`
80			`end else begin`
81			`hcount <= hcount + 1;`
82			`hblnk <= (hcount >= tc_hsblnk);`
83			`end`
84			`hsync <= (hcount >= tc_hssync) && (hcount < tc_hesync);`
85			`end`
86
87			`//******************************************************************//`
88			`// This logic describes a 10-bit vertical position counter. //`
89			`//******************************************************************//`
90			`always @(posedge clk)`
91			`if(ce && hcount == tc_heblnk) begin`
92			`if (vcount >= tc_veblnk) begin`
93			`vcount <= 0;`
94			`vblnk <= 0;`
95			`end else begin`
96			`vcount <= vcount + 1;`
97			`vblnk <= (vcount >= tc_vsblnk);`
98			`end`
99			`vsync <= (vcount >= tc_vssync) && (vcount < tc_vesync);`
100			`end`
101
102			`//******************************************************************//`
103			`// This is the logic for the horizontal outputs. Active video is //`
104			`// always started when the horizontal count is zero. Example: //`
105			`//`
106			`//`
107			`// tc_hsblnk = 03 //`
108			`// tc_hssync = 07 //`
109			`// tc_hesync = 11 //`
110			`// tc_heblnk = 15 (htotal) //`
111			`// //`
112			`// hcount 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 //`
113			`// hsync ________________________------------____________ //`
114			`// hblnk ____________------------------------------------ //`
115			`// //`
116			`// hsync time = (tc_hesync - tc_hssync) pixels //`
117			`// hblnk time = (tc_heblnk - tc_hsblnk) pixels //`
118			`// active time = (tc_hsblnk + 1) pixels //`
119			`// //`
120			`//******************************************************************//`
121
122			`//******************************************************************//`
123			`// This is the logic for the vertical outputs. Active video is //`
124			`// always started when the vertical count is zero. Example: //`
125			`// //`
126			`// tc_vsblnk = 03 //`
127			`// tc_vssync = 07 //`
128			`// tc_vesync = 11 //`
129			`// tc_veblnk = 15 (vtotal) //`
130			`// //`
131			`// vcount 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 //`
132			`// vsync ________________________------------____________ //`
133			`// vblnk ____________------------------------------------ //`
134			`// //`
135			`// vsync time = (tc_vesync - tc_vssync) lines //`
136			`// vblnk time = (tc_veblnk - tc_vsblnk) lines //`
137			`// active time = (tc_vsblnk + 1) lines //`
138			`// //`
139			`//******************************************************************//`
140
141
142			`endmodule`
143
144
145			`module VGA_DAC(`
146			`input CE,`
147			`input WR,`
148			`input [3:0]addr,`
149			`input [7:0]din,`
150			`output [7:0]dout,`
151			`input CLK,`
152			`input VGA_CLK,`
153			`input [7:0]vga_addr,`
154			`input setindex,`
155			`output [17:0]color,`
156			`output reg vgatext = 1,`
157			`output reg vga400 = 1,`
158			`output reg vgaflash = 0,`
159			`output reg half = 0,`
160			`output reg [3:0]hrzpan = 0`
161			`);`
162
163			`reg [7:0]mask = 8'hff;`
164			`reg [9:0]index = 0;`
165			`reg mode = 0;`
166			`reg [1:0]a0mode = 0;`
167			`reg a0data = 0;`
168			`wire [7:0]pal_dout;`
169			`wire [31:0]pal_out;`
170			`wire addr6 = addr == 6;`
171			`wire addr7 = addr == 7;`
172			`wire addr8 = addr == 8;`
173			`wire addr9 = addr == 9;`
174			`wire addr0 = addr == 0;`
175
176
177			`DAC_SRAM vga_dac`
178			`(`
179			`.clka(CLK), // input clka`
180			`.wea(CE & WR & addr9), // input [0 : 0] wea`
181			`.addra(index), // input [9 : 0] addra`
182			`.dina(din), // input [7 : 0] dina`
183			`.douta(pal_dout), // output [7 : 0] douta`
184			`.clkb(VGA_CLK), // input clkb`
185			`.web(1'b0), // input [0 : 0] web`
186			`.addrb(vga_addr & mask), // input [7 : 0] addrb`
187			`.dinb(32'h00000000), // input [31 : 0] dinb`
188			`.doutb(pal_out) // output [31 : 0] doutb`
189			`);`
190
191			`assign color = {pal_out[21:16], pal_out[13:8], pal_out[5:0]};`
192			`assign dout = addr6 ? mask : addr7 ? {6'bxxxxxx, mode, mode} : addr8 ? index[9:2] : pal_dout;`
193
194			`always @(posedge CLK) begin`
195
196			`if(setindex) a0data <= 0;`
197			`else if(CE && addr0 && WR) a0data <= ~a0data;`
198
199			`if(CE) begin`
200			`if(addr0) begin`
201			`if(WR) begin`
202			`if(a0data) case(a0mode)`
203			`2'b01: {vga400, half, vgaflash, vgatext} <= {din[6], din[4:3], ~din[0]};`
204			`2'b10: hrzpan <= din[3:0];`
205			`endcase else case(din[4:0])`
206			`5'h10: a0mode <= 2'b01;`
207			`5'h13: a0mode <= 2'b10;`
208			`default: a0mode <= 2'b00;`
209			`endcase`
210			`end`
211			`end`
212			`if(addr6 && WR) mask <= din;`
213			`if(addr7 \| addr8) begin`
214			`if(WR) index <= {din, 2'b00};`
215			`mode <= addr8;`
216			`end else if(addr9) index <= index + (index[1:0] == 2'b10 ? 2 : 1);`
217			`end`
218			`end`
219
220			`endmodule`
221
222
223
224			`module VGA_CRT(`
225			`input CE,`
226			`input WR,`
227			`input WORD,`
228			`input [15:0]din,`
229			`input addr,`
230			`output reg [7:0]dout,`
231			`input CLK,`
232			`output reg oncursor,`
233			`output wire [11:0]cursorpos,`
234			`output wire [15:0]scraddr,`
235			`output reg v240 = 1'b0,`
236			`output reg [7:0]offset = 8'h28`
237			`);`
238
239			`reg [7:0]crtc[3:0];`
240			`reg [4:0]index = 0;`
241			`assign cursorpos = {crtc[2][3:0], crtc[3]};`
242			`assign scraddr = {crtc[0], crtc[1]};`
243
244			`always @(posedge CLK) begin`
245			`if(CE && WR) begin`
246			`if(addr) begin`
247			`if(index == 5'h6) v240 <= ~din[7];`
248			`if(index == 5'ha) oncursor <= din[5];`
249			`if(index >= 5'hc && index <= 5'hf) crtc[index[1:0]] <= din[7:0];`
250			`if(index == 5'h13) offset <= din[7:0];`
251			`end else begin`
252			`if(WORD) begin`
253			`if(din[4:0] == 5'h6) v240 <= ~din[15];`
254			`if(din[4:0] == 5'ha) oncursor <= din[13];`
255			`if(din[4:0] >= 5'hc && din[4:0] <= 5'hf) crtc[din[1:0]] <= din[15:8];`
256			`if(din[4:0] == 5'h13) offset <= din[15:8];`
257			`end`
258			`index <= din[4:0];`
259			`end`
260			`end`
261			`dout <= crtc[index[1:0]];`
262			`end`
263			`endmodule`
264
265
266			`module VGA_SC(`
267			`input CE,`
268			`input WR,`
269			`input WORD,`
270			`input [15:0]din,`
271			`output reg [7:0]dout,`
272			`input addr,`
273			`input CLK,`
274			`output reg planarreq,`
275			`output reg[3:0]wplane`
276			`);`
277
278			`reg [2:0]index = 0;`
279
280			`always @(posedge CLK) begin`
281			`if(CE && WR) begin`
282			`if(addr) begin`
283			`if(index == 2) wplane <= din[3:0];`
284			`if(index == 4) planarreq <= ~din[3];`
285			`end else begin`
286			`if(WORD) begin`
287			`if(din[2:0] == 2) wplane <= din[11:8];`
288			`if(din[2:0] == 4) planarreq <= ~din[11];`
289			`end`
290			`index <= din[2:0];`
291			`end`
292			`end`
293			`dout <= {4'b0000, index == 2 ? wplane : {~planarreq, 3'b000}};`
294			`end`
295			`endmodule`
296
297
298			`module VGA_GC(`
299			`input CE,`
300			`input WR,`
301			`input WORD,`
302			`input [15:0]din,`
303			`output reg [7:0]dout,`
304			`input addr,`
305			`input CLK,`
306			`output reg [1:0]rplane = 2'b00,`
307			`output reg[7:0]bitmask = 8'b11111111,`
308			`output reg [2:0]rwmode = 3'b000,`
309			`output reg [3:0]setres = 4'b0000,`
310			`output reg [3:0]enable_setres = 4'b0000,`
311			`output reg [1:0]logop = 2'b00,`
312			`output reg [3:0]color_compare,`
313			`output reg [3:0]color_dont_care`
314			`);`
315
316			`reg [3:0]index = 0;`
317
318			`always @(posedge CLK) begin`
319			`if(CE && WR) begin`
320			`if(addr) begin`
321			`case(index)`
322			`0: setres <= din[3:0];`
323			`1: enable_setres <= din[3:0];`
324			`2: color_compare <= din[3:0];`
325			`3: logop <= din[4:3];`
326			`4: rplane <= din[1:0];`
327			`5: rwmode <= {din[3], din[1:0]};`
328			`7: color_dont_care <= din[3:0];`
329			`8: bitmask <= din[7:0];`
330			`endcase`
331			`end else begin`
332			`if(WORD) case(din[3:0])`
333			`0: setres <= din[11:8];`
334			`1: enable_setres <= din[11:8];`
335			`2: color_compare <= din[11:8];`
336			`3: logop <= din[12:11];`
337			`4: rplane <= din[9:8];`
338			`5: rwmode <= {din[11], din[9:8]};`
339			`7: color_dont_care <= din[11:8];`
340			`8: bitmask <= din[15:8];`
341			`endcase`
342			`index <= din[3:0];`
343			`end`
344			`end`
345			`case(index)`
346			`0: dout[3:0] <= setres;`
347			`1: dout[3:0] <= enable_setres;`
348			`2: dout[3:0] <= color_compare;`
349			`3: dout[4:3] <= logop;`
350			`4: dout[1:0] <= rplane;`
351			`5: dout[3:0] <= {rwmode[2], 1'bx, rwmode[1:0]};`
352			`7: dout[3:0] <= color_dont_care;`
353			`8: dout[7:0] <= bitmask;`
354			`endcase`
355			`end`
356			`endmodule`
357