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arif_endro |
-- ------------------------------------------------------------------------
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-- Copyright (C) 2010 Arif Endro Nugroho
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- End Of License.
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-- ------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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-- 128 64 0
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-- Ln Rn
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--
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-- L_{r} = R_{r-1} xor F(L_{r-1}, k_r)
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-- R_{r} = L_{r-1}
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-- because P-function working in 64 bit field, then the minimum block is 64.
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entity camellia is
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port (
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pt : in bit_vector ( 63 downto 0);
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key : in bit_vector ( 63 downto 0);
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Nk : in bit_vector ( 3 downto 0);
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ldpt : in bit;
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ct : out bit_vector ( 63 downto 0);
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--probe
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--r_prb : out bit_vector ( 63 downto 0);
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--l_prb : out bit_vector ( 63 downto 0);
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--s_prb : out bit_vector ( 63 downto 0);
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--z_prb : out bit_vector ( 63 downto 0);
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--fla_prb : out bit_vector ( 63 downto 0);
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--ir_prb : out bit_vector ( 63 downto 0);
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--il_prb : out bit_vector ( 63 downto 0);
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--rc_prb : out bit_vector ( 2 downto 0);
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--probe
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v : out bit;
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clk : in bit;
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rst : in bit
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);
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end camellia;
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architecture phy of camellia is
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signal ireg1 : bit_vector (127 downto 0);
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signal ikey : bit_vector ( 63 downto 0);
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signal ipt : bit_vector ( 63 downto 0);
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signal iptt : bit_vector ( 63 downto 0);
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signal f : bit_vector ( 63 downto 0);
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signal l : bit_vector ( 63 downto 0);
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signal r : bit_vector ( 63 downto 0);
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signal ri : bit_vector ( 63 downto 0);
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signal il : bit_vector ( 63 downto 0);
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signal ir : bit_vector ( 63 downto 0);
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signal fl1 : bit_vector ( 63 downto 0);
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signal fl1i : bit_vector ( 63 downto 0);
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signal fl2 : bit_vector ( 63 downto 0);
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signal flx : bit_vector ( 31 downto 0);
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signal fla : bit_vector ( 63 downto 0);
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signal flb : bit_vector ( 63 downto 0);
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signal s1i : bit_vector ( 7 downto 0);
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signal s2i : bit_vector ( 7 downto 0);
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signal s2t : bit_vector ( 7 downto 0);
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signal s3i : bit_vector ( 7 downto 0);
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signal s4i : bit_vector ( 7 downto 0);
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signal s5i : bit_vector ( 7 downto 0);
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signal s5t : bit_vector ( 7 downto 0);
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signal s6i : bit_vector ( 7 downto 0);
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signal s7i : bit_vector ( 7 downto 0);
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signal s8i : bit_vector ( 7 downto 0);
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signal s1o : bit_vector ( 7 downto 0);
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signal s2o : bit_vector ( 7 downto 0);
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signal s3o : bit_vector ( 7 downto 0);
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signal s4o : bit_vector ( 7 downto 0);
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signal s5o : bit_vector ( 7 downto 0);
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signal s6o : bit_vector ( 7 downto 0);
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signal s7o : bit_vector ( 7 downto 0);
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signal s8o : bit_vector ( 7 downto 0);
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signal z1 : bit_vector ( 7 downto 0);
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signal z2 : bit_vector ( 7 downto 0);
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signal z3 : bit_vector ( 7 downto 0);
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signal z4 : bit_vector ( 7 downto 0);
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signal z5 : bit_vector ( 7 downto 0);
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signal z6 : bit_vector ( 7 downto 0);
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signal z7 : bit_vector ( 7 downto 0);
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signal z8 : bit_vector ( 7 downto 0);
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signal c2b : bit_vector ( 1 downto 0);
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signal c2b_cr : bit_vector ( 1 downto 0);
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signal c3b : bit_vector ( 2 downto 0);
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signal c3b_cr : bit_vector ( 2 downto 0);
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signal c3b_rst : bit;
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signal c2b_rst : bit;
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signal rc : bit;
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signal vld4 : bit;
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signal vld8 : bit;
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signal ildpt : bit;
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signal ildptt : bit;
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signal ildpt_rst : bit;
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component sbox
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port (
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di : in bit_vector ( 7 downto 0);
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do : out bit_vector ( 7 downto 0)
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);
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end component;
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begin
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sb1 : sbox
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port map (
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di => s1i,
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do => s1o
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);
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sb2 : sbox
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port map (
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di => s2i,
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do => s2o
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);
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sb3 : sbox
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port map (
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di => s3i,
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do => s3o
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);
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sb4 : sbox
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port map (
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di => s4i,
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do => s4o
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);
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sb5 : sbox
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port map (
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di => s5i,
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do => s5o
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);
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sb6 : sbox
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port map (
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di => s6i,
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do => s6o
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);
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sb7 : sbox
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port map (
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di => s7i,
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do => s7o
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);
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sb8 : sbox
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port map (
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di => s8i,
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do => s8o
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);
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--probe
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--r_prb <= r;
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--l_prb <= l;
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--fla_prb <= fla;
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--ir_prb <= ir;
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--il_prb <= il;
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--rc_prb <= c3b;
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--s_prb <= s8i & s7i & s6i & s5i & s4i & s3i & s2i & s1i;
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--z_prb <= z1 & z2 & z3 & z4 & z5 & z6 & z7 & z8 ;
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--probe
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c3b_cr(0) <= '0'; -- LSB always zero
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c3b_cr( 2 downto 1) <= ( ((c3b( 1 downto 0) and B"01") or (c3b( 1 downto 0) and c3b_cr( 1 downto 0))) or (B"01" and c3b_cr( 1 downto 0)) );
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process (clk)
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begin
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if (clk = '1' and clk'event) then
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if (c3b_rst = '1') then
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c3b <= B"000";
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else
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c3b <= ((c3b xor B"001") xor c3b_cr);
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end if;
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end if;
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end process;
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c2b_cr(0) <= '0'; -- LSB always zero
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c2b_cr(1) <= c2b(0);
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process (clk)
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begin
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if (clk = '1' and clk'event) then
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if (c2b_rst = '1') then
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c2b <= B"00";
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elsif (rc = '1') then
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c2b <= ((c2b xor B"01") xor c2b_cr);
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end if;
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end if;
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end process;
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process (clk)
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begin
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if ((clk = '1') and clk'event) then
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if (rst = '1') then
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ildpt <= '0';
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ildptt <= '0';
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ipt <= (others => '0');
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ikey <= (others => '0');
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fl1i <= (others => '0');
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iptt <= (others => '0');
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ri <= (others => '0');
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else
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ildptt <= ldpt;
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ildpt <= ildptt;
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fl1i <= fl1;
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iptt <= pt;
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ipt <= iptt;
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ikey <= key;
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ri <= r;
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end if;
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end if;
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end process;
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rc <= not(not(c3b(2)) or not(c3b(1)) or not(c3b(0))); -- B"111" -- count until 7 ( 8 clock cycle)
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ildpt_rst <= ((ildpt xor ildptt) and ildpt);
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c3b_rst <= rst or ildpt_rst or rc ;
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c2b_rst <= rst or ildpt_rst;
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--L_{r} == R_{r-1} xor F(L_{r-1}, kr)
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--R_{r} == L_{r-1}
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l <= ireg1(127 downto 64) ;
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r <= ireg1( 63 downto 0) ;
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s1i <= l ( 7 downto 0) xor ikey( 7 downto 0);
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s2t <= l ( 15 downto 8) xor ikey(15 downto 8);
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s2i <= s2t(6 downto 0) & s2t(7);
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s3i <= l ( 23 downto 16) xor ikey(23 downto 16);
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s4i <= l ( 31 downto 24) xor ikey(31 downto 24);-- SBOX4(ROTL1x)
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s5t <= l ( 39 downto 32) xor ikey(39 downto 32);
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s5i <= s5t(6 downto 0) & s5t(7);
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s6i <= l ( 47 downto 40) xor ikey(47 downto 40);
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s7i <= l ( 55 downto 48) xor ikey(55 downto 48);-- SBOX4(ROTL1x)
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s8i <= l ( 63 downto 56) xor ikey(63 downto 56);
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--S-function
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z8 <= s1o; -- SBOX1
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z7 <= s2o; -- SBOX4(ROTL1x)
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z6 <= s3o(0) & s3o(7 downto 1); -- SBOX3 ROTR1
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z5 <= s4o(6 downto 0) & s4o(7); -- SBOX2 ROTL1
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z4 <= s5o; -- SBOX4(ROTL1x)
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z3 <= s6o(0) & s6o(7 downto 1); -- SBOX3 ROTR1
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z2 <= s7o(6 downto 0) & s7o(7); -- SBOX2 ROTL1
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z1 <= s8o; -- SBOX1
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--P-function
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--z'1 == z1 xor z3 xor z4 xor z6 xor z7 xor z8
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--z'2 == z1 xor z2 xor z4 xor z5 xor z7 xor z8
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--z'3 == z1 xor z2 xor z3 xor z5 xor z6 xor z8
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--z'4 == z2 xor z3 xor z4 xor z5 xor z6 xor z7
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--z'5 == z1 xor z2 xor z6 xor z7 xor z8
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--z'6 == z2 xor z3 xor z5 xor z7 xor z8
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--z'7 == z3 xor z4 xor z5 xor z6 xor z8
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--z'8 == z1 xor z4 xor z5 xor z6 xor z7
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f (63 downto 56) <= z1 xor z3 xor z4 xor z6 xor z7 xor z8 ;
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f (55 downto 48) <= z1 xor z2 xor z4 xor z5 xor z7 xor z8 ;
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f (47 downto 40) <= z1 xor z2 xor z3 xor z5 xor z6 xor z8 ;
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f (39 downto 32) <= z2 xor z3 xor z4 xor z5 xor z6 xor z7 ;
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f (31 downto 24) <= z1 xor z2 xor z6 xor z7 xor z8 ;
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f (23 downto 16) <= z2 xor z3 xor z5 xor z7 xor z8 ;
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f (15 downto 8) <= z3 xor z4 xor z5 xor z6 xor z8 ;
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f ( 7 downto 0) <= z1 xor z4 xor z5 xor z6 xor z7 ;
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--F-function
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fla <= r xor f;
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--FL1-function
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--Xi(64) == XL(32) & XR(32)
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--Ki(64) == KL(32) & KR(32)
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--Yr(32) == ((XL and Kl) <<< 1) xor XR
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--Yl(32) == ( Yr or Kr) xor XL
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--Yi(64) == Yl(32) & Yr(32)
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fl1(31 downto 0)<= ((( l (62 downto 32) and ikey(62 downto 32)) & ( l (63) and ikey(63))) xor l (31 downto 0));
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--fl1(31 downto 0)<= ((((fla(62 downto 32) and ikey(62 downto 32)) & (fla(63) and ikey(32))) xor fla(31 downto 0)) or ikey(31 downto 0)) xor fla(63 downto 32);
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fl1(63 downto 32)<= (fl1(31 downto 0) or ikey(31 downto 0)) xor l (63 downto 32);
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il <= fla when rc = '0' else fl1i;
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--FL2-function
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--Yi(64) == YL(32) & YR(32)
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--Ki(64) == KL(32) & KR(32)
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--Xl(32) == ( Yr or Kr) xor YL
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--Xr(32) == ((Xl and Kl) <<< 1) xor YR
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--Xi(64) == Xl(32) & Xr(32)
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fl2(63 downto 32)<= ((ri(31 downto 0) or ikey(31 downto 0)) xor ri(63 downto 32));
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flx(31 downto 0)<= (((ri(31 downto 0) or ikey(31 downto 0)) xor ri(63 downto 32)) and ikey(63 downto 32));
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fl2(31 downto 0)<= (( flx(30 downto 0) & flx(31) ) xor ri(31 downto 0));
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ir <= l when rc = '0' else fl2;
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process (clk)
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begin
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if ((clk = '1') and clk'event) then
|
316 |
|
|
if (rst = '1') then
|
317 |
|
|
ireg1(127 downto 0) <= (others => '0') ;
|
318 |
|
|
elsif (ildpt = '1') then
|
319 |
|
|
ireg1(127 downto 0) <= ireg1( 63 downto 0) & (ipt xor ikey); -- initial round 2 clock
|
320 |
|
|
else
|
321 |
|
|
ireg1( 63 downto 0) <= ir ;
|
322 |
|
|
ireg1(127 downto 64) <= il ;
|
323 |
|
|
end if;
|
324 |
|
|
end if;
|
325 |
|
|
end process;
|
326 |
|
|
|
327 |
|
|
-- this valid signal for Nk=4 2 round (8 clock) plus the next 6-7 (the last two clock of its round) approx: 24 clock for each block
|
328 |
|
|
vld4 <= not(not(c2b(1)) or c2b(0) ) and (not(not(c3b(2)) or not(c3b(1)) or not(c3b(0))) or not(not(c3b(2)) or not(c3b(1)) or c3b(0)));
|
329 |
|
|
-- this valid signal for Nk=6/8 3 round (8 clock) plus the next 6-7 (the last two clock of its round) aprrox: 32 clock for each block
|
330 |
|
|
vld8 <= not(not(c2b(1)) or not(c2b(0))) and (not(not(c3b(2)) or not(c3b(1)) or not(c3b(0))) or not(not(c3b(2)) or not(c3b(1)) or c3b(0)));
|
331 |
|
|
ct <= r xor ikey ;
|
332 |
|
|
v <= vld4 when (not(Nk(3) or not(Nk(2)) or Nk(1) or Nk(0)) = '1') else vld8;
|
333 |
|
|
|
334 |
|
|
end phy;
|