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[/] [nfcc/] [trunk/] [kasumi/] [kasumi.vhdl] - Blame information for rev 2

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-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
-- 
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 
-- 1. Redistributions of source code must retain the above copyright
--    notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
--    notice, this list of conditions and the following disclaimer in the
--    documentation and/or other materials provided with the distribution.
-- 
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-- 
-- End Of License.
-- ------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity kasumi is
  port (
  pt               : in  bit_vector ( 31 downto 0);
  ldpt             : in  bit;
  key              : in  bit_vector ( 63 downto 0);
  ldk              : in  bit;
--probe
--L_prb            : out bit_vector ( 31 downto 0);
--R_prb            : out bit_vector ( 31 downto 0);
--FL_prb           : out bit_vector ( 31 downto 0);
--ikey_prb         : out bit_vector ( 15 downto 0);
--FO_prb           : out bit_vector ( 15 downto 0);
--FI_prb           : out bit_vector ( 15 downto 0);
--st_prb           : out bit_vector (  3 downto 0);
--rnd_prb          : out bit_vector (  1 downto 0);
--even_prb         : out bit;
--probe
  ct               : out bit_vector ( 63 downto 0);
  v                : out bit;
  clk              : in  bit;
  rst              : in  bit
  );
end kasumi;
 
architecture phy of kasumi is
 
  signal ireg1     :     bit_vector ( 63 downto 0);
  signal ikey      :     bit_vector ( 15 downto 0);
  signal ipt       :     bit_vector ( 31 downto 0);
  signal iptt      :     bit_vector ( 31 downto 0);
  signal r         :     bit_vector ( 31 downto 0);
  signal l         :     bit_vector ( 31 downto 0);
  signal ir        :     bit_vector ( 31 downto 0);
  signal il        :     bit_vector ( 31 downto 0);
  signal F         :     bit_vector ( 31 downto 0);
  signal FL        :     bit_vector ( 31 downto 0);
  signal FLl       :     bit_vector ( 15 downto 0);
  signal FLr       :     bit_vector ( 15 downto 0);
  signal FL0       :     bit_vector ( 15 downto 0);
  signal FL1       :     bit_vector ( 15 downto 0);
  signal LFL       :     bit_vector ( 15 downto 0);
  signal RFL       :     bit_vector ( 15 downto 0);
  signal FO        :     bit_vector ( 15 downto 0);
  signal FI        :     bit_vector ( 15 downto 0);
  signal x7a       :     bit_vector (  6 downto 0);
  signal x9a       :     bit_vector (  8 downto 0);
  signal x7b       :     bit_vector (  6 downto 0);
  signal x9b       :     bit_vector (  8 downto 0);
  signal y7a       :     bit_vector (  6 downto 0);
  signal y9a       :     bit_vector (  8 downto 0);
  signal y7b       :     bit_vector (  6 downto 0);
  signal y9b       :     bit_vector (  8 downto 0);
  signal st        :     bit_vector (  3 downto 0); -- 16 states
  signal c3b       :     bit_vector (  2 downto 0);
  signal c3b_cr    :     bit_vector (  2 downto 0);
  signal c3b_rst   :     bit;
  signal rnd       :     bit_vector (  1 downto 0);
  signal rnd_cr    :     bit_vector (  1 downto 0);
  signal rnd_rst   :     bit;
  signal even      :     bit;
  signal vld       :     bit;
  signal ildpt     :     bit;
  signal ildpt_rst :     bit;
  signal ildptt    :     bit;
 
  component sbox
  port (
  x7               : in  bit_vector (  6 downto 0);
  x9               : in  bit_vector (  8 downto 0);
  y7               : out bit_vector (  6 downto 0);
  y9               : out bit_vector (  8 downto 0)
  );
  end component;
 
  component keyschedule
  port (
  key              : in  bit_vector ( 63 downto 0);
  st               : in  bit_vector (  3 downto 0);
  ldk              : in  bit;
  rk               : out bit_vector ( 15 downto 0);
  clk              : in  bit;
  rst              : in  bit
  );
  end component;
 
begin
 
  s1               : sbox
  port map (
  x7               => x7a,
  x9               => x9a,
  y7               => y7a,
  y9               => y9a
  );
  s2               : sbox
  port map (
  x7               => x7b,
  x9               => x9b,
  y7               => y7b,
  y9               => y9b
  );
  roundkey         : keyschedule
  port map (
  key              => key,
  st               => st,
  ldk              => ldk,
  rk               => ikey,
  clk              => clk,
  rst              => rst
  );
 
--probe
--L_prb            <= l;
--R_prb            <= r;
--ikey_prb         <= ikey;
--FL_prb           <= FL;
--FI_prb           <= FI;
--FO_prb           <= FO;
--st_prb           <= st;
--rnd_prb          <= rnd;
--even_prb         <= even;
--probe
 
  process (clk)
  begin
    if ((clk = '1') and clk'event) then
      if (rst = '1') then
        ildpt      <=  '0';
        ildptt     <=  '0';
        ipt        <= (others => '0');
--      ikey       <= (others => '0');
        iptt       <= (others => '0');
      else
        ildptt     <= ldpt;
        ildpt      <= ildptt;
        iptt       <=   pt;
        ipt        <= iptt;
--      ikey       <=  key;
      end if;
    end if;
  end process;
 
  process (clk)
  begin
    if ((clk = '1') and clk'event) then
      if (rst = '1') then
        even       <= '0';
      elsif (c3b = O"7") then
        even       <= not(even);
      end if;
    end if;
  end process;
 
  c3b_cr(0)                            <= '0'; -- LSB always zero
  c3b_cr( 2 downto  1)                 <= ( ((c3b( 1 downto  0) and B"01") or (c3b( 1 downto  0) and c3b_cr( 1 downto  0))) or (B"01" and c3b_cr( 1 downto  0)) );
 
  process (clk)
  begin
    if (clk = '1' and clk'event) then
      if (c3b_rst = '1') then
        c3b        <= B"000";
      else
        c3b        <= ((c3b xor B"001") xor c3b_cr);
      end if;
    end if;
  end process;
 
  ildpt_rst        <= ((ildpt xor ildptt) and ildpt);
  c3b_rst          <= rst or ildpt_rst;
 
  l                <= ireg1( 63 downto 32);
  r                <= ireg1( 31 downto  0);
 
--0-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+
--1-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+
--2-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+
--3-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+
 
  st <= even & c3b;
  process (st,rst,FL,FO,FI,FL0,FL1,r)
  begin
    if (rst = '1') then
      LFL          <= (others => '0');
      RFL          <= (others => '0');
    else
      case st is
        when X"0"  =>
          LFL      <=                      FL(31 downto 16);
          RFL      <= FL0;
        when X"1" =>
          LFL      <= FL1;
          RFL      <=                      FL(15 downto  0);
        when X"2" =>
          LFL      <= FO;
          RFL      <=                      FL(15 downto  0);
        when X"3" =>
          LFL      <=                      FL(15 downto  0);
          RFL      <= FI               xor FL(15 downto  0);
        when X"4" =>
          LFL      <= FO;
          RFL      <=                      FL(15 downto  0);
        when X"5" =>
          LFL      <=                      FL(15 downto  0);
          RFL      <= FI               xor FL(15 downto  0);
        when X"6" =>
          LFL      <= FO;
          RFL      <=                      FL(15 downto  0);
        when X"7" =>
          LFL      <=                      FL(15 downto  0)  xor  r(31 downto 16); -- xor R
          RFL      <= FI               xor FL(15 downto  0)  xor  r(15 downto  0); -- xor R
        when X"8" =>
          LFL      <= FO;
          RFL      <=                      FL(15 downto  0);
        when X"9" =>
          LFL      <=                      FL(15 downto  0);
          RFL      <= FI               xor FL(15 downto  0);
        when X"a" =>
          LFL      <= FO;
          RFL      <=                      FL(15 downto  0);
        when X"b" =>
          LFL      <=                      FL(15 downto  0);
          RFL      <= FI               xor FL(15 downto  0);
        when X"c" =>
          LFL      <= FO;
          RFL      <=                      FL(15 downto  0);
        when X"d" =>
          LFL      <=                      FL(15 downto  0);
          RFL      <= FI               xor FL(15 downto  0);
        when X"e"  =>
          LFL      <=                      FL(31 downto 16);
          RFL      <= FL0;
        when X"f" =>
          LFL      <= FL1              xor  r(31 downto 16); -- xor R
          RFL      <= FL(15 downto  0) xor  r(15 downto  0); -- xor R
      end case;
    end if;
  end process;
 
  FLl              <= l(31 downto 16) when even = '0' else FL(31 downto 16);
  FLr              <= l(15 downto  0) when even = '0' else FL(15 downto  0);
--FL(R')           == FL(R) xor ROTL1{FL(L) and KLi1}
  FL0              <= FLr xor ((FLl(14 downto 0) and ikey(14 downto 0)) & (FLl(15) and ikey(15)));
--FL(L')           == FL(L) xor ROTL1{FL(R') or KLi2}
  FL1              <= FLl xor ((FL (14 downto 0) or  ikey(14 downto 0)) & (FL (15) or  ikey(15)));
 
  process (clk)
  begin
    if ((clk = '1') and clk'event) then
      if (rst = '1') then
        FL         <= (others => '0');
      else
        FL         <= LFL & RFL;
      end if;
    end if;
  end process;
 
--FO               == Lj-1             xor KOij
  FO               <= FL(31 downto 16) xor ikey(15 downto  0);
 
--FI-function
-- L1 == R0                 R1 == S9[L0] xor ZE(R0)
-- L2 == R1 xor KIij2       R2 == S7[L1] xor TR(R1) xor KIij1
-- L3 == R2                 R3 == S9[L2] xor ZE(R2)
-- L4 == S7[L3] xor TR(R3)  R4 == R3
-- Return L4 || R4
 
--L0
  x9a              <= FL(31 downto 23);
--R0
  x7a              <= FL(22 downto 16);
--L2               ==         S9[L0]          xor    ZE    (R0)     xor KIi,j,2 (9 bit)
  x9b              <=         y9a(8 downto 0) xor (B"00" & x7a)     xor ikey( 8 downto 0);
--R2               == S7[L1] xor             TR(R1)                 xor KIi,j,1 (7 bit)
  x7b              <= y7a xor y9a(6 downto 0) xor          x7a      xor ikey(15 downto 9);
--R3               ==         S9[L2]          xor    ZE    (R2)
  FI( 8 downto 0)  <=         y9b(8 downto 0) xor (B"00" & x7b);
--L4               == S7[L3] xor TR(R3)
  FI(15 downto 9)  <= y7b xor  FI(6 downto 0);
--Rj               == FI(Lj-1 xor KOij, KIij) xor Rj-1
 
  il               <= LFL & RFL;
--R'               == Li-1
  ir               <= l;
 
  process (clk)
  begin
    if ((clk = '1') and clk'event) then
      if (rst = '1') then
        ireg1      <= (others => '0');
      elsif (ildpt = '1') then
        ireg1      <= ireg1( 31 downto 0) & ipt;
      elsif (c3b = O"7") then
ireg1(31 downto  0)<= ir;
ireg1(63 downto 32)<= il;
      end if;
    end if;
  end process;
 
  rnd_cr           <= rnd(0) & '0';
  process (clk)
  begin
    if ((clk = '1') and clk'event) then
      if (rst = '1') then
        rnd        <= B"00";
      elsif (st  = X"f") then
        rnd        <= ((rnd xor B"01") xor rnd_cr);
      end if;
    end if;
  end process;
 
  process (clk)
  begin
    if ((clk = '1') and clk'event) then
      if (rst = '1') then
        vld        <= '0';
      elsif ((rnd & st) = B"111111") then
        vld        <= '1';
      else
        vld        <= '0';
      end if;
    end if;
  end process;
 
  v                <= vld;
  ct               <= l & r;
 
end phy;

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[/] [nfcc/] [trunk/] [kasumi/] [kasumi.vhdl] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	arif_endro	`-- ------------------------------------------------------------------------`
2			`-- Copyright (C) 2010 Arif Endro Nugroho`
3			`-- All rights reserved.`
4			`--`
5			`-- Redistribution and use in source and binary forms, with or without`
6			`-- modification, are permitted provided that the following conditions`
7			`-- are met:`
8			`--`
9			`-- 1. Redistributions of source code must retain the above copyright`
10			`-- notice, this list of conditions and the following disclaimer.`
11			`-- 2. Redistributions in binary form must reproduce the above copyright`
12			`-- notice, this list of conditions and the following disclaimer in the`
13			`-- documentation and/or other materials provided with the distribution.`
14			`--`
15			`-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS`
16			`-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED`
17			`-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE`
18			`-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY`
19			`-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
20			`-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS`
21			`-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)`
22			`-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,`
23			`-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN`
24			`-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE`
25			`-- POSSIBILITY OF SUCH DAMAGE.`
26			`--`
27			`-- End Of License.`
28			`-- ------------------------------------------------------------------------`
29
30			`library ieee;`
31			`use ieee.std_logic_1164.all;`
32			`use ieee.std_logic_unsigned.all;`
33
34			`entity kasumi is`
35			`port (`
36			`pt : in bit_vector ( 31 downto 0);`
37			`ldpt : in bit;`
38			`key : in bit_vector ( 63 downto 0);`
39			`ldk : in bit;`
40			`--probe`
41			`--L_prb : out bit_vector ( 31 downto 0);`
42			`--R_prb : out bit_vector ( 31 downto 0);`
43			`--FL_prb : out bit_vector ( 31 downto 0);`
44			`--ikey_prb : out bit_vector ( 15 downto 0);`
45			`--FO_prb : out bit_vector ( 15 downto 0);`
46			`--FI_prb : out bit_vector ( 15 downto 0);`
47			`--st_prb : out bit_vector ( 3 downto 0);`
48			`--rnd_prb : out bit_vector ( 1 downto 0);`
49			`--even_prb : out bit;`
50			`--probe`
51			`ct : out bit_vector ( 63 downto 0);`
52			`v : out bit;`
53			`clk : in bit;`
54			`rst : in bit`
55			`);`
56			`end kasumi;`
57
58			`architecture phy of kasumi is`
59
60			`signal ireg1 : bit_vector ( 63 downto 0);`
61			`signal ikey : bit_vector ( 15 downto 0);`
62			`signal ipt : bit_vector ( 31 downto 0);`
63			`signal iptt : bit_vector ( 31 downto 0);`
64			`signal r : bit_vector ( 31 downto 0);`
65			`signal l : bit_vector ( 31 downto 0);`
66			`signal ir : bit_vector ( 31 downto 0);`
67			`signal il : bit_vector ( 31 downto 0);`
68			`signal F : bit_vector ( 31 downto 0);`
69			`signal FL : bit_vector ( 31 downto 0);`
70			`signal FLl : bit_vector ( 15 downto 0);`
71			`signal FLr : bit_vector ( 15 downto 0);`
72			`signal FL0 : bit_vector ( 15 downto 0);`
73			`signal FL1 : bit_vector ( 15 downto 0);`
74			`signal LFL : bit_vector ( 15 downto 0);`
75			`signal RFL : bit_vector ( 15 downto 0);`
76			`signal FO : bit_vector ( 15 downto 0);`
77			`signal FI : bit_vector ( 15 downto 0);`
78			`signal x7a : bit_vector ( 6 downto 0);`
79			`signal x9a : bit_vector ( 8 downto 0);`
80			`signal x7b : bit_vector ( 6 downto 0);`
81			`signal x9b : bit_vector ( 8 downto 0);`
82			`signal y7a : bit_vector ( 6 downto 0);`
83			`signal y9a : bit_vector ( 8 downto 0);`
84			`signal y7b : bit_vector ( 6 downto 0);`
85			`signal y9b : bit_vector ( 8 downto 0);`
86			`signal st : bit_vector ( 3 downto 0); -- 16 states`
87			`signal c3b : bit_vector ( 2 downto 0);`
88			`signal c3b_cr : bit_vector ( 2 downto 0);`
89			`signal c3b_rst : bit;`
90			`signal rnd : bit_vector ( 1 downto 0);`
91			`signal rnd_cr : bit_vector ( 1 downto 0);`
92			`signal rnd_rst : bit;`
93			`signal even : bit;`
94			`signal vld : bit;`
95			`signal ildpt : bit;`
96			`signal ildpt_rst : bit;`
97			`signal ildptt : bit;`
98
99			`component sbox`
100			`port (`
101			`x7 : in bit_vector ( 6 downto 0);`
102			`x9 : in bit_vector ( 8 downto 0);`
103			`y7 : out bit_vector ( 6 downto 0);`
104			`y9 : out bit_vector ( 8 downto 0)`
105			`);`
106			`end component;`
107
108			`component keyschedule`
109			`port (`
110			`key : in bit_vector ( 63 downto 0);`
111			`st : in bit_vector ( 3 downto 0);`
112			`ldk : in bit;`
113			`rk : out bit_vector ( 15 downto 0);`
114			`clk : in bit;`
115			`rst : in bit`
116			`);`
117			`end component;`
118
119			`begin`
120
121			`s1 : sbox`
122			`port map (`
123			`x7 => x7a,`
124			`x9 => x9a,`
125			`y7 => y7a,`
126			`y9 => y9a`
127			`);`
128			`s2 : sbox`
129			`port map (`
130			`x7 => x7b,`
131			`x9 => x9b,`
132			`y7 => y7b,`
133			`y9 => y9b`
134			`);`
135			`roundkey : keyschedule`
136			`port map (`
137			`key => key,`
138			`st => st,`
139			`ldk => ldk,`
140			`rk => ikey,`
141			`clk => clk,`
142			`rst => rst`
143			`);`
144
145			`--probe`
146			`--L_prb <= l;`
147			`--R_prb <= r;`
148			`--ikey_prb <= ikey;`
149			`--FL_prb <= FL;`
150			`--FI_prb <= FI;`
151			`--FO_prb <= FO;`
152			`--st_prb <= st;`
153			`--rnd_prb <= rnd;`
154			`--even_prb <= even;`
155			`--probe`
156
157			`process (clk)`
158			`begin`
159			`if ((clk = '1') and clk'event) then`
160			`if (rst = '1') then`
161			`ildpt <= '0';`
162			`ildptt <= '0';`
163			`ipt <= (others => '0');`
164			`-- ikey <= (others => '0');`
165			`iptt <= (others => '0');`
166			`else`
167			`ildptt <= ldpt;`
168			`ildpt <= ildptt;`
169			`iptt <= pt;`
170			`ipt <= iptt;`
171			`-- ikey <= key;`
172			`end if;`
173			`end if;`
174			`end process;`
175
176			`process (clk)`
177			`begin`
178			`if ((clk = '1') and clk'event) then`
179			`if (rst = '1') then`
180			`even <= '0';`
181			`elsif (c3b = O"7") then`
182			`even <= not(even);`
183			`end if;`
184			`end if;`
185			`end process;`
186
187			`c3b_cr(0) <= '0'; -- LSB always zero`
188			`c3b_cr( 2 downto 1) <= ( ((c3b( 1 downto 0) and B"01") or (c3b( 1 downto 0) and c3b_cr( 1 downto 0))) or (B"01" and c3b_cr( 1 downto 0)) );`
189
190			`process (clk)`
191			`begin`
192			`if (clk = '1' and clk'event) then`
193			`if (c3b_rst = '1') then`
194			`c3b <= B"000";`
195			`else`
196			`c3b <= ((c3b xor B"001") xor c3b_cr);`
197			`end if;`
198			`end if;`
199			`end process;`
200
201			`ildpt_rst <= ((ildpt xor ildptt) and ildpt);`
202			`c3b_rst <= rst or ildpt_rst;`
203
204			`l <= ireg1( 63 downto 32);`
205			`r <= ireg1( 31 downto 0);`
206
207			`--0-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+`
208			`--1-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+`
209			`--2-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+`
210			`--3-FL-FL-FO-FI-FO-FI-FO-FI+FO-FI-FO-FI-FO-FI-FL-FL+`
211
212			`st <= even & c3b;`
213			`process (st,rst,FL,FO,FI,FL0,FL1,r)`
214			`begin`
215			`if (rst = '1') then`
216			`LFL <= (others => '0');`
217			`RFL <= (others => '0');`
218			`else`
219			`case st is`
220			`when X"0" =>`
221			`LFL <= FL(31 downto 16);`
222			`RFL <= FL0;`
223			`when X"1" =>`
224			`LFL <= FL1;`
225			`RFL <= FL(15 downto 0);`
226			`when X"2" =>`
227			`LFL <= FO;`
228			`RFL <= FL(15 downto 0);`
229			`when X"3" =>`
230			`LFL <= FL(15 downto 0);`
231			`RFL <= FI xor FL(15 downto 0);`
232			`when X"4" =>`
233			`LFL <= FO;`
234			`RFL <= FL(15 downto 0);`
235			`when X"5" =>`
236			`LFL <= FL(15 downto 0);`
237			`RFL <= FI xor FL(15 downto 0);`
238			`when X"6" =>`
239			`LFL <= FO;`
240			`RFL <= FL(15 downto 0);`
241			`when X"7" =>`
242			`LFL <= FL(15 downto 0) xor r(31 downto 16); -- xor R`
243			`RFL <= FI xor FL(15 downto 0) xor r(15 downto 0); -- xor R`
244			`when X"8" =>`
245			`LFL <= FO;`
246			`RFL <= FL(15 downto 0);`
247			`when X"9" =>`
248			`LFL <= FL(15 downto 0);`
249			`RFL <= FI xor FL(15 downto 0);`
250			`when X"a" =>`
251			`LFL <= FO;`
252			`RFL <= FL(15 downto 0);`
253			`when X"b" =>`
254			`LFL <= FL(15 downto 0);`
255			`RFL <= FI xor FL(15 downto 0);`
256			`when X"c" =>`
257			`LFL <= FO;`
258			`RFL <= FL(15 downto 0);`
259			`when X"d" =>`
260			`LFL <= FL(15 downto 0);`
261			`RFL <= FI xor FL(15 downto 0);`
262			`when X"e" =>`
263			`LFL <= FL(31 downto 16);`
264			`RFL <= FL0;`
265			`when X"f" =>`
266			`LFL <= FL1 xor r(31 downto 16); -- xor R`
267			`RFL <= FL(15 downto 0) xor r(15 downto 0); -- xor R`
268			`end case;`
269			`end if;`
270			`end process;`
271
272			`FLl <= l(31 downto 16) when even = '0' else FL(31 downto 16);`
273			`FLr <= l(15 downto 0) when even = '0' else FL(15 downto 0);`
274			`--FL(R') == FL(R) xor ROTL1{FL(L) and KLi1}`
275			`FL0 <= FLr xor ((FLl(14 downto 0) and ikey(14 downto 0)) & (FLl(15) and ikey(15)));`
276			`--FL(L') == FL(L) xor ROTL1{FL(R') or KLi2}`
277			`FL1 <= FLl xor ((FL (14 downto 0) or ikey(14 downto 0)) & (FL (15) or ikey(15)));`
278
279			`process (clk)`
280			`begin`
281			`if ((clk = '1') and clk'event) then`
282			`if (rst = '1') then`
283			`FL <= (others => '0');`
284			`else`
285			`FL <= LFL & RFL;`
286			`end if;`
287			`end if;`
288			`end process;`
289
290			`--FO == Lj-1 xor KOij`
291			`FO <= FL(31 downto 16) xor ikey(15 downto 0);`
292
293			`--FI-function`
294			`-- L1 == R0 R1 == S9[L0] xor ZE(R0)`
295			`-- L2 == R1 xor KIij2 R2 == S7[L1] xor TR(R1) xor KIij1`
296			`-- L3 == R2 R3 == S9[L2] xor ZE(R2)`
297			`-- L4 == S7[L3] xor TR(R3) R4 == R3`
298			`-- Return L4 \|\| R4`
299
300			`--L0`
301			`x9a <= FL(31 downto 23);`
302			`--R0`
303			`x7a <= FL(22 downto 16);`
304			`--L2 == S9[L0] xor ZE (R0) xor KIi,j,2 (9 bit)`
305			`x9b <= y9a(8 downto 0) xor (B"00" & x7a) xor ikey( 8 downto 0);`
306			`--R2 == S7[L1] xor TR(R1) xor KIi,j,1 (7 bit)`
307			`x7b <= y7a xor y9a(6 downto 0) xor x7a xor ikey(15 downto 9);`
308			`--R3 == S9[L2] xor ZE (R2)`
309			`FI( 8 downto 0) <= y9b(8 downto 0) xor (B"00" & x7b);`
310			`--L4 == S7[L3] xor TR(R3)`
311			`FI(15 downto 9) <= y7b xor FI(6 downto 0);`
312			`--Rj == FI(Lj-1 xor KOij, KIij) xor Rj-1`
313
314			`il <= LFL & RFL;`
315			`--R' == Li-1`
316			`ir <= l;`
317
318			`process (clk)`
319			`begin`
320			`if ((clk = '1') and clk'event) then`
321			`if (rst = '1') then`
322			`ireg1 <= (others => '0');`
323			`elsif (ildpt = '1') then`
324			`ireg1 <= ireg1( 31 downto 0) & ipt;`
325			`elsif (c3b = O"7") then`
326			`ireg1(31 downto 0)<= ir;`
327			`ireg1(63 downto 32)<= il;`
328			`end if;`
329			`end if;`
330			`end process;`
331
332			`rnd_cr <= rnd(0) & '0';`
333			`process (clk)`
334			`begin`
335			`if ((clk = '1') and clk'event) then`
336			`if (rst = '1') then`
337			`rnd <= B"00";`
338			`elsif (st = X"f") then`
339			`rnd <= ((rnd xor B"01") xor rnd_cr);`
340			`end if;`
341			`end if;`
342			`end process;`
343
344			`process (clk)`
345			`begin`
346			`if ((clk = '1') and clk'event) then`
347			`if (rst = '1') then`
348			`vld <= '0';`
349			`elsif ((rnd & st) = B"111111") then`
350			`vld <= '1';`
351			`else`
352			`vld <= '0';`
353			`end if;`
354			`end if;`
355			`end process;`
356
357			`v <= vld;`
358			`ct <= l & r;`
359
360			`end phy;`