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[/] [nlprg/] [trunk/] [nlprg/] [rtl/] [nlprg16.v] - Blame information for rev 4

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/*
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 * Generated by Digital. Don't modify this file!
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 * Any changes will be lost if this file is regenerated.
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 */
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module DIG_D_FF_AS_1bit
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#(
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    parameter Default = 0
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)
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(
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   input Set,
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   input D,
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   input C,
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   input Clr,
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   output Q,
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   output \~Q
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);
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    reg state;
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    assign Q = state;
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    assign \~Q  = ~state;
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    always @ (posedge C or posedge Clr or posedge Set)
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    begin
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        if (Set)
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            state <= 1'b1;
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        else if (Clr)
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            state <= 'h0;
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        else
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            state <= D;
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    end
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    initial begin
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        state = Default;
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    end
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endmodule
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module nlprg16 (
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  input ck,
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  input rst,
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  output [15:0] o
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);
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  wire o0;
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  wire s0;
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  wire s1;
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  wire o5;
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  wire o1;
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  wire s2;
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  wire o2;
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  wire s3;
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  wire o3;
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  wire s4;
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  wire o4;
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  wire s5;
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  wire o7;
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  wire o6;
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  wire o8;
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  wire o9;
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  wire o10;
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  wire o11;
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  wire o12;
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  wire o13;
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  wire o14;
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  wire o15;
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i0 (
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    .Set( 1'b0 ),
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    .D( s1 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o0 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i1 (
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    .Set( 1'b0 ),
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    .D( s0 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o1 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i2 (
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    .Set( 1'b0 ),
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    .D( s2 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o2 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i3 (
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    .Set( 1'b0 ),
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    .D( s3 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o3 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i4 (
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    .Set( 1'b0 ),
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    .D( s4 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o4 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i5 (
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    .Set( 1'b0 ),
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    .D( s5 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o5 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i6 (
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    .Set( 1'b0 ),
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    .D( o5 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o6 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i7 (
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    .Set( 1'b0 ),
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    .D( o6 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o7 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i8 (
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    .Set( 1'b0 ),
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    .D( o7 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o8 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i9 (
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    .Set( 1'b0 ),
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    .D( o8 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o9 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i10 (
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    .Set( 1'b0 ),
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    .D( o9 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o10 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i11 (
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    .Set( 1'b0 ),
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    .D( o10 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o11 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i12 (
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    .Set( 1'b0 ),
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    .D( o11 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o12 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i13 (
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    .Set( 1'b0 ),
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    .D( o12 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o13 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i14 (
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    .Set( 1'b0 ),
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    .D( o13 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o14 )
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  );
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  DIG_D_FF_AS_1bit #(
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    .Default(0)
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  )
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  DIG_D_FF_AS_1bit_i15 (
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    .Set( 1'b0 ),
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    .D( o14 ),
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    .C( ck ),
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    .Clr( rst ),
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    .Q( o15 )
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  );
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  assign s0 = ((o12 ^ o13) ^ o0);
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  assign s1 = ~ ((o14 ^ o15) ^ o5);
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  assign s2 = ((o10 ^ o11) ^ o1);
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  assign s3 = ((o8 ^ o9) ^ o2);
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  assign s4 = ((o6 ^ o7) ^ o3);
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  assign s5 = (~ (o7 ^ o4) ^ (((o3 & o2) & (o1 & o0)) & ((((~ (o15 | o14) & ~ (o13 | o12)) & (~ (o11 | o10) & ~ (o9 | o8))) & ~ (o7 | o6)) & ~ o5)));
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  assign o[0] = o0;
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  assign o[1] = o1;
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  assign o[2] = o2;
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  assign o[3] = o3;
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  assign o[4] = o4;
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  assign o[5] = o5;
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  assign o[6] = o6;
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  assign o[7] = o7;
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  assign o[8] = o8;
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  assign o[9] = o9;
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  assign o[10] = o10;
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  assign o[11] = o11;
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  assign o[12] = o12;
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  assign o[13] = o13;
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  assign o[14] = o14;
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  assign o[15] = o15;
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endmodule

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