OpenCores
URL https://opencores.org/ocsvn/nlprg/nlprg/trunk

Subversion Repositories nlprg

[/] [nlprg/] [trunk/] [nlprg/] [tb/] [a.out] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 fra93
#! /usr/bin/vvp
2
:ivl_version "10.1 (stable)";
3
:ivl_delay_selection "TYPICAL";
4
:vpi_time_precision + 0;
5
:vpi_module "system";
6
:vpi_module "vhdl_sys";
7
:vpi_module "v2005_math";
8
:vpi_module "va_math";
9
S_0x7fffc966aed0 .scope module, "prng4_tb" "prng4_tb" 2 3;
10
 .timescale 0 0;
11
P_0x7fffc966d710 .param/l "N" 0 2 5, +C4<00000000000000000000000000000100>;
12
L_0x7f688a980138 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>;
13
v0x7fffc96915a0_0 .net/2u *"_s0", 3 0, L_0x7f688a980138;  1 drivers
14
L_0x7f688a980180 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>;
15
v0x7fffc9691680_0 .net/2u *"_s4", 3 0, L_0x7f688a980180;  1 drivers
16
v0x7fffc9691760_0 .var "ck", 0 0;
17
v0x7fffc9691800_0 .var "cnt", 3 0;
18
v0x7fffc96918c0_0 .net "cnt_start_state", 0 0, L_0x7fffc9693690;  1 drivers
19
v0x7fffc96919d0_0 .var "endsim", 0 0;
20
v0x7fffc9691a90_0 .var/i "f", 31 0;
21
v0x7fffc9691b70_0 .net "o", 3 0, L_0x7fffc96932d0;  1 drivers
22
v0x7fffc9691c30_0 .var "pass", 0 0;
23
v0x7fffc9691d60_0 .net "prng_start_state", 0 0, L_0x7fffc96935a0;  1 drivers
24
v0x7fffc9691e20_0 .var "rst", 0 0;
25
v0x7fffc9691ec0_0 .var "rst_d0", 0 0;
26
v0x7fffc9691f80_0 .var "rst_d1", 0 0;
27
E_0x7fffc9663260 .event posedge, v0x7fffc968dc60_0, v0x7fffc96658a0_0;
28
L_0x7fffc96935a0 .cmp/eq 4, L_0x7fffc96932d0, L_0x7f688a980138;
29
L_0x7fffc9693690 .cmp/eq 4, v0x7fffc9691800_0, L_0x7f688a980180;
30
S_0x7fffc966a5f0 .scope begin, "cnt_process" "cnt_process" 2 51, 2 51 0, S_0x7fffc966aed0;
31
 .timescale 0 0;
32
S_0x7fffc9663fa0 .scope begin, "display_process" "display_process" 2 109, 2 109 0, S_0x7fffc966aed0;
33
 .timescale 0 0;
34
S_0x7fffc966f0f0 .scope begin, "lock_process" "lock_process" 2 88, 2 88 0, S_0x7fffc966aed0;
35
 .timescale 0 0;
36
S_0x7fffc96667d0 .scope module, "nlprg4_u" "nlprg4" 2 14, 3 38 0, S_0x7fffc966aed0;
37
 .timescale 0 0;
38
    .port_info 0 /INPUT 1 "ck"
39
    .port_info 1 /INPUT 1 "rst"
40
    .port_info 2 /OUTPUT 4 "o"
41
L_0x7fffc9692700 .functor XOR 1, L_0x7fffc96921e0, L_0x7fffc9692550, C4<0>, C4<0>;
42
L_0x7fffc9692830 .functor XOR 1, L_0x7fffc9692700, L_0x7fffc9692390, C4<0>, C4<0>;
43
L_0x7fffc9692960 .functor NOT 1, L_0x7fffc9692830, C4<0>, C4<0>, C4<0>;
44
L_0x7fffc9692a20 .functor XOR 1, L_0x7fffc96921e0, L_0x7fffc9692040, C4<0>, C4<0>;
45
L_0x7fffc9692a90 .functor NOT 1, L_0x7fffc9692a20, C4<0>, C4<0>, C4<0>;
46
L_0x7fffc9692b50 .functor OR 1, L_0x7fffc9692550, L_0x7fffc96921e0, C4<0>, C4<0>;
47
L_0x7fffc9692c50 .functor NOT 1, L_0x7fffc9692b50, C4<0>, C4<0>, C4<0>;
48
L_0x7fffc9692cc0 .functor NOT 1, L_0x7fffc9692390, C4<0>, C4<0>, C4<0>;
49
L_0x7fffc9692d80 .functor AND 1, L_0x7fffc9692c50, L_0x7fffc9692cc0, C4<1>, C4<1>;
50
L_0x7fffc9692ec0 .functor XOR 1, L_0x7fffc9692a90, L_0x7fffc9692d80, C4<0>, C4<0>;
51
L_0x7fffc9693080 .functor BUFZ 1, L_0x7fffc9692040, C4<0>, C4<0>, C4<0>;
52
L_0x7fffc9693180 .functor BUFZ 1, L_0x7fffc9692390, C4<0>, C4<0>, C4<0>;
53
L_0x7fffc9693260 .functor BUFZ 1, L_0x7fffc96921e0, C4<0>, C4<0>, C4<0>;
54
L_0x7fffc9693410 .functor BUFZ 1, L_0x7fffc9692550, C4<0>, C4<0>, C4<0>;
55
v0x7fffc96900c0_0 .net *"_s10", 0 0, L_0x7fffc9692830;  1 drivers
56
v0x7fffc96901c0_0 .net *"_s14", 0 0, L_0x7fffc9692a20;  1 drivers
57
v0x7fffc96902a0_0 .net *"_s16", 0 0, L_0x7fffc9692a90;  1 drivers
58
v0x7fffc9690360_0 .net *"_s18", 0 0, L_0x7fffc9692b50;  1 drivers
59
v0x7fffc9690440_0 .net *"_s20", 0 0, L_0x7fffc9692c50;  1 drivers
60
v0x7fffc9690570_0 .net *"_s22", 0 0, L_0x7fffc9692cc0;  1 drivers
61
v0x7fffc9690650_0 .net *"_s24", 0 0, L_0x7fffc9692d80;  1 drivers
62
v0x7fffc9690730_0 .net *"_s31", 0 0, L_0x7fffc9693080;  1 drivers
63
v0x7fffc9690810_0 .net *"_s35", 0 0, L_0x7fffc9693180;  1 drivers
64
v0x7fffc9690980_0 .net *"_s39", 0 0, L_0x7fffc9693260;  1 drivers
65
v0x7fffc9690a60_0 .net *"_s44", 0 0, L_0x7fffc9693410;  1 drivers
66
v0x7fffc9690b40_0 .net *"_s8", 0 0, L_0x7fffc9692700;  1 drivers
67
v0x7fffc9690c20_0 .net "ck", 0 0, v0x7fffc9691760_0;  1 drivers
68
v0x7fffc9690d50_0 .net "o", 3 0, L_0x7fffc96932d0;  alias, 1 drivers
69
v0x7fffc9690e30_0 .net "o0", 0 0, L_0x7fffc9692040;  1 drivers
70
v0x7fffc9690ed0_0 .net "o1", 0 0, L_0x7fffc9692390;  1 drivers
71
v0x7fffc9690f70_0 .net "o2", 0 0, L_0x7fffc96921e0;  1 drivers
72
v0x7fffc9691120_0 .net "o3", 0 0, L_0x7fffc9692550;  1 drivers
73
v0x7fffc96911c0_0 .net "rst", 0 0, v0x7fffc9691e20_0;  1 drivers
74
v0x7fffc9691260_0 .net "s0", 0 0, L_0x7fffc9692960;  1 drivers
75
v0x7fffc9691300_0 .net "s1", 0 0, L_0x7fffc9692ec0;  1 drivers
76
L_0x7fffc96932d0 .concat8 [ 1 1 1 1], L_0x7fffc9693080, L_0x7fffc9693180, L_0x7fffc9693260, L_0x7fffc9693410;
77
S_0x7fffc96651b0 .scope module, "DIG_D_FF_AS_1bit_i0" "DIG_D_FF_AS_1bit" 3 52, 3 6 0, S_0x7fffc96667d0;
78
 .timescale 0 0;
79
    .port_info 0 /INPUT 1 "Set"
80
    .port_info 1 /INPUT 1 "D"
81
    .port_info 2 /INPUT 1 "C"
82
    .port_info 3 /INPUT 1 "Clr"
83
    .port_info 4 /OUTPUT 1 "Q"
84
    .port_info 5 /OUTPUT 1 "~Q"
85
P_0x7fffc9665600 .param/l "Default" 0 3 8, +C4<00000000000000000000000000000000>;
86
L_0x7fffc9692040 .functor BUFZ 1, v0x7fffc968dfc0_0, C4<0>, C4<0>, C4<0>;
87
L_0x7fffc96920d0 .functor NOT 1, v0x7fffc968dfc0_0, C4<0>, C4<0>, C4<0>;
88
v0x7fffc96658a0_0 .net "C", 0 0, v0x7fffc9691760_0;  alias, 1 drivers
89
v0x7fffc968dc60_0 .net "Clr", 0 0, v0x7fffc9691e20_0;  alias, 1 drivers
90
v0x7fffc968dd20_0 .net "D", 0 0, L_0x7fffc9692960;  alias, 1 drivers
91
v0x7fffc968ddf0_0 .net "Q", 0 0, L_0x7fffc9692040;  alias, 1 drivers
92
L_0x7f688a980018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
93
v0x7fffc968deb0_0 .net "Set", 0 0, L_0x7f688a980018;  1 drivers
94
v0x7fffc968dfc0_0 .var "state", 0 0;
95
v0x7fffc968e080_0 .net "~Q", 0 0, L_0x7fffc96920d0;  1 drivers
96
E_0x7fffc9663e40 .event posedge, v0x7fffc968deb0_0, v0x7fffc968dc60_0, v0x7fffc96658a0_0;
97
S_0x7fffc968e240 .scope module, "DIG_D_FF_AS_1bit_i1" "DIG_D_FF_AS_1bit" 3 62, 3 6 0, S_0x7fffc96667d0;
98
 .timescale 0 0;
99
    .port_info 0 /INPUT 1 "Set"
100
    .port_info 1 /INPUT 1 "D"
101
    .port_info 2 /INPUT 1 "C"
102
    .port_info 3 /INPUT 1 "Clr"
103
    .port_info 4 /OUTPUT 1 "Q"
104
    .port_info 5 /OUTPUT 1 "~Q"
105
P_0x7fffc968e430 .param/l "Default" 0 3 8, +C4<00000000000000000000000000000000>;
106
L_0x7fffc96921e0 .functor BUFZ 1, v0x7fffc968e9f0_0, C4<0>, C4<0>, C4<0>;
107
L_0x7fffc9692250 .functor NOT 1, v0x7fffc968e9f0_0, C4<0>, C4<0>, C4<0>;
108
v0x7fffc968e5d0_0 .net "C", 0 0, v0x7fffc9691760_0;  alias, 1 drivers
109
v0x7fffc968e6c0_0 .net "Clr", 0 0, v0x7fffc9691e20_0;  alias, 1 drivers
110
v0x7fffc968e790_0 .net "D", 0 0, L_0x7fffc9692390;  alias, 1 drivers
111
v0x7fffc968e860_0 .net "Q", 0 0, L_0x7fffc96921e0;  alias, 1 drivers
112
L_0x7f688a980060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
113
v0x7fffc968e900_0 .net "Set", 0 0, L_0x7f688a980060;  1 drivers
114
v0x7fffc968e9f0_0 .var "state", 0 0;
115
v0x7fffc968eab0_0 .net "~Q", 0 0, L_0x7fffc9692250;  1 drivers
116
E_0x7fffc968e570 .event posedge, v0x7fffc968e900_0, v0x7fffc968dc60_0, v0x7fffc96658a0_0;
117
S_0x7fffc968ec70 .scope module, "DIG_D_FF_AS_1bit_i2" "DIG_D_FF_AS_1bit" 3 72, 3 6 0, S_0x7fffc96667d0;
118
 .timescale 0 0;
119
    .port_info 0 /INPUT 1 "Set"
120
    .port_info 1 /INPUT 1 "D"
121
    .port_info 2 /INPUT 1 "C"
122
    .port_info 3 /INPUT 1 "Clr"
123
    .port_info 4 /OUTPUT 1 "Q"
124
    .port_info 5 /OUTPUT 1 "~Q"
125
P_0x7fffc968ee40 .param/l "Default" 0 3 8, +C4<00000000000000000000000000000000>;
126
L_0x7fffc9692390 .functor BUFZ 1, v0x7fffc968f470_0, C4<0>, C4<0>, C4<0>;
127
L_0x7fffc9692430 .functor NOT 1, v0x7fffc968f470_0, C4<0>, C4<0>, C4<0>;
128
v0x7fffc968f040_0 .net "C", 0 0, v0x7fffc9691760_0;  alias, 1 drivers
129
v0x7fffc968f130_0 .net "Clr", 0 0, v0x7fffc9691e20_0;  alias, 1 drivers
130
v0x7fffc968f240_0 .net "D", 0 0, L_0x7fffc9692ec0;  alias, 1 drivers
131
v0x7fffc968f2e0_0 .net "Q", 0 0, L_0x7fffc9692390;  alias, 1 drivers
132
L_0x7f688a9800a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
133
v0x7fffc968f380_0 .net "Set", 0 0, L_0x7f688a9800a8;  1 drivers
134
v0x7fffc968f470_0 .var "state", 0 0;
135
v0x7fffc968f530_0 .net "~Q", 0 0, L_0x7fffc9692430;  1 drivers
136
E_0x7fffc968eee0 .event posedge, v0x7fffc968f380_0, v0x7fffc968dc60_0, v0x7fffc96658a0_0;
137
S_0x7fffc968f6f0 .scope module, "DIG_D_FF_AS_1bit_i3" "DIG_D_FF_AS_1bit" 3 82, 3 6 0, S_0x7fffc96667d0;
138
 .timescale 0 0;
139
    .port_info 0 /INPUT 1 "Set"
140
    .port_info 1 /INPUT 1 "D"
141
    .port_info 2 /INPUT 1 "C"
142
    .port_info 3 /INPUT 1 "Clr"
143
    .port_info 4 /OUTPUT 1 "Q"
144
    .port_info 5 /OUTPUT 1 "~Q"
145
P_0x7fffc968f8c0 .param/l "Default" 0 3 8, +C4<00000000000000000000000000000000>;
146
L_0x7fffc9692550 .functor BUFZ 1, v0x7fffc968fe60_0, C4<0>, C4<0>, C4<0>;
147
L_0x7fffc9692610 .functor NOT 1, v0x7fffc968fe60_0, C4<0>, C4<0>, C4<0>;
148
v0x7fffc968fa80_0 .net "C", 0 0, v0x7fffc9691760_0;  alias, 1 drivers
149
v0x7fffc968fb40_0 .net "Clr", 0 0, v0x7fffc9691e20_0;  alias, 1 drivers
150
v0x7fffc968fc00_0 .net "D", 0 0, L_0x7fffc96921e0;  alias, 1 drivers
151
v0x7fffc968fcd0_0 .net "Q", 0 0, L_0x7fffc9692550;  alias, 1 drivers
152
L_0x7f688a9800f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
153
v0x7fffc968fd70_0 .net "Set", 0 0, L_0x7f688a9800f0;  1 drivers
154
v0x7fffc968fe60_0 .var "state", 0 0;
155
v0x7fffc968ff00_0 .net "~Q", 0 0, L_0x7fffc9692610;  1 drivers
156
E_0x7fffc968fa00 .event posedge, v0x7fffc968fd70_0, v0x7fffc968dc60_0, v0x7fffc96658a0_0;
157
S_0x7fffc96913d0 .scope begin, "reset_delay_process" "reset_delay_process" 2 63, 2 63 0, S_0x7fffc966aed0;
158
 .timescale 0 0;
159
    .scope S_0x7fffc96651b0;
160
T_0 ;
161
    %wait E_0x7fffc9663e40;
162
    %load/vec4 v0x7fffc968deb0_0;
163
    %flag_set/vec4 8;
164
    %jmp/0xz  T_0.0, 8;
165
    %pushi/vec4 1, 0, 1;
166
    %assign/vec4 v0x7fffc968dfc0_0, 0;
167
    %jmp T_0.1;
168
T_0.0 ;
169
    %load/vec4 v0x7fffc968dc60_0;
170
    %flag_set/vec4 8;
171
    %jmp/0xz  T_0.2, 8;
172
    %pushi/vec4 0, 0, 1;
173
    %assign/vec4 v0x7fffc968dfc0_0, 0;
174
    %jmp T_0.3;
175
T_0.2 ;
176
    %load/vec4 v0x7fffc968dd20_0;
177
    %assign/vec4 v0x7fffc968dfc0_0, 0;
178
T_0.3 ;
179
T_0.1 ;
180
    %jmp T_0;
181
    .thread T_0;
182
    .scope S_0x7fffc96651b0;
183
T_1 ;
184
    %pushi/vec4 0, 0, 1;
185
    %store/vec4 v0x7fffc968dfc0_0, 0, 1;
186
    %end;
187
    .thread T_1;
188
    .scope S_0x7fffc968e240;
189
T_2 ;
190
    %wait E_0x7fffc968e570;
191
    %load/vec4 v0x7fffc968e900_0;
192
    %flag_set/vec4 8;
193
    %jmp/0xz  T_2.0, 8;
194
    %pushi/vec4 1, 0, 1;
195
    %assign/vec4 v0x7fffc968e9f0_0, 0;
196
    %jmp T_2.1;
197
T_2.0 ;
198
    %load/vec4 v0x7fffc968e6c0_0;
199
    %flag_set/vec4 8;
200
    %jmp/0xz  T_2.2, 8;
201
    %pushi/vec4 0, 0, 1;
202
    %assign/vec4 v0x7fffc968e9f0_0, 0;
203
    %jmp T_2.3;
204
T_2.2 ;
205
    %load/vec4 v0x7fffc968e790_0;
206
    %assign/vec4 v0x7fffc968e9f0_0, 0;
207
T_2.3 ;
208
T_2.1 ;
209
    %jmp T_2;
210
    .thread T_2;
211
    .scope S_0x7fffc968e240;
212
T_3 ;
213
    %pushi/vec4 0, 0, 1;
214
    %store/vec4 v0x7fffc968e9f0_0, 0, 1;
215
    %end;
216
    .thread T_3;
217
    .scope S_0x7fffc968ec70;
218
T_4 ;
219
    %wait E_0x7fffc968eee0;
220
    %load/vec4 v0x7fffc968f380_0;
221
    %flag_set/vec4 8;
222
    %jmp/0xz  T_4.0, 8;
223
    %pushi/vec4 1, 0, 1;
224
    %assign/vec4 v0x7fffc968f470_0, 0;
225
    %jmp T_4.1;
226
T_4.0 ;
227
    %load/vec4 v0x7fffc968f130_0;
228
    %flag_set/vec4 8;
229
    %jmp/0xz  T_4.2, 8;
230
    %pushi/vec4 0, 0, 1;
231
    %assign/vec4 v0x7fffc968f470_0, 0;
232
    %jmp T_4.3;
233
T_4.2 ;
234
    %load/vec4 v0x7fffc968f240_0;
235
    %assign/vec4 v0x7fffc968f470_0, 0;
236
T_4.3 ;
237
T_4.1 ;
238
    %jmp T_4;
239
    .thread T_4;
240
    .scope S_0x7fffc968ec70;
241
T_5 ;
242
    %pushi/vec4 0, 0, 1;
243
    %store/vec4 v0x7fffc968f470_0, 0, 1;
244
    %end;
245
    .thread T_5;
246
    .scope S_0x7fffc968f6f0;
247
T_6 ;
248
    %wait E_0x7fffc968fa00;
249
    %load/vec4 v0x7fffc968fd70_0;
250
    %flag_set/vec4 8;
251
    %jmp/0xz  T_6.0, 8;
252
    %pushi/vec4 1, 0, 1;
253
    %assign/vec4 v0x7fffc968fe60_0, 0;
254
    %jmp T_6.1;
255
T_6.0 ;
256
    %load/vec4 v0x7fffc968fb40_0;
257
    %flag_set/vec4 8;
258
    %jmp/0xz  T_6.2, 8;
259
    %pushi/vec4 0, 0, 1;
260
    %assign/vec4 v0x7fffc968fe60_0, 0;
261
    %jmp T_6.3;
262
T_6.2 ;
263
    %load/vec4 v0x7fffc968fc00_0;
264
    %assign/vec4 v0x7fffc968fe60_0, 0;
265
T_6.3 ;
266
T_6.1 ;
267
    %jmp T_6;
268
    .thread T_6;
269
    .scope S_0x7fffc968f6f0;
270
T_7 ;
271
    %pushi/vec4 0, 0, 1;
272
    %store/vec4 v0x7fffc968fe60_0, 0, 1;
273
    %end;
274
    .thread T_7;
275
    .scope S_0x7fffc966aed0;
276
T_8 ;
277
    %vpi_call 2 24 "$dumpfile", "./wave/prng4_tb.vcd" {0 0 0};
278
    %vpi_call 2 25 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x7fffc966aed0 {0 0 0};
279
    %end;
280
    .thread T_8;
281
    .scope S_0x7fffc966aed0;
282
T_9 ;
283
    %pushi/vec4 4294967295, 0, 32;
284
    %store/vec4 v0x7fffc9691a90_0, 0, 32;
285
    %end;
286
    .thread T_9;
287
    .scope S_0x7fffc966aed0;
288
T_10 ;
289
    %vpi_func 2 36 "$fopen" 32, "./log/prng4_tb.log", "w+" {0 0 0};
290
    %store/vec4 v0x7fffc9691a90_0, 0, 32;
291
    %pushi/vec4 1, 0, 1;
292
    %store/vec4 v0x7fffc9691e20_0, 0, 1;
293
    %delay 5, 0;
294
    %load/vec4 v0x7fffc9691e20_0;
295
    %inv;
296
    %store/vec4 v0x7fffc9691e20_0, 0, 1;
297
    %delay 5, 0;
298
    %load/vec4 v0x7fffc9691e20_0;
299
    %inv;
300
    %store/vec4 v0x7fffc9691e20_0, 0, 1;
301
    %delay 5, 0;
302
    %load/vec4 v0x7fffc9691e20_0;
303
    %inv;
304
    %store/vec4 v0x7fffc9691e20_0, 0, 1;
305
    %pushi/vec4 1, 0, 1;
306
    %store/vec4 v0x7fffc9691760_0, 0, 1;
307
T_10.0 ;
308
    %delay 5, 0;
309
    %load/vec4 v0x7fffc9691760_0;
310
    %inv;
311
    %store/vec4 v0x7fffc9691760_0, 0, 1;
312
    %jmp T_10.0;
313
    %end;
314
    .thread T_10;
315
    .scope S_0x7fffc966aed0;
316
T_11 ;
317
    %wait E_0x7fffc9663260;
318
    %fork t_1, S_0x7fffc966a5f0;
319
    %jmp t_0;
320
    .scope S_0x7fffc966a5f0;
321
t_1 ;
322
    %load/vec4 v0x7fffc9691e20_0;
323
    %flag_set/vec4 8;
324
    %jmp/0xz  T_11.0, 8;
325
    %pushi/vec4 0, 0, 4;
326
    %assign/vec4 v0x7fffc9691800_0, 0;
327
    %jmp T_11.1;
328
T_11.0 ;
329
    %load/vec4 v0x7fffc9691800_0;
330
    %addi 1, 0, 4;
331
    %assign/vec4 v0x7fffc9691800_0, 0;
332
T_11.1 ;
333
    %end;
334
    .scope S_0x7fffc966aed0;
335
t_0 %join;
336
    %jmp T_11;
337
    .thread T_11;
338
    .scope S_0x7fffc966aed0;
339
T_12 ;
340
    %wait E_0x7fffc9663260;
341
    %fork t_3, S_0x7fffc96913d0;
342
    %jmp t_2;
343
    .scope S_0x7fffc96913d0;
344
t_3 ;
345
    %load/vec4 v0x7fffc9691e20_0;
346
    %flag_set/vec4 8;
347
    %jmp/0xz  T_12.0, 8;
348
    %pushi/vec4 1, 0, 1;
349
    %assign/vec4 v0x7fffc9691ec0_0, 0;
350
    %pushi/vec4 1, 0, 1;
351
    %assign/vec4 v0x7fffc9691f80_0, 0;
352
    %jmp T_12.1;
353
T_12.0 ;
354
    %pushi/vec4 0, 0, 1;
355
    %assign/vec4 v0x7fffc9691ec0_0, 0;
356
    %load/vec4 v0x7fffc9691ec0_0;
357
    %assign/vec4 v0x7fffc9691f80_0, 0;
358
T_12.1 ;
359
    %end;
360
    .scope S_0x7fffc966aed0;
361
t_2 %join;
362
    %jmp T_12;
363
    .thread T_12;
364
    .scope S_0x7fffc966aed0;
365
T_13 ;
366
    %wait E_0x7fffc9663260;
367
    %fork t_5, S_0x7fffc966f0f0;
368
    %jmp t_4;
369
    .scope S_0x7fffc966f0f0;
370
t_5 ;
371
    %load/vec4 v0x7fffc9691e20_0;
372
    %flag_set/vec4 8;
373
    %jmp/0xz  T_13.0, 8;
374
    %pushi/vec4 0, 0, 1;
375
    %assign/vec4 v0x7fffc96919d0_0, 0;
376
    %pushi/vec4 0, 0, 1;
377
    %assign/vec4 v0x7fffc9691c30_0, 0;
378
    %jmp T_13.1;
379
T_13.0 ;
380
    %load/vec4 v0x7fffc9691d60_0;
381
    %load/vec4 v0x7fffc9691f80_0;
382
    %nor/r;
383
    %and;
384
    %flag_set/vec4 8;
385
    %jmp/0xz  T_13.2, 8;
386
    %pushi/vec4 1, 0, 1;
387
    %assign/vec4 v0x7fffc96919d0_0, 0;
388
    %pushi/vec4 0, 0, 1;
389
    %assign/vec4 v0x7fffc9691c30_0, 0;
390
    %jmp T_13.3;
391
T_13.2 ;
392
    %load/vec4 v0x7fffc96918c0_0;
393
    %load/vec4 v0x7fffc9691d60_0;
394
    %and;
395
    %load/vec4 v0x7fffc9691f80_0;
396
    %nor/r;
397
    %and;
398
    %flag_set/vec4 8;
399
    %jmp/0xz  T_13.4, 8;
400
    %pushi/vec4 1, 0, 1;
401
    %assign/vec4 v0x7fffc96919d0_0, 0;
402
    %pushi/vec4 1, 0, 1;
403
    %assign/vec4 v0x7fffc9691c30_0, 0;
404
    %jmp T_13.5;
405
T_13.4 ;
406
    %load/vec4 v0x7fffc96918c0_0;
407
    %load/vec4 v0x7fffc9691f80_0;
408
    %nor/r;
409
    %and;
410
    %flag_set/vec4 8;
411
    %jmp/0xz  T_13.6, 8;
412
    %pushi/vec4 1, 0, 1;
413
    %assign/vec4 v0x7fffc96919d0_0, 0;
414
    %pushi/vec4 0, 0, 1;
415
    %assign/vec4 v0x7fffc9691c30_0, 0;
416
T_13.6 ;
417
T_13.5 ;
418
T_13.3 ;
419
T_13.1 ;
420
    %end;
421
    .scope S_0x7fffc966aed0;
422
t_4 %join;
423
    %jmp T_13;
424
    .thread T_13;
425
    .scope S_0x7fffc966aed0;
426
T_14 ;
427
    %wait E_0x7fffc9663260;
428
    %fork t_7, S_0x7fffc9663fa0;
429
    %jmp t_6;
430
    .scope S_0x7fffc9663fa0;
431
t_7 ;
432
    %load/vec4 v0x7fffc96919d0_0;
433
    %nor/r;
434
    %load/vec4 v0x7fffc9691e20_0;
435
    %nor/r;
436
    %and;
437
    %flag_set/vec4 8;
438
    %jmp/0xz  T_14.0, 8;
439
    %vpi_call 2 112 "$fdisplay", v0x7fffc9691a90_0, "%10d %10b", v0x7fffc9691800_0, v0x7fffc9691b70_0 {0 0 0};
440
    %jmp T_14.1;
441
T_14.0 ;
442
    %load/vec4 v0x7fffc96919d0_0;
443
    %flag_set/vec4 8;
444
    %jmp/0xz  T_14.2, 8;
445
    %vpi_call 2 114 "$fclose", v0x7fffc9691a90_0 {0 0 0};
446
    %vpi_call 2 115 "$finish" {0 0 0};
447
T_14.2 ;
448
T_14.1 ;
449
    %end;
450
    .scope S_0x7fffc966aed0;
451
t_6 %join;
452
    %jmp T_14;
453
    .thread T_14;
454
# The file index is used to find the file name in the following table.
455
:file_names 4;
456
    "N/A";
457
    "";
458
    "nlprg4_tb.v";
459
    "./../rtl/nlprg4.v";

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.