Subversion Repositories nlprg

$date

        Sat Apr 18 17:08:32 2020

$end

$version

        Icarus Verilog

$end

$timescale

        1s

$end

$scope module prng8_tb $end

$var wire 1 ! prng_start_state $end

$var wire 1 " o7 $end

$var wire 1 # o6 $end

$var wire 1 $ o5 $end

$var wire 1 % o4 $end

$var wire 1 & o3 $end

$var wire 1 ' o2 $end

$var wire 1 ( o1 $end

$var wire 1 ) o0 $end

$var wire 8 * o [7:0] $end

$var wire 1 + cnt_start_state $end

$var reg 1 , ck $end

$var reg 8 - cnt [7:0] $end

$var reg 1 . endsim $end

$var reg 1 / pass $end

$var reg 1 0 rst $end

$var reg 1 1 rst_d0 $end

$var reg 1 2 rst_d1 $end

$var integer 32 3 f [31:0] $end

$scope module nlprg8_u $end

$var wire 1 , ck $end

$var wire 1 ) o0 $end

$var wire 1 ( o1 $end

$var wire 1 ' o2 $end

$var wire 1 & o3 $end

$var wire 1 % o4 $end

$var wire 1 $ o5 $end

$var wire 1 # o6 $end

$var wire 1 " o7 $end

$var wire 1 0 rst $end

$var wire 1 4 s0 $end

$var wire 1 5 s1 $end

$var wire 1 6 s2 $end

$var wire 1 7 s3 $end

$var wire 1 8 o7_temp $end

$var wire 1 9 o6_temp $end

$var wire 1 : o5_temp $end

$var wire 1 ; o4_temp $end

$var wire 1 < o3_temp $end

$var wire 1 = o2_temp $end

$var wire 1 > o1_temp $end

$var wire 1 ? o0_temp $end

$scope module dff0 $end

$var wire 1 , ck $end

$var wire 1 4 d $end

$var wire 1 0 rst $end

$var wire 1 ? q $end

$var reg 1 ? state $end

$upscope $end

$scope module dff1 $end

$var wire 1 , ck $end

$var wire 1 5 d $end

$var wire 1 0 rst $end

$var wire 1 = q $end

$var reg 1 = state $end

$upscope $end

$scope module dff2 $end

$var wire 1 , ck $end

$var wire 1 6 d $end

$var wire 1 0 rst $end

$var wire 1 > q $end

$var reg 1 > state $end

$upscope $end

$scope module dff3 $end

$var wire 1 , ck $end

$var wire 1 7 d $end

$var wire 1 0 rst $end

$var wire 1 < q $end

$var reg 1 < state $end

$upscope $end

$scope module dff4 $end

$var wire 1 , ck $end

$var wire 1 0 rst $end

$var wire 1 : q $end

$var wire 1 ; d $end

$var reg 1 : state $end

$upscope $end

$scope module dff5 $end

$var wire 1 , ck $end

$var wire 1 < d $end

$var wire 1 0 rst $end

$var wire 1 ; q $end

$var reg 1 ; state $end

$upscope $end

$scope module dff6 $end

$var wire 1 , ck $end

$var wire 1 : d $end

$var wire 1 0 rst $end

$var wire 1 9 q $end

$var reg 1 9 state $end

$upscope $end

$scope module dff7 $end

$var wire 1 , ck $end

$var wire 1 9 d $end

$var wire 1 0 rst $end

$var wire 1 8 q $end

$var reg 1 8 state $end

$upscope $end

$upscope $end

$scope begin cnt_process $end

$upscope $end

$scope begin display_process $end

$upscope $end

$scope begin end_sim_process $end

$upscope $end

$scope begin reset_delay_process $end

$upscope $end

$upscope $end

$enddefinitions $end

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