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URL https://opencores.org/ocsvn/nlprg/nlprg/trunk

Subversion Repositories nlprg

[/] [nlprg/] [trunk/] [tb/] [wave/] [prng8_tb.vcd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 fra93
$date
2
        Sat Apr 18 17:08:32 2020
3
$end
4
$version
5
        Icarus Verilog
6
$end
7
$timescale
8
        1s
9
$end
10
$scope module prng8_tb $end
11
$var wire 1 ! prng_start_state $end
12
$var wire 1 " o7 $end
13
$var wire 1 # o6 $end
14
$var wire 1 $ o5 $end
15
$var wire 1 % o4 $end
16
$var wire 1 & o3 $end
17
$var wire 1 ' o2 $end
18
$var wire 1 ( o1 $end
19
$var wire 1 ) o0 $end
20
$var wire 8 * o [7:0] $end
21
$var wire 1 + cnt_start_state $end
22
$var reg 1 , ck $end
23
$var reg 8 - cnt [7:0] $end
24
$var reg 1 . endsim $end
25
$var reg 1 / pass $end
26
$var reg 1 0 rst $end
27
$var reg 1 1 rst_d0 $end
28
$var reg 1 2 rst_d1 $end
29
$var integer 32 3 f [31:0] $end
30
$scope module nlprg8_u $end
31
$var wire 1 , ck $end
32
$var wire 1 ) o0 $end
33
$var wire 1 ( o1 $end
34
$var wire 1 ' o2 $end
35
$var wire 1 & o3 $end
36
$var wire 1 % o4 $end
37
$var wire 1 $ o5 $end
38
$var wire 1 # o6 $end
39
$var wire 1 " o7 $end
40
$var wire 1 0 rst $end
41
$var wire 1 4 s0 $end
42
$var wire 1 5 s1 $end
43
$var wire 1 6 s2 $end
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$var wire 1 7 s3 $end
45
$var wire 1 8 o7_temp $end
46
$var wire 1 9 o6_temp $end
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$var wire 1 : o5_temp $end
48
$var wire 1 ; o4_temp $end
49
$var wire 1 < o3_temp $end
50
$var wire 1 = o2_temp $end
51
$var wire 1 > o1_temp $end
52
$var wire 1 ? o0_temp $end
53
$scope module dff0 $end
54
$var wire 1 , ck $end
55
$var wire 1 4 d $end
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$var wire 1 0 rst $end
57
$var wire 1 ? q $end
58
$var reg 1 ? state $end
59
$upscope $end
60
$scope module dff1 $end
61
$var wire 1 , ck $end
62
$var wire 1 5 d $end
63
$var wire 1 0 rst $end
64
$var wire 1 = q $end
65
$var reg 1 = state $end
66
$upscope $end
67
$scope module dff2 $end
68
$var wire 1 , ck $end
69
$var wire 1 6 d $end
70
$var wire 1 0 rst $end
71
$var wire 1 > q $end
72
$var reg 1 > state $end
73
$upscope $end
74
$scope module dff3 $end
75
$var wire 1 , ck $end
76
$var wire 1 7 d $end
77
$var wire 1 0 rst $end
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$var wire 1 < q $end
79
$var reg 1 < state $end
80
$upscope $end
81
$scope module dff4 $end
82
$var wire 1 , ck $end
83
$var wire 1 0 rst $end
84
$var wire 1 : q $end
85
$var wire 1 ; d $end
86
$var reg 1 : state $end
87
$upscope $end
88
$scope module dff5 $end
89
$var wire 1 , ck $end
90
$var wire 1 < d $end
91
$var wire 1 0 rst $end
92
$var wire 1 ; q $end
93
$var reg 1 ; state $end
94
$upscope $end
95
$scope module dff6 $end
96
$var wire 1 , ck $end
97
$var wire 1 : d $end
98
$var wire 1 0 rst $end
99
$var wire 1 9 q $end
100
$var reg 1 9 state $end
101
$upscope $end
102
$scope module dff7 $end
103
$var wire 1 , ck $end
104
$var wire 1 9 d $end
105
$var wire 1 0 rst $end
106
$var wire 1 8 q $end
107
$var reg 1 8 state $end
108
$upscope $end
109
$upscope $end
110
$scope begin cnt_process $end
111
$upscope $end
112
$scope begin display_process $end
113
$upscope $end
114
$scope begin end_sim_process $end
115
$upscope $end
116
$scope begin reset_delay_process $end
117
$upscope $end
118
$upscope $end
119
$enddefinitions $end
120
#0
121
$dumpvars
122
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4078
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4092
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4097
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4098
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4099
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4119
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4280
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16
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b11110100 -
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4300
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4380
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