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[/] [noc/] [src/] [core.cc] - Blame information for rev 4

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1 4 imori
#include <systemc>
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#include <iostream>
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#include "core.h"
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#include "define.h"
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using namespace std;
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void core :: transfer_data()
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{
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        sc_uint<FIFO_DEEP>      buff;
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        sc_uint<FIFO_DEEP>      f_ct[3];
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        sc_uint<3>              channel = 0;
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        sc_uint<3>              sel = 0;
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        sc_uint<8>                              data_address = 0;
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        bool                    stop_flag = 0;
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        bool                    temp = 0;
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        bool                    ready = 0;
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        while(true){
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                if(!reset_n.read()){
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                        stop_flag = 0;
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                        f_ct[0] = f_ct[1] = f_ct[2] = 0;
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                        data_address = 0;
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                }
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                else{
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                        if(clk.read()){
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                                write_n->write(true);
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                                if(((full->read()&0x01) != 0x01) && ((write_state & FIFO1) == FIFO1)){
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                                        sel = 1;
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                                        channel = 0;
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                                        stop_flag = 0;
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                                        f_ct[channel]++;
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                                        data_address = write_address[0];
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                                }
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                                else if(((full->read()&0x02) != 0x02)&&((write_state & FIFO2) == FIFO2)){
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                                        sel = 2;
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                                        channel = 1;
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                                        stop_flag = 0;
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                                        f_ct[channel]++;
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                                        data_address = write_address[1];
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                                }
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                                else if(((full->read()&0x04) != 0x04)&&((write_state & FIFO3) == FIFO3)){
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                                        sel = 3;
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                                        channel = 2;
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                                        stop_flag = 0;
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                                        f_ct[channel]++;
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                                        data_address = write_address[2];
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                                }
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                                else{
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                                        sel = 0;
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                                        stop_flag = 1;
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                                }
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                                core_to_fifo_sel->write(sel);
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                                ready = 1;
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                        }
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                        else if((ready == 1) && (stop_flag == 0)){
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                                if(((f_ct[channel] - 1) < FIFO_DEEP)){
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                                        buff = wmemory[data_address];
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                                        temp = (bool)((buff >> (f_ct[channel] - 1)) & 0x0001);
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                                        data_out->write(temp);
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                                        wait(1,SC_NS);
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                                        write_n->write(false);
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                                        ready = 0;
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                                        EI_POWER;
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                                }
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                                if((f_ct[channel]) == FIFO_DEEP){
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#ifdef CORE_TRANSMIT_DEBUG
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                                        short debug_temp = 0;
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                                        for(int dc = 0; dc <= FIFO_DEEP; dc++){
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                                                debug_temp = wmemory[data_address];
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                                                debug_temp = debug_temp >> dc;
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                                                debug_temp &= 0x0001;
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                                                if(dc  == 0){
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                                                        cout << "Core [" << core_id << "] channel[" << channel
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                                                                << "] " << " transmit data: \t\t";
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                                                        cout << debug_temp;
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                                                }
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                                                else if(dc < FIFO_DEEP){
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                                                        cout << debug_temp;
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                                                }
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                                        }
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                                        cout << endl;
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#endif
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                                        EI_POWER;
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                                        wmemory[data_address] = 0;
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                                        f_ct[channel] = 0;
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                                        if(channel == 0){
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                                                write_state &= ~FIFO1;
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                                        }
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                                        else if(channel == 1){
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                                                write_state &= ~FIFO2;
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                                        }
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                                        else if(channel == 2){
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                                                write_state &= ~FIFO3;
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                                        }
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                                }
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                        }
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                }
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                wait();
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        }
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}
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void core :: receive_data()
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{
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        sc_uint<FIFO_DEEP>  rec_buff = 0;
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        sc_uint<FIFO_DEEP>  f_ct[3];         //fifo deep counter.
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        sc_uint<2>                      sel = 0;
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        sc_uint<2>                      channel = 0;
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        sc_uint<8>                              data_address = 0;
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        bool temp = 0;
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        bool ready = 0;
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        f_ct[0] = f_ct[1] = f_ct[2] = 0;
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        while(true){
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                wait();
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                if(!reset_n.read())
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                {
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                        f_ct[0] = f_ct[1] = f_ct[2] = 0;
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                }
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                else{
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                        if(clk.read()){
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                                read_n->write(true);
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                                if(((empty->read()&0x01) != 0x01) && ((read_state & FIFO1) == FIFO1)){
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                                        channel = 0;
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                                        sel = 1;
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                                        f_ct[channel]++;
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                                        ready = 1;
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                                        data_address = read_address[0];
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                                }
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                                else if(((empty->read()&0x02) != 0x02) && ((read_state & FIFO2) == FIFO2)){
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                                        channel = 1;
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                                        sel = 2;
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                                        f_ct[channel]++;
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                                        ready = 1;
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                                        data_address = read_address[1];
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                                }
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                                else if(((empty->read()&0x04) != 0x04) && ((read_state & FIFO3) == FIFO3)){
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                                        channel = 2;
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                                        sel = 3;
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                                        f_ct[channel]++;
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                                        ready = 1;
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                                        data_address = read_address[1];
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                                }
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                                else{
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                                        ready = 0;
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                                        sel = 0;
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                                }
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                                fifo_to_core_sel->write(sel);
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                        }
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                        else if(ready == 1){
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                                if((f_ct[channel]-1) < FIFO_DEEP){
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                                        read_n->write(false);
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                                        wait(2,SC_NS);
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                                        temp = data_in->read();
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                                        rmemory[data_address] |= (temp << (f_ct[channel]-1));
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                                        ready = 0;
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                                        EI_POWER;
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                                }
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                                if((f_ct[channel]) == (FIFO_DEEP)){
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                                        f_ct[channel] = 0;
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                                        if(channel == 0)
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                                                read_state &= ~FIFO1;
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                                        else if(channel == 1)
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                                                read_state &= ~FIFO2;
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                                        else if(channel == 2)
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                                                read_state &= ~FIFO3;
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#ifdef CORE_RECEIVE_DEBUG
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                                        short debug_temp = 0;
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                                        for(int dc = 0; dc <= FIFO_DEEP; dc++){
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                                                debug_temp = rmemory[data_address];
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                                                debug_temp = debug_temp >> dc;
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                                                debug_temp &= 0x0001;
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                                                if(dc  == 0){
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                                                        cout << "Core [" << core_id << "] channel[" << channel
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                                                                << "] " << " receive data: \t\t";
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                                                        cout << debug_temp;
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                                                }
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                                                else if(dc < FIFO_DEEP){
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                                                        cout << debug_temp;
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                                                }
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                                        }
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                                        rmemory[data_address] = 0;
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                                        cout << endl;
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#endif
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                                }
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                        }
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                }
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        }
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}
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char core :: write_data(sc_uint<3> sel, sc_uint<8> addr)
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{
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        sc_uint<3> fifo = 0;
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        if(!(write_state & sel)){
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                if(sel == FIFO1)
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                        fifo = 0;
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                else if(sel == FIFO2)
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                        fifo = 1;
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                else if(sel == FIFO3)
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                        fifo = 2;
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                else
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                        cout << "error" << endl;
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                write_address[fifo] = addr;
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                write_state |= sel;
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                return SUCCEED;
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        }
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        else
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                return FAIL;
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}
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char core :: read_data(sc_uint<3> sel, sc_uint<8> addr)
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{
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        sc_uint<3> fifo = 0;
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        if(!(read_state & sel)){
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                if(sel == FIFO1)
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                        fifo = 0;
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                else if(sel == FIFO2)
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                        fifo = 1;
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                else if(sel == FIFO3)
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                        fifo = 2;
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                read_address[fifo] = addr;
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                read_state |= sel;
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                return SUCCEED;
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        }
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        else
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                return FAIL;
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}
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void core :: core_handle()
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{
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        char state1 = FAIL, state2 = FAIL, state3 = FAIL, state4 = FAIL;
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        char state5 = FAIL, state6 = FAIL;
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        char rstate1 = 0, rstate2 = 0, rstate3 = 0;
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        unsigned int delay = 0;
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        HEAD_FLIT *head;
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        BODY_FLIT *body;
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        head = (HEAD_FLIT *)(wmemory+10); //0000 0010 1000 0000.
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        head->type = 0;
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        head->conn_type = 0;
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        head->dst_addr = 4;
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        head->pkt_size = 0;
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        body = (BODY_FLIT *)(wmemory+11);//0100 1111 1111 0000
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        body->type = 1;
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        body->data = 0x0ff0;
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        body = (BODY_FLIT *)(wmemory+12);//0100 1000 1000 0000
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        body->type = 1;
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        body->data = 0x0880;
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        //Optical interconnects 
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        head = (HEAD_FLIT *)(wmemory+13); //0010 0100 0000 0000
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        head->type = 0;
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        head->conn_type = 1;
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        head->dst_addr = 15;
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        head->pkt_size = 0;
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        body = (BODY_FLIT *)(wmemory+14); //0100 0001 0001 0000
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        body->type = 1;
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        body->data = 0x0110;
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        body = (BODY_FLIT *)(wmemory+15); //0100 1111 1111 1111
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        body->type = 1;
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        body->data = 0x0fff;
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        while(true){
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                if(!reset_n.read()){
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277
                }
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                else{
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                        if(core_id == 0){
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281
                                if(state1 == FAIL)
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                                        state1 = write_data(FIFO1,10);
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                                if(state2 == FAIL)
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                                        state2 = write_data(FIFO1,11);
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                                if(state3 == FAIL)
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                                        state3 = write_data(FIFO1,12);
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                                if(state4 == FAIL)
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                                        state4 = write_data(FIFO2,13);
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                                if(state4 == SUCCEED){
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                                        if(delay > 200){
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                                                if(state5 == FAIL)
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                                                        state5 = write_data(FIFO2,14);
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                                                if(state6 == FAIL){
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                                                        state6 = write_data(FIFO2,15);
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                                                        if(state6 == SUCCEED)
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                                                                delay = 0;
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                                                }
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                                        }
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                                        else{
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                                                delay++;
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                                        }
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                                }
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                        }
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                        rstate1 = read_data(FIFO1,0);
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                        rstate2 = read_data(FIFO2,1);
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                        rstate3 = read_data(FIFO3,2);
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                }
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                wait();
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        }
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}

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