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[/] [noc/] [src/] [core.cc] - Blame information for rev 4

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#include <systemc>
#include <iostream>
#include "core.h"
#include "define.h"
 
using namespace std;
 
void core :: transfer_data()
{
        sc_uint<FIFO_DEEP>      buff;
        sc_uint<FIFO_DEEP>      f_ct[3];
        sc_uint<3>              channel = 0;
        sc_uint<3>              sel = 0;
        sc_uint<8>                              data_address = 0;
        bool                    stop_flag = 0;
        bool                    temp = 0;
        bool                    ready = 0;
 
        while(true){
                if(!reset_n.read()){
                        stop_flag = 0;
                        f_ct[0] = f_ct[1] = f_ct[2] = 0;
                        data_address = 0;
                }
                else{
                        if(clk.read()){
                                write_n->write(true);
                                if(((full->read()&0x01) != 0x01) && ((write_state & FIFO1) == FIFO1)){
                                        sel = 1;
                                        channel = 0;
                                        stop_flag = 0;
                                        f_ct[channel]++;
                                        data_address = write_address[0];
                                }
                                else if(((full->read()&0x02) != 0x02)&&((write_state & FIFO2) == FIFO2)){
                                        sel = 2;
                                        channel = 1;
                                        stop_flag = 0;
                                        f_ct[channel]++;
                                        data_address = write_address[1];
                                }
                                else if(((full->read()&0x04) != 0x04)&&((write_state & FIFO3) == FIFO3)){
                                        sel = 3;
                                        channel = 2;
                                        stop_flag = 0;
                                        f_ct[channel]++;
                                        data_address = write_address[2];
                                }
                                else{
                                        sel = 0;
                                        stop_flag = 1;
                                }
                                core_to_fifo_sel->write(sel);
                                ready = 1;
                        }
                        else if((ready == 1) && (stop_flag == 0)){
                                if(((f_ct[channel] - 1) < FIFO_DEEP)){
                                        buff = wmemory[data_address];
                                        temp = (bool)((buff >> (f_ct[channel] - 1)) & 0x0001);
                                        data_out->write(temp);
                                        wait(1,SC_NS);
                                        write_n->write(false);
                                        ready = 0;
                                        EI_POWER;
                                }
                                if((f_ct[channel]) == FIFO_DEEP){
#ifdef CORE_TRANSMIT_DEBUG
                                        short debug_temp = 0;
                                        for(int dc = 0; dc <= FIFO_DEEP; dc++){
                                                debug_temp = wmemory[data_address];
                                                debug_temp = debug_temp >> dc;
                                                debug_temp &= 0x0001;
                                                if(dc  == 0){
                                                        cout << "Core [" << core_id << "] channel[" << channel
                                                                << "] " << " transmit data: \t\t";
                                                        cout << debug_temp;
                                                }
                                                else if(dc < FIFO_DEEP){
                                                        cout << debug_temp;
                                                }
                                        }
                                        cout << endl;
#endif
                                        EI_POWER;
                                        wmemory[data_address] = 0;
                                        f_ct[channel] = 0;
                                        if(channel == 0){
                                                write_state &= ~FIFO1;
                                        }
                                        else if(channel == 1){
                                                write_state &= ~FIFO2;
                                        }
                                        else if(channel == 2){
                                                write_state &= ~FIFO3;
                                        }
                                }
                        }
                }
                wait();
        }
}
 
void core :: receive_data()
{
 
        sc_uint<FIFO_DEEP>  rec_buff = 0;
        sc_uint<FIFO_DEEP>  f_ct[3];         //fifo deep counter.
        sc_uint<2>                      sel = 0;
        sc_uint<2>                      channel = 0;
        sc_uint<8>                              data_address = 0;
        bool temp = 0;
        bool ready = 0;
 
        f_ct[0] = f_ct[1] = f_ct[2] = 0;
 
        while(true){
                wait();
                if(!reset_n.read())
                {
                        f_ct[0] = f_ct[1] = f_ct[2] = 0;
                }
                else{
                        if(clk.read()){
                                read_n->write(true);
                                if(((empty->read()&0x01) != 0x01) && ((read_state & FIFO1) == FIFO1)){
                                        channel = 0;
                                        sel = 1;
                                        f_ct[channel]++;
                                        ready = 1;
                                        data_address = read_address[0];
                                }
                                else if(((empty->read()&0x02) != 0x02) && ((read_state & FIFO2) == FIFO2)){
                                        channel = 1;
                                        sel = 2;
                                        f_ct[channel]++;
                                        ready = 1;
                                        data_address = read_address[1];
                                }
                                else if(((empty->read()&0x04) != 0x04) && ((read_state & FIFO3) == FIFO3)){
                                        channel = 2;
                                        sel = 3;
                                        f_ct[channel]++;
                                        ready = 1;
                                        data_address = read_address[1];
                                }
                                else{
                                        ready = 0;
                                        sel = 0;
                                }
                                fifo_to_core_sel->write(sel);
                        }
                        else if(ready == 1){
                                if((f_ct[channel]-1) < FIFO_DEEP){
                                        read_n->write(false);
                                        wait(2,SC_NS);
                                        temp = data_in->read();
                                        rmemory[data_address] |= (temp << (f_ct[channel]-1));
                                        ready = 0;
                                        EI_POWER;
                                }
                                if((f_ct[channel]) == (FIFO_DEEP)){
                                        f_ct[channel] = 0;
                                        if(channel == 0)
                                                read_state &= ~FIFO1;
                                        else if(channel == 1)
                                                read_state &= ~FIFO2;
                                        else if(channel == 2)
                                                read_state &= ~FIFO3;
#ifdef CORE_RECEIVE_DEBUG
                                        short debug_temp = 0;
                                        for(int dc = 0; dc <= FIFO_DEEP; dc++){
                                                debug_temp = rmemory[data_address];
                                                debug_temp = debug_temp >> dc;
                                                debug_temp &= 0x0001;
                                                if(dc  == 0){
                                                        cout << "Core [" << core_id << "] channel[" << channel
                                                                << "] " << " receive data: \t\t";
                                                        cout << debug_temp;
                                                }
                                                else if(dc < FIFO_DEEP){
                                                        cout << debug_temp;
                                                }
                                        }
                                        rmemory[data_address] = 0;
                                        cout << endl;
#endif
                                }
                        }
                }
        }
}
 
char core :: write_data(sc_uint<3> sel, sc_uint<8> addr)
{
        sc_uint<3> fifo = 0;
 
        if(!(write_state & sel)){
                if(sel == FIFO1)
                        fifo = 0;
                else if(sel == FIFO2)
                        fifo = 1;
                else if(sel == FIFO3)
                        fifo = 2;
                else
                        cout << "error" << endl;
 
                write_address[fifo] = addr;
                write_state |= sel;
                return SUCCEED;
        }
        else
                return FAIL;
}
 
char core :: read_data(sc_uint<3> sel, sc_uint<8> addr)
{
        sc_uint<3> fifo = 0;
 
        if(!(read_state & sel)){
                if(sel == FIFO1)
                        fifo = 0;
                else if(sel == FIFO2)
                        fifo = 1;
                else if(sel == FIFO3)
                        fifo = 2;
                read_address[fifo] = addr;
                read_state |= sel;
                return SUCCEED;
        }
        else
                return FAIL;
}
 
void core :: core_handle()
{
        char state1 = FAIL, state2 = FAIL, state3 = FAIL, state4 = FAIL;
        char state5 = FAIL, state6 = FAIL;
        char rstate1 = 0, rstate2 = 0, rstate3 = 0;
        unsigned int delay = 0;
        HEAD_FLIT *head;
        BODY_FLIT *body;
 
        head = (HEAD_FLIT *)(wmemory+10); //0000 0010 1000 0000.
 
        head->type = 0;
        head->conn_type = 0;
        head->dst_addr = 4;
        head->pkt_size = 0;
 
        body = (BODY_FLIT *)(wmemory+11);//0100 1111 1111 0000
        body->type = 1;
        body->data = 0x0ff0;
 
 
        body = (BODY_FLIT *)(wmemory+12);//0100 1000 1000 0000
        body->type = 1;
        body->data = 0x0880;
 
        //Optical interconnects 
        head = (HEAD_FLIT *)(wmemory+13); //0010 0100 0000 0000
        head->type = 0;
        head->conn_type = 1;
        head->dst_addr = 15;
        head->pkt_size = 0;
 
        body = (BODY_FLIT *)(wmemory+14); //0100 0001 0001 0000
        body->type = 1;
        body->data = 0x0110;
 
        body = (BODY_FLIT *)(wmemory+15); //0100 1111 1111 1111
        body->type = 1;
        body->data = 0x0fff;
 
        while(true){
                if(!reset_n.read()){
 
                }
                else{
                        if(core_id == 0){
 
                                if(state1 == FAIL)
                                        state1 = write_data(FIFO1,10);
                                if(state2 == FAIL)
                                        state2 = write_data(FIFO1,11);
                                if(state3 == FAIL)
                                        state3 = write_data(FIFO1,12);
 
                                if(state4 == FAIL)
                                        state4 = write_data(FIFO2,13);
 
                                if(state4 == SUCCEED){
                                        if(delay > 200){
                                                if(state5 == FAIL)
                                                        state5 = write_data(FIFO2,14);
                                                if(state6 == FAIL){
                                                        state6 = write_data(FIFO2,15);
                                                        if(state6 == SUCCEED)
                                                                delay = 0;
                                                }
                                        }
                                        else{
                                                delay++;
                                        }
                                }
                        }
                        rstate1 = read_data(FIFO1,0);
                        rstate2 = read_data(FIFO2,1);
                        rstate3 = read_data(FIFO3,2);
                }
                wait();
        }
}

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[/] [noc/] [src/] [core.cc] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	imori	`#include <systemc>`
2			`#include <iostream>`
3			`#include "core.h"`
4			`#include "define.h"`
5
6			`using namespace std;`
7
8			`void core :: transfer_data()`
9			`{`
10			`sc_uint<FIFO_DEEP> buff;`
11			`sc_uint<FIFO_DEEP> f_ct[3];`
12			`sc_uint<3> channel = 0;`
13			`sc_uint<3> sel = 0;`
14			`sc_uint<8> data_address = 0;`
15			`bool stop_flag = 0;`
16			`bool temp = 0;`
17			`bool ready = 0;`
18
19			`while(true){`
20			`if(!reset_n.read()){`
21			`stop_flag = 0;`
22			`f_ct[0] = f_ct[1] = f_ct[2] = 0;`
23			`data_address = 0;`
24			`}`
25			`else{`
26			`if(clk.read()){`
27			`write_n->write(true);`
28			`if(((full->read()&0x01) != 0x01) && ((write_state & FIFO1) == FIFO1)){`
29			`sel = 1;`
30			`channel = 0;`
31			`stop_flag = 0;`
32			`f_ct[channel]++;`
33			`data_address = write_address[0];`
34			`}`
35			`else if(((full->read()&0x02) != 0x02)&&((write_state & FIFO2) == FIFO2)){`
36			`sel = 2;`
37			`channel = 1;`
38			`stop_flag = 0;`
39			`f_ct[channel]++;`
40			`data_address = write_address[1];`
41			`}`
42			`else if(((full->read()&0x04) != 0x04)&&((write_state & FIFO3) == FIFO3)){`
43			`sel = 3;`
44			`channel = 2;`
45			`stop_flag = 0;`
46			`f_ct[channel]++;`
47			`data_address = write_address[2];`
48			`}`
49			`else{`
50			`sel = 0;`
51			`stop_flag = 1;`
52			`}`
53			`core_to_fifo_sel->write(sel);`
54			`ready = 1;`
55			`}`
56			`else if((ready == 1) && (stop_flag == 0)){`
57			`if(((f_ct[channel] - 1) < FIFO_DEEP)){`
58			`buff = wmemory[data_address];`
59			`temp = (bool)((buff >> (f_ct[channel] - 1)) & 0x0001);`
60			`data_out->write(temp);`
61			`wait(1,SC_NS);`
62			`write_n->write(false);`
63			`ready = 0;`
64			`EI_POWER;`
65			`}`
66			`if((f_ct[channel]) == FIFO_DEEP){`
67			`#ifdef CORE_TRANSMIT_DEBUG`
68			`short debug_temp = 0;`
69			`for(int dc = 0; dc <= FIFO_DEEP; dc++){`
70			`debug_temp = wmemory[data_address];`
71			`debug_temp = debug_temp >> dc;`
72			`debug_temp &= 0x0001;`
73			`if(dc == 0){`
74			`cout << "Core [" << core_id << "] channel[" << channel`
75			`<< "] " << " transmit data: \t\t";`
76			`cout << debug_temp;`
77			`}`
78			`else if(dc < FIFO_DEEP){`
79			`cout << debug_temp;`
80			`}`
81			`}`
82			`cout << endl;`
83			`#endif`
84			`EI_POWER;`
85			`wmemory[data_address] = 0;`
86			`f_ct[channel] = 0;`
87			`if(channel == 0){`
88			`write_state &= ~FIFO1;`
89			`}`
90			`else if(channel == 1){`
91			`write_state &= ~FIFO2;`
92			`}`
93			`else if(channel == 2){`
94			`write_state &= ~FIFO3;`
95			`}`
96			`}`
97			`}`
98			`}`
99			`wait();`
100			`}`
101			`}`
102
103			`void core :: receive_data()`
104			`{`
105
106			`sc_uint<FIFO_DEEP> rec_buff = 0;`
107			`sc_uint<FIFO_DEEP> f_ct[3]; //fifo deep counter.`
108			`sc_uint<2> sel = 0;`
109			`sc_uint<2> channel = 0;`
110			`sc_uint<8> data_address = 0;`
111			`bool temp = 0;`
112			`bool ready = 0;`
113
114			`f_ct[0] = f_ct[1] = f_ct[2] = 0;`
115
116			`while(true){`
117			`wait();`
118			`if(!reset_n.read())`
119			`{`
120			`f_ct[0] = f_ct[1] = f_ct[2] = 0;`
121			`}`
122			`else{`
123			`if(clk.read()){`
124			`read_n->write(true);`
125			`if(((empty->read()&0x01) != 0x01) && ((read_state & FIFO1) == FIFO1)){`
126			`channel = 0;`
127			`sel = 1;`
128			`f_ct[channel]++;`
129			`ready = 1;`
130			`data_address = read_address[0];`
131			`}`
132			`else if(((empty->read()&0x02) != 0x02) && ((read_state & FIFO2) == FIFO2)){`
133			`channel = 1;`
134			`sel = 2;`
135			`f_ct[channel]++;`
136			`ready = 1;`
137			`data_address = read_address[1];`
138			`}`
139			`else if(((empty->read()&0x04) != 0x04) && ((read_state & FIFO3) == FIFO3)){`
140			`channel = 2;`
141			`sel = 3;`
142			`f_ct[channel]++;`
143			`ready = 1;`
144			`data_address = read_address[1];`
145			`}`
146			`else{`
147			`ready = 0;`
148			`sel = 0;`
149			`}`
150			`fifo_to_core_sel->write(sel);`
151			`}`
152			`else if(ready == 1){`
153			`if((f_ct[channel]-1) < FIFO_DEEP){`
154			`read_n->write(false);`
155			`wait(2,SC_NS);`
156			`temp = data_in->read();`
157			`rmemory[data_address] \|= (temp << (f_ct[channel]-1));`
158			`ready = 0;`
159			`EI_POWER;`
160			`}`
161			`if((f_ct[channel]) == (FIFO_DEEP)){`
162			`f_ct[channel] = 0;`
163			`if(channel == 0)`
164			`read_state &= ~FIFO1;`
165			`else if(channel == 1)`
166			`read_state &= ~FIFO2;`
167			`else if(channel == 2)`
168			`read_state &= ~FIFO3;`
169			`#ifdef CORE_RECEIVE_DEBUG`
170			`short debug_temp = 0;`
171			`for(int dc = 0; dc <= FIFO_DEEP; dc++){`
172			`debug_temp = rmemory[data_address];`
173			`debug_temp = debug_temp >> dc;`
174			`debug_temp &= 0x0001;`
175			`if(dc == 0){`
176			`cout << "Core [" << core_id << "] channel[" << channel`
177			`<< "] " << " receive data: \t\t";`
178			`cout << debug_temp;`
179			`}`
180			`else if(dc < FIFO_DEEP){`
181			`cout << debug_temp;`
182			`}`
183			`}`
184			`rmemory[data_address] = 0;`
185			`cout << endl;`
186			`#endif`
187			`}`
188			`}`
189			`}`
190			`}`
191			`}`
192
193			`char core :: write_data(sc_uint<3> sel, sc_uint<8> addr)`
194			`{`
195			`sc_uint<3> fifo = 0;`
196
197			`if(!(write_state & sel)){`
198			`if(sel == FIFO1)`
199			`fifo = 0;`
200			`else if(sel == FIFO2)`
201			`fifo = 1;`
202			`else if(sel == FIFO3)`
203			`fifo = 2;`
204			`else`
205			`cout << "error" << endl;`
206
207			`write_address[fifo] = addr;`
208			`write_state \|= sel;`
209			`return SUCCEED;`
210			`}`
211			`else`
212			`return FAIL;`
213			`}`
214
215			`char core :: read_data(sc_uint<3> sel, sc_uint<8> addr)`
216			`{`
217			`sc_uint<3> fifo = 0;`
218
219			`if(!(read_state & sel)){`
220			`if(sel == FIFO1)`
221			`fifo = 0;`
222			`else if(sel == FIFO2)`
223			`fifo = 1;`
224			`else if(sel == FIFO3)`
225			`fifo = 2;`
226			`read_address[fifo] = addr;`
227			`read_state \|= sel;`
228			`return SUCCEED;`
229			`}`
230			`else`
231			`return FAIL;`
232			`}`
233
234			`void core :: core_handle()`
235			`{`
236			`char state1 = FAIL, state2 = FAIL, state3 = FAIL, state4 = FAIL;`
237			`char state5 = FAIL, state6 = FAIL;`
238			`char rstate1 = 0, rstate2 = 0, rstate3 = 0;`
239			`unsigned int delay = 0;`
240			`HEAD_FLIT *head;`
241			`BODY_FLIT *body;`
242
243			`head = (HEAD_FLIT *)(wmemory+10); //0000 0010 1000 0000.`
244
245			`head->type = 0;`
246			`head->conn_type = 0;`
247			`head->dst_addr = 4;`
248			`head->pkt_size = 0;`
249
250			`body = (BODY_FLIT *)(wmemory+11);//0100 1111 1111 0000`
251			`body->type = 1;`
252			`body->data = 0x0ff0;`
253
254
255			`body = (BODY_FLIT *)(wmemory+12);//0100 1000 1000 0000`
256			`body->type = 1;`
257			`body->data = 0x0880;`
258
259			`//Optical interconnects`
260			`head = (HEAD_FLIT *)(wmemory+13); //0010 0100 0000 0000`
261			`head->type = 0;`
262			`head->conn_type = 1;`
263			`head->dst_addr = 15;`
264			`head->pkt_size = 0;`
265
266			`body = (BODY_FLIT *)(wmemory+14); //0100 0001 0001 0000`
267			`body->type = 1;`
268			`body->data = 0x0110;`
269
270			`body = (BODY_FLIT *)(wmemory+15); //0100 1111 1111 1111`
271			`body->type = 1;`
272			`body->data = 0x0fff;`
273
274			`while(true){`
275			`if(!reset_n.read()){`
276
277			`}`
278			`else{`
279			`if(core_id == 0){`
280
281			`if(state1 == FAIL)`
282			`state1 = write_data(FIFO1,10);`
283			`if(state2 == FAIL)`
284			`state2 = write_data(FIFO1,11);`
285			`if(state3 == FAIL)`
286			`state3 = write_data(FIFO1,12);`
287
288			`if(state4 == FAIL)`
289			`state4 = write_data(FIFO2,13);`
290
291			`if(state4 == SUCCEED){`
292			`if(delay > 200){`
293			`if(state5 == FAIL)`
294			`state5 = write_data(FIFO2,14);`
295			`if(state6 == FAIL){`
296			`state6 = write_data(FIFO2,15);`
297			`if(state6 == SUCCEED)`
298			`delay = 0;`
299			`}`
300			`}`
301			`else{`
302			`delay++;`
303			`}`
304			`}`
305			`}`
306			`rstate1 = read_data(FIFO1,0);`
307			`rstate2 = read_data(FIFO2,1);`
308			`rstate3 = read_data(FIFO3,2);`
309			`}`
310			`wait();`
311			`}`
312			`}`