| 1 |
4 |
imori |
/*
|
| 2 |
|
|
* =====================================================================================
|
| 3 |
|
|
*
|
| 4 |
|
|
* Filename: router.cc
|
| 5 |
|
|
*
|
| 6 |
|
|
* Description: router
|
| 7 |
|
|
*
|
| 8 |
|
|
* Version: 1.0
|
| 9 |
|
|
* Created: 03/25/2009 12:42:15 PM
|
| 10 |
|
|
* Revision: none
|
| 11 |
|
|
* Compiler: gcc
|
| 12 |
|
|
*
|
| 13 |
|
|
* Author: Soontea Kwon (), Kwonst@skku.edu
|
| 14 |
|
|
* Company: Mobile Electronics Lab
|
| 15 |
|
|
*
|
| 16 |
|
|
* =====================================================================================
|
| 17 |
|
|
*/
|
| 18 |
|
|
#include "router.h"
|
| 19 |
|
|
|
| 20 |
|
|
char router :: direction_decision(char dst_x, char dst_y, char router_x, char router_y)
|
| 21 |
|
|
{
|
| 22 |
|
|
if(dst_x < router_x){ //outgoing west.
|
| 23 |
|
|
return WEST_ADDRESS;
|
| 24 |
|
|
}
|
| 25 |
|
|
else if(dst_x > router_x){ //outgoing east.
|
| 26 |
|
|
return EAST_ADDRESS;
|
| 27 |
|
|
}
|
| 28 |
|
|
else{
|
| 29 |
|
|
if(dst_y > router_y){ //outgoing north.
|
| 30 |
|
|
return SOUTH_ADDRESS;
|
| 31 |
|
|
}
|
| 32 |
|
|
else if(dst_y < router_y){ //outgoing sourth.
|
| 33 |
|
|
return NORTH_ADDRESS;
|
| 34 |
|
|
}
|
| 35 |
|
|
else{ //outgoing core.
|
| 36 |
|
|
return CORE_ADDRESS;
|
| 37 |
|
|
}
|
| 38 |
|
|
}
|
| 39 |
|
|
}
|
| 40 |
|
|
|
| 41 |
|
|
char router :: header_decoder(sc_uint<8> addr){
|
| 42 |
|
|
|
| 43 |
|
|
HEAD_FLIT *head_flit;
|
| 44 |
|
|
sc_uint<6> dst_x, dst_y, router_x, router_y;
|
| 45 |
|
|
sc_uint<16> temp;
|
| 46 |
|
|
sc_uint<2> ch_temp = 0;
|
| 47 |
|
|
unsigned short temp_s;
|
| 48 |
|
|
|
| 49 |
|
|
temp = rbuffer[addr].range(15,0);
|
| 50 |
|
|
temp_s = temp;
|
| 51 |
|
|
head_flit = (HEAD_FLIT *)&temp_s;
|
| 52 |
|
|
|
| 53 |
|
|
if(head_flit->type == _HEAD_FLIT){
|
| 54 |
|
|
//Header flit.
|
| 55 |
|
|
dst_x = head_flit->dst_addr % x_num;
|
| 56 |
|
|
dst_y = head_flit->dst_addr / y_num;
|
| 57 |
|
|
router_x = router_id % x_num;
|
| 58 |
|
|
router_y = router_id / y_num;
|
| 59 |
|
|
port[addr].outport = direction_decision(dst_x, dst_y, router_x, router_y);
|
| 60 |
|
|
#ifdef ROUTER_DEC_DEBUG
|
| 61 |
|
|
cout << "Head flit" << endl;
|
| 62 |
|
|
cout << "packet dst_y: " << dst_y << ", dst_x: " << dst_x << endl;
|
| 63 |
|
|
cout << "router x: " << router_x << ", y: " << router_y << endl;
|
| 64 |
|
|
|
| 65 |
|
|
switch(port[addr].outport){
|
| 66 |
|
|
case WEST_ADDRESS : cout << "WEST" << endl;
|
| 67 |
|
|
break;
|
| 68 |
|
|
case EAST_ADDRESS : cout << "EAST" << endl;
|
| 69 |
|
|
break;
|
| 70 |
|
|
case SOUTH_ADDRESS : cout << "SOUTH" << endl;
|
| 71 |
|
|
break;
|
| 72 |
|
|
case NORTH_ADDRESS : cout << "NORTH" << endl;
|
| 73 |
|
|
break;
|
| 74 |
|
|
case CORE_ADDRESS : cout << "CORE" << endl;
|
| 75 |
|
|
break;
|
| 76 |
|
|
}
|
| 77 |
|
|
#endif
|
| 78 |
|
|
|
| 79 |
|
|
for(int i = 0; i < 3; i++){
|
| 80 |
|
|
if(!(tbuffer_state & (1 << (port[addr].outport + i)))){
|
| 81 |
|
|
port[addr].out_ch = i;
|
| 82 |
|
|
port[addr].set = 1;
|
| 83 |
|
|
tbuffer_state |= (1 << (port[addr].outport + i));
|
| 84 |
|
|
|
| 85 |
|
|
if(head_flit->conn_type == EIs){
|
| 86 |
|
|
return EIs;
|
| 87 |
|
|
}
|
| 88 |
|
|
else if(head_flit->conn_type == OIs){
|
| 89 |
|
|
return OIs;
|
| 90 |
|
|
}
|
| 91 |
|
|
}
|
| 92 |
|
|
}
|
| 93 |
|
|
}
|
| 94 |
|
|
return FAIL;
|
| 95 |
|
|
}
|
| 96 |
|
|
|
| 97 |
|
|
#ifdef ROUTER_DEBUG
|
| 98 |
|
|
void router :: transfer_data(sc_out<bool> *data_out, sc_out<sc_uint<2> > *router_to_fifo_sel,
|
| 99 |
|
|
sc_out<bool> *write_n, sc_in<sc_uint<3> > *full, sc_uint<8> address,
|
| 100 |
|
|
char *debug_string, unsigned char debug_en)
|
| 101 |
|
|
#else
|
| 102 |
|
|
|
| 103 |
|
|
void router :: transfer_data(sc_out<bool> *data_out, sc_out<sc_uint<2> > *router_to_fifo_sel,
|
| 104 |
|
|
sc_out<bool> *write_n, sc_in<sc_uint<3> > *full, sc_uint<8> address)
|
| 105 |
|
|
#endif
|
| 106 |
|
|
{
|
| 107 |
|
|
sc_uint<FIFO_DEEP> tr_fc; //fifo deep counter.
|
| 108 |
|
|
sc_uint<FIFO_DEEP> buff;
|
| 109 |
|
|
sc_uint<FIFO_DEEP> f_ct[3];
|
| 110 |
|
|
sc_uint<3> channel = 0;
|
| 111 |
|
|
sc_uint<3> sel = 0;
|
| 112 |
|
|
bool stop_flag = 0;
|
| 113 |
|
|
bool temp = 0;
|
| 114 |
|
|
bool ready = 0;
|
| 115 |
|
|
|
| 116 |
|
|
while(true){
|
| 117 |
|
|
if(!reset_n.read()){
|
| 118 |
|
|
stop_flag = 0;
|
| 119 |
|
|
f_ct[0] = f_ct[1] = f_ct[2] = 0;
|
| 120 |
|
|
}
|
| 121 |
|
|
else{
|
| 122 |
|
|
if(clk.read()){
|
| 123 |
|
|
write_n->write(true);
|
| 124 |
|
|
if(((full->read()&0x01) != 0x01) && ((tbuffer[address+0] & WEN) == WEN)){
|
| 125 |
|
|
sel = 1;
|
| 126 |
|
|
channel = 0;
|
| 127 |
|
|
stop_flag = 0;
|
| 128 |
|
|
f_ct[channel]++;
|
| 129 |
|
|
}
|
| 130 |
|
|
else if(((full->read()&0x02) != 0x02)&&((tbuffer[address+1] & WEN) == WEN)){
|
| 131 |
|
|
sel = 2;
|
| 132 |
|
|
channel = 1;
|
| 133 |
|
|
stop_flag = 0;
|
| 134 |
|
|
f_ct[channel]++;
|
| 135 |
|
|
}
|
| 136 |
|
|
else if(((full->read()&0x04) != 0x04)&&((tbuffer[address+2] & WEN) == WEN)){
|
| 137 |
|
|
sel = 3;
|
| 138 |
|
|
channel = 2;
|
| 139 |
|
|
stop_flag = 0;
|
| 140 |
|
|
f_ct[channel]++;
|
| 141 |
|
|
}
|
| 142 |
|
|
else{
|
| 143 |
|
|
sel = 0x00;
|
| 144 |
|
|
stop_flag = 1;
|
| 145 |
|
|
}
|
| 146 |
|
|
router_to_fifo_sel->write(sel);
|
| 147 |
|
|
ready = 1;
|
| 148 |
|
|
}
|
| 149 |
|
|
else if((ready == 1) && (stop_flag == 0)){
|
| 150 |
|
|
if(((f_ct[channel] - 1) < FIFO_DEEP)){
|
| 151 |
|
|
buff = tbuffer[address+channel].range(15,0);
|
| 152 |
|
|
temp =(bool)((buff >> (f_ct[channel] - 1)) & 0x0001);
|
| 153 |
|
|
data_out->write(temp);
|
| 154 |
|
|
write_n->write(false);
|
| 155 |
|
|
ready = 0;
|
| 156 |
|
|
EI_POWER;
|
| 157 |
|
|
}
|
| 158 |
|
|
if((f_ct[channel]) >= (FIFO_DEEP)){
|
| 159 |
|
|
f_ct[channel] = 0;
|
| 160 |
|
|
tbuffer[address+channel] &= ~WEN;
|
| 161 |
|
|
tbuffer[address+channel] = 0;
|
| 162 |
|
|
if(tbuffer[address+channel].range(15,14) & _TAIL_FLIT){
|
| 163 |
|
|
#ifdef ROUTER_DEBUG
|
| 164 |
|
|
cout << "Tail flit" << endl;
|
| 165 |
|
|
#endif
|
| 166 |
|
|
port[address+channel].set = 0;
|
| 167 |
|
|
port[address+channel].inport = 0;
|
| 168 |
|
|
port[address+channel].outport = 0;
|
| 169 |
|
|
port[address+channel].in_ch = 0;
|
| 170 |
|
|
port[address+channel].out_ch = 0;
|
| 171 |
|
|
tbuffer_state &= ~(1 << address + channel);
|
| 172 |
|
|
}
|
| 173 |
|
|
EI_POWER;
|
| 174 |
|
|
#ifdef ROUTER_DEBUG
|
| 175 |
|
|
// cout << "Router [" << router_id << "] " << debug_string << " output channel: " << channel << endl;
|
| 176 |
|
|
#endif
|
| 177 |
|
|
}
|
| 178 |
|
|
}
|
| 179 |
|
|
}
|
| 180 |
|
|
wait();
|
| 181 |
|
|
}
|
| 182 |
|
|
}
|
| 183 |
|
|
#ifdef ROUTER_DEBUG
|
| 184 |
|
|
void router :: receive_data(sc_in<bool> *data_in, sc_out<sc_uint<2> > *fifo_to_router_sel,
|
| 185 |
|
|
sc_out<bool> *read_n, sc_in<sc_uint<3> > *empty, sc_uint<8> address,
|
| 186 |
|
|
char *debug_string, unsigned char debug_en)
|
| 187 |
|
|
#else
|
| 188 |
|
|
void router :: receive_data(sc_in<bool> *data_in, sc_out<sc_uint<2> > *fifo_to_router_sel,
|
| 189 |
|
|
sc_out<bool> *read_n, sc_in<sc_uint<3> > *empty, sc_uint<8> address)
|
| 190 |
|
|
#endif
|
| 191 |
|
|
{
|
| 192 |
|
|
sc_uint<FIFO_DEEP> rec_buff = 0;
|
| 193 |
|
|
sc_uint<FIFO_DEEP> rec_fc = 0; //fifo deep counter.
|
| 194 |
|
|
sc_uint<FIFO_DEEP> f_ct[3]; //fifo deep counter.
|
| 195 |
|
|
sc_uint<2> sel = 0;
|
| 196 |
|
|
sc_uint<2> channel = 0;
|
| 197 |
|
|
bool temp = 0;
|
| 198 |
|
|
bool ready = 0;
|
| 199 |
|
|
|
| 200 |
|
|
f_ct[0] = f_ct[1] = f_ct[2] = 0;
|
| 201 |
|
|
rbuffer[0] = rbuffer[1] = rbuffer[2] = 0;
|
| 202 |
|
|
|
| 203 |
|
|
read_n->write(true);
|
| 204 |
|
|
|
| 205 |
|
|
while(true){
|
| 206 |
|
|
wait();
|
| 207 |
|
|
if(!reset_n.read())
|
| 208 |
|
|
{
|
| 209 |
|
|
rbuffer[0] = rbuffer[1] = rbuffer[2] = 0;
|
| 210 |
|
|
f_ct[0] = f_ct[1] = f_ct[2] = 0;
|
| 211 |
|
|
read_n->write(true);
|
| 212 |
|
|
}
|
| 213 |
|
|
else{
|
| 214 |
|
|
if(clk.read()){
|
| 215 |
|
|
read_n->write(true);
|
| 216 |
|
|
if(((empty->read()&0x01) != 0x01) && (rbuffer[address+0]&REN) != REN){
|
| 217 |
|
|
channel = 0;
|
| 218 |
|
|
sel = 1;
|
| 219 |
|
|
f_ct[channel]++;
|
| 220 |
|
|
ready = 1;
|
| 221 |
|
|
}
|
| 222 |
|
|
else if(((empty->read()&0x02) != 0x02) && ((rbuffer[address+1]&REN) != REN)){
|
| 223 |
|
|
channel = 1;
|
| 224 |
|
|
sel = 2;
|
| 225 |
|
|
f_ct[channel]++;
|
| 226 |
|
|
ready = 1;
|
| 227 |
|
|
}
|
| 228 |
|
|
else if(((empty->read()&0x04) != 0x04) && ((rbuffer[address+2]&REN) != REN)){
|
| 229 |
|
|
channel = 2;
|
| 230 |
|
|
sel = 3;
|
| 231 |
|
|
f_ct[channel]++;
|
| 232 |
|
|
ready = 1;
|
| 233 |
|
|
}
|
| 234 |
|
|
else{
|
| 235 |
|
|
ready = 0;
|
| 236 |
|
|
sel = 0;
|
| 237 |
|
|
}
|
| 238 |
|
|
fifo_to_router_sel->write(sel);
|
| 239 |
|
|
}
|
| 240 |
|
|
else if(ready == 1){
|
| 241 |
|
|
if((f_ct[channel]) < FIFO_DEEP+1){
|
| 242 |
|
|
read_n->write(false);
|
| 243 |
|
|
wait(2,SC_NS);
|
| 244 |
|
|
temp = data_in->read();
|
| 245 |
|
|
rbuffer[address+channel] |= (temp << (f_ct[channel]-1));
|
| 246 |
|
|
ready = 0;
|
| 247 |
|
|
EI_POWER;
|
| 248 |
|
|
}
|
| 249 |
|
|
if((f_ct[channel]) == (FIFO_DEEP)){
|
| 250 |
|
|
f_ct[channel] = 0;
|
| 251 |
|
|
rbuffer[address+channel] |= REN;
|
| 252 |
|
|
EI_POWER;
|
| 253 |
|
|
EI_DELAY;
|
| 254 |
|
|
#ifdef ROUTER_DEBUG
|
| 255 |
|
|
if(debug_en == 1){
|
| 256 |
|
|
unsigned short debug_temp = 0;
|
| 257 |
|
|
for(int dc = 0; dc <= FIFO_DEEP; dc++){
|
| 258 |
|
|
debug_temp = rbuffer[address+channel];
|
| 259 |
|
|
debug_temp = debug_temp >> dc;
|
| 260 |
|
|
debug_temp &= 0x0001;
|
| 261 |
|
|
if(dc == 0){
|
| 262 |
|
|
cout << "router [" << router_id << "] channel["
|
| 263 |
|
|
<< channel << "] " << debug_string << " receive data: \t";
|
| 264 |
|
|
cout << debug_temp;
|
| 265 |
|
|
}
|
| 266 |
|
|
else if(dc < FIFO_DEEP){
|
| 267 |
|
|
cout << debug_temp;
|
| 268 |
|
|
}
|
| 269 |
|
|
}
|
| 270 |
|
|
cout << endl;
|
| 271 |
|
|
}
|
| 272 |
|
|
#endif
|
| 273 |
|
|
}
|
| 274 |
|
|
}
|
| 275 |
|
|
}
|
| 276 |
|
|
}
|
| 277 |
|
|
}
|
| 278 |
|
|
|
| 279 |
|
|
//CORE
|
| 280 |
|
|
void router :: core_receive_data(){
|
| 281 |
|
|
#ifdef ROUTER_DEBUG
|
| 282 |
|
|
receive_data(&c_data_in, &c_fifo_to_router_sel, &c_read_n, &c_empty, CORE_ADDRESS,
|
| 283 |
|
|
"core",1);
|
| 284 |
|
|
#else
|
| 285 |
|
|
receive_data(&c_data_in, &c_fifo_to_router_sel, &c_read_n, &c_empty, CORE_ADDRESS);
|
| 286 |
|
|
#endif
|
| 287 |
|
|
}
|
| 288 |
|
|
void router :: core_transfer_data(){
|
| 289 |
|
|
#ifdef ROUTER_DEBUG
|
| 290 |
|
|
transfer_data(&c_data_out, &c_router_to_fifo_sel, &c_write_n, &c_full, CORE_ADDRESS,
|
| 291 |
|
|
"core" , 1);
|
| 292 |
|
|
#else
|
| 293 |
|
|
transfer_data(&c_data_out, &c_router_to_fifo_sel, &c_write_n, &c_full, CORE_ADDRESS);
|
| 294 |
|
|
#endif
|
| 295 |
|
|
}
|
| 296 |
|
|
|
| 297 |
|
|
//WEST
|
| 298 |
|
|
void router :: west_receive_data(){
|
| 299 |
|
|
#ifdef ROUTER_DEBUG
|
| 300 |
|
|
receive_data(&w_data_in, &w_fifo_to_router_sel, &w_read_n, &w_empty, WEST_ADDRESS,
|
| 301 |
|
|
"west", 0);
|
| 302 |
|
|
#else
|
| 303 |
|
|
receive_data(&w_data_in, &w_fifo_to_router_sel, &w_read_n, &w_empty, WEST_ADDRESS);
|
| 304 |
|
|
#endif
|
| 305 |
|
|
|
| 306 |
|
|
}
|
| 307 |
|
|
void router :: west_transfer_data(){
|
| 308 |
|
|
#ifdef ROUTER_DEBUG
|
| 309 |
|
|
transfer_data(&w_data_out, &w_router_to_fifo_sel, &w_write_n, &w_full, WEST_ADDRESS,
|
| 310 |
|
|
"west" , 0);
|
| 311 |
|
|
#else
|
| 312 |
|
|
transfer_data(&w_data_out, &w_router_to_fifo_sel, &w_write_n, &w_full, WEST_ADDRESS);
|
| 313 |
|
|
#endif
|
| 314 |
|
|
}
|
| 315 |
|
|
|
| 316 |
|
|
//EAST
|
| 317 |
|
|
void router :: east_receive_data(){
|
| 318 |
|
|
#ifdef ROUTER_DEBUG
|
| 319 |
|
|
receive_data(&e_data_in, &e_fifo_to_router_sel, &e_read_n, &e_empty, EAST_ADDRESS,
|
| 320 |
|
|
"east", 0);
|
| 321 |
|
|
#else
|
| 322 |
|
|
receive_data(&e_data_in, &e_fifo_to_router_sel, &e_read_n, &e_empty, EAST_ADDRESS);
|
| 323 |
|
|
#endif
|
| 324 |
|
|
}
|
| 325 |
|
|
|
| 326 |
|
|
void router :: east_transfer_data(){
|
| 327 |
|
|
#ifdef ROUTER_DEBUG
|
| 328 |
|
|
transfer_data(&e_data_out, &e_router_to_fifo_sel, &e_write_n, &e_full, EAST_ADDRESS,
|
| 329 |
|
|
"east", 0);
|
| 330 |
|
|
#else
|
| 331 |
|
|
transfer_data(&e_data_out, &e_router_to_fifo_sel, &e_write_n, &e_full, EAST_ADDRESS);
|
| 332 |
|
|
#endif
|
| 333 |
|
|
}
|
| 334 |
|
|
|
| 335 |
|
|
//NORTH
|
| 336 |
|
|
void router :: north_receive_data(){
|
| 337 |
|
|
#ifdef ROUTER_DEBUG
|
| 338 |
|
|
receive_data(&n_data_in, &n_fifo_to_router_sel, &n_read_n, &n_empty, NORTH_ADDRESS,
|
| 339 |
|
|
"north", 0);
|
| 340 |
|
|
#else
|
| 341 |
|
|
receive_data(&n_data_in, &n_fifo_to_router_sel, &n_read_n, &n_empty, NORTH_ADDRESS);
|
| 342 |
|
|
#endif
|
| 343 |
|
|
}
|
| 344 |
|
|
|
| 345 |
|
|
void router :: north_transfer_data(){
|
| 346 |
|
|
#ifdef ROUTER_DEBUG
|
| 347 |
|
|
transfer_data(&n_data_out, &n_router_to_fifo_sel, &n_write_n, &n_full, NORTH_ADDRESS,
|
| 348 |
|
|
"north", 0);
|
| 349 |
|
|
#else
|
| 350 |
|
|
transfer_data(&n_data_out, &n_router_to_fifo_sel, &n_write_n, &n_full, NORTH_ADDRESS);
|
| 351 |
|
|
#endif
|
| 352 |
|
|
}
|
| 353 |
|
|
|
| 354 |
|
|
//SOUTH
|
| 355 |
|
|
void router :: south_receive_data(){
|
| 356 |
|
|
#ifdef ROUTER_DEBUG
|
| 357 |
|
|
receive_data(&s_data_in, &s_fifo_to_router_sel, &s_read_n, &s_empty, SOUTH_ADDRESS,
|
| 358 |
|
|
"south", 0);
|
| 359 |
|
|
#else
|
| 360 |
|
|
receive_data(&s_data_in, &s_fifo_to_router_sel, &s_read_n, &s_empty, SOUTH_ADDRESS);
|
| 361 |
|
|
#endif
|
| 362 |
|
|
}
|
| 363 |
|
|
|
| 364 |
|
|
void router :: south_transfer_data(){
|
| 365 |
|
|
#ifdef ROUTER_DEBUG
|
| 366 |
|
|
transfer_data(&s_data_out, &s_router_to_fifo_sel, &s_write_n, &s_full, SOUTH_ADDRESS,
|
| 367 |
|
|
"south", 0);
|
| 368 |
|
|
#else
|
| 369 |
|
|
transfer_data(&s_data_out, &s_router_to_fifo_sel, &s_write_n, &s_full, SOUTH_ADDRESS);
|
| 370 |
|
|
#endif
|
| 371 |
|
|
}
|
| 372 |
|
|
|
| 373 |
|
|
void router :: oi_transfer_data()
|
| 374 |
|
|
{
|
| 375 |
|
|
sc_uint<OI_FLIT_SIZE> temp = 0;
|
| 376 |
|
|
sc_uint<OI_FLIT_SIZE> tc_count = 0;
|
| 377 |
|
|
bool tr_bit_temp;
|
| 378 |
|
|
sc_logic rc_temp = SC_LOGIC_Z;
|
| 379 |
|
|
|
| 380 |
|
|
while(true){
|
| 381 |
|
|
if(!reset_n.read()){
|
| 382 |
|
|
c_oi_out.write(SC_LOGIC_Z);
|
| 383 |
|
|
tc_count = 0;
|
| 384 |
|
|
}
|
| 385 |
|
|
else{
|
| 386 |
|
|
if((tbuffer[OI_ADDRESS] & WEN) == WEN){
|
| 387 |
|
|
temp = tbuffer[OI_ADDRESS].range(15,0);
|
| 388 |
|
|
tr_bit_temp = ((temp >> tc_count) & 0x0001);
|
| 389 |
|
|
if(tr_bit_temp == 1){
|
| 390 |
|
|
c_oi_out.write(SC_LOGIC_1);
|
| 391 |
|
|
tc_count++;
|
| 392 |
|
|
TRANSMITTER_OI_POWER;
|
| 393 |
|
|
}
|
| 394 |
|
|
else if(tr_bit_temp == 0){
|
| 395 |
|
|
c_oi_out.write(SC_LOGIC_0);
|
| 396 |
|
|
tc_count++;
|
| 397 |
|
|
TRANSMITTER_OI_POWER;
|
| 398 |
|
|
}
|
| 399 |
|
|
else{
|
| 400 |
|
|
c_oi_out.write(SC_LOGIC_Z);
|
| 401 |
|
|
}
|
| 402 |
|
|
if(tc_count == OI_FLIT_SIZE + 1){
|
| 403 |
|
|
c_oi_out.write(SC_LOGIC_Z);
|
| 404 |
|
|
#ifdef ROUTER_DEBUG
|
| 405 |
|
|
short debug_temp = 0;
|
| 406 |
|
|
for(int dc = 0; dc <= FIFO_DEEP; dc++){
|
| 407 |
|
|
debug_temp = tbuffer[OI_ADDRESS].range(15,0);
|
| 408 |
|
|
debug_temp = debug_temp >> dc;
|
| 409 |
|
|
debug_temp &= 0x0001;
|
| 410 |
|
|
if(dc == 0){
|
| 411 |
|
|
cout << "router [" << router_id << "] OI transfer data: \t";
|
| 412 |
|
|
cout << debug_temp;
|
| 413 |
|
|
}
|
| 414 |
|
|
else if(dc < FIFO_DEEP){
|
| 415 |
|
|
cout << debug_temp;
|
| 416 |
|
|
}
|
| 417 |
|
|
}
|
| 418 |
|
|
cout << endl;
|
| 419 |
|
|
#endif
|
| 420 |
|
|
if(tbuffer[OI_ADDRESS].range(15,14) & _TAIL_FLIT){
|
| 421 |
|
|
#ifdef ROUTER_DEBUG
|
| 422 |
|
|
cout << "OI TR : Tail flit" << endl;
|
| 423 |
|
|
#endif
|
| 424 |
|
|
port[OI_ADDRESS].set = 0;
|
| 425 |
|
|
port[OI_ADDRESS].inport = 0;
|
| 426 |
|
|
port[OI_ADDRESS].outport = 0;
|
| 427 |
|
|
port[OI_ADDRESS].in_ch = 0;
|
| 428 |
|
|
port[OI_ADDRESS].out_ch = 0;
|
| 429 |
|
|
tbuffer_state &= ~(1 << OI_ADDRESS);
|
| 430 |
|
|
}
|
| 431 |
|
|
TRANSMITTER_OI_DELAY;
|
| 432 |
|
|
tc_count = 0;
|
| 433 |
|
|
tbuffer[OI_ADDRESS] = 0;
|
| 434 |
|
|
}
|
| 435 |
|
|
}
|
| 436 |
|
|
}
|
| 437 |
|
|
wait();
|
| 438 |
|
|
}
|
| 439 |
|
|
}
|
| 440 |
|
|
|
| 441 |
|
|
void router :: oi_receive_data()
|
| 442 |
|
|
{
|
| 443 |
|
|
sc_uint<OI_FLIT_SIZE> temp = 0;
|
| 444 |
|
|
sc_uint<OI_FLIT_SIZE> oi_count = 0;
|
| 445 |
|
|
sc_logic rc_temp = SC_LOGIC_Z;
|
| 446 |
|
|
|
| 447 |
|
|
while(true){
|
| 448 |
|
|
if(!reset_n.read()){
|
| 449 |
|
|
oi_count = 0;
|
| 450 |
|
|
rc_temp = SC_LOGIC_Z;
|
| 451 |
|
|
temp = 0;
|
| 452 |
|
|
}
|
| 453 |
|
|
else{
|
| 454 |
|
|
if((rbuffer[OI_ADDRESS] & REN) != REN){
|
| 455 |
|
|
rc_temp = c_oi_in.read();
|
| 456 |
|
|
if((rc_temp != SC_LOGIC_Z) && (rc_temp != SC_LOGIC_X)){
|
| 457 |
|
|
if(rc_temp == SC_LOGIC_0){
|
| 458 |
|
|
oi_count++;
|
| 459 |
|
|
RECEIVER_OI_ENERGY;
|
| 460 |
|
|
}
|
| 461 |
|
|
else if(rc_temp == SC_LOGIC_1){
|
| 462 |
|
|
temp |= (1 << oi_count);
|
| 463 |
|
|
oi_count++;
|
| 464 |
|
|
RECEIVER_OI_ENERGY;
|
| 465 |
|
|
}
|
| 466 |
|
|
if(oi_count == OI_FLIT_SIZE){
|
| 467 |
|
|
rbuffer[OI_ADDRESS] = temp;
|
| 468 |
|
|
rbuffer[OI_ADDRESS] |= REN;
|
| 469 |
|
|
RECEIVER_OI_DELAY;
|
| 470 |
|
|
oi_count = 0;
|
| 471 |
|
|
temp = 0;
|
| 472 |
|
|
#ifdef ROUTER_DEBUG
|
| 473 |
|
|
short debug_temp = 0;
|
| 474 |
|
|
for(int dc = 0; dc <= FIFO_DEEP; dc++){
|
| 475 |
|
|
debug_temp = rbuffer[OI_ADDRESS];
|
| 476 |
|
|
debug_temp = debug_temp >> dc;
|
| 477 |
|
|
debug_temp &= 0x0001;
|
| 478 |
|
|
if(dc == 0){
|
| 479 |
|
|
cout << "router [" << router_id << "] OI receive data: \t";
|
| 480 |
|
|
cout << debug_temp;
|
| 481 |
|
|
}
|
| 482 |
|
|
else if(dc < FIFO_DEEP){
|
| 483 |
|
|
cout << debug_temp;
|
| 484 |
|
|
}
|
| 485 |
|
|
}
|
| 486 |
|
|
cout << endl;
|
| 487 |
|
|
#endif
|
| 488 |
|
|
}
|
| 489 |
|
|
}
|
| 490 |
|
|
}
|
| 491 |
|
|
}
|
| 492 |
|
|
wait();
|
| 493 |
|
|
}
|
| 494 |
|
|
}
|
| 495 |
|
|
|
| 496 |
|
|
void router :: direction_handle(){
|
| 497 |
|
|
sc_uint<8> ch = 0;
|
| 498 |
|
|
char state = 0;
|
| 499 |
|
|
|
| 500 |
|
|
ch = CORE_ADDRESS;
|
| 501 |
|
|
|
| 502 |
|
|
while(true){
|
| 503 |
|
|
if(!reset_n.read()){
|
| 504 |
|
|
control_state = 0;
|
| 505 |
|
|
}
|
| 506 |
|
|
else{
|
| 507 |
|
|
for(ch = 0; ch < 16; ch++){
|
| 508 |
|
|
if(rbuffer[ch] & REN){
|
| 509 |
|
|
if(port[ch].set == 1){
|
| 510 |
|
|
if(!(tbuffer[port[ch].outport + port[ch].out_ch] & WEN)){
|
| 511 |
|
|
tbuffer[port[ch].outport + port[ch].out_ch] = rbuffer[ch].range(15,0);
|
| 512 |
|
|
tbuffer[port[ch].outport + port[ch].out_ch] |= WEN;
|
| 513 |
|
|
rbuffer[ch] = 0;
|
| 514 |
|
|
rbuffer[ch] &= ~REN;
|
| 515 |
|
|
}
|
| 516 |
|
|
}
|
| 517 |
|
|
else if(port[ch].set == 0){
|
| 518 |
|
|
state = header_decoder(ch);
|
| 519 |
|
|
if(state != FAIL){
|
| 520 |
|
|
if(!(tbuffer[port[ch].outport + port[ch].out_ch] & WEN)){
|
| 521 |
|
|
tbuffer[port[ch].outport + port[ch].out_ch] = rbuffer[ch].range(15,0);
|
| 522 |
|
|
tbuffer[port[ch].outport + port[ch].out_ch] |= WEN;
|
| 523 |
|
|
rbuffer[ch] &= ~REN;
|
| 524 |
|
|
if(state == OIs){
|
| 525 |
|
|
if(ch < 3){
|
| 526 |
|
|
port[ch].outport = OI_ADDRESS;
|
| 527 |
|
|
port[ch].out_ch = 0;
|
| 528 |
|
|
port[ch].set = 1;
|
| 529 |
|
|
}
|
| 530 |
|
|
|
| 531 |
|
|
if(port[ch].outport == 0){
|
| 532 |
|
|
port[15].outport = 0;
|
| 533 |
|
|
port[15].out_ch = port[ch].out_ch;
|
| 534 |
|
|
port[ch].set = 0;
|
| 535 |
|
|
port[15].set = 1;
|
| 536 |
|
|
}
|
| 537 |
|
|
optical_sw(ch);
|
| 538 |
|
|
}
|
| 539 |
|
|
rbuffer[ch] = 0;
|
| 540 |
|
|
}
|
| 541 |
|
|
}
|
| 542 |
|
|
}
|
| 543 |
|
|
}
|
| 544 |
|
|
}
|
| 545 |
|
|
}
|
| 546 |
|
|
wait();
|
| 547 |
|
|
}
|
| 548 |
|
|
}
|
| 549 |
|
|
|
| 550 |
|
|
sc_uint<16> router :: out_direction(sc_uint<8> out_going, sc_uint<16> go_a, sc_uint<16> go_b,
|
| 551 |
|
|
sc_uint<16> go_c, sc_uint<16> go_d, sc_uint<16> go_e)
|
| 552 |
|
|
{
|
| 553 |
|
|
sc_uint<16> out_temp = 0;
|
| 554 |
|
|
|
| 555 |
|
|
if(out_going == EAST_ADDRESS){
|
| 556 |
|
|
out_temp = go_a;
|
| 557 |
|
|
}
|
| 558 |
|
|
else if(out_going == WEST_ADDRESS){
|
| 559 |
|
|
out_temp = go_b;
|
| 560 |
|
|
}
|
| 561 |
|
|
else if(out_going == NORTH_ADDRESS){
|
| 562 |
|
|
out_temp = go_c;
|
| 563 |
|
|
}
|
| 564 |
|
|
else if(out_going == SOUTH_ADDRESS){
|
| 565 |
|
|
out_temp = go_d;
|
| 566 |
|
|
}
|
| 567 |
|
|
else if(out_going == CORE_ADDRESS){
|
| 568 |
|
|
out_temp = go_e;
|
| 569 |
|
|
}
|
| 570 |
|
|
|
| 571 |
|
|
return out_temp;
|
| 572 |
|
|
}
|
| 573 |
|
|
|
| 574 |
|
|
void router :: optical_sw(sc_uint<8> ch)
|
| 575 |
|
|
{
|
| 576 |
|
|
sc_uint<16> out_temp = 0;
|
| 577 |
|
|
HEAD_FLIT *head_flit;
|
| 578 |
|
|
sc_uint<6> dst_x, dst_y, router_x, router_y;
|
| 579 |
|
|
sc_uint<16> temp;
|
| 580 |
|
|
sc_uint<2> ch_temp = 0;
|
| 581 |
|
|
unsigned short temp_s;
|
| 582 |
|
|
sc_uint<8> outgoing = 0;
|
| 583 |
|
|
|
| 584 |
|
|
temp = rbuffer[ch].range(15,0);
|
| 585 |
|
|
temp_s = temp;
|
| 586 |
|
|
head_flit = (HEAD_FLIT *)&temp_s;
|
| 587 |
|
|
|
| 588 |
|
|
//Header flit.
|
| 589 |
|
|
dst_x = head_flit->dst_addr % x_num;
|
| 590 |
|
|
dst_y = head_flit->dst_addr / y_num;
|
| 591 |
|
|
router_x = router_id % x_num;
|
| 592 |
|
|
router_y = router_id / y_num;
|
| 593 |
|
|
|
| 594 |
|
|
outgoing = direction_decision(dst_x, dst_y, router_x, router_y);
|
| 595 |
|
|
|
| 596 |
|
|
//input buffer number.
|
| 597 |
|
|
if(ch < 3){ //in core.
|
| 598 |
|
|
out_temp = out_direction(outgoing, CORE_TO_EAST, CORE_TO_WEST, CORE_TO_NORTH, CORE_TO_SOUTH, 0);
|
| 599 |
|
|
}
|
| 600 |
|
|
else if(ch < 6){ //in west
|
| 601 |
|
|
out_temp = out_direction(outgoing, 0, 0, WEST_TO_NORTH, WEST_TO_SOUTH, WEST_TO_CORE);
|
| 602 |
|
|
}
|
| 603 |
|
|
else if(ch < 9){ //in east
|
| 604 |
|
|
out_temp = out_direction(outgoing, 0, 0, EAST_TO_NORTH, EAST_TO_SOUTH, EAST_TO_CORE);
|
| 605 |
|
|
}
|
| 606 |
|
|
else if(ch < 12){ //in north
|
| 607 |
|
|
out_temp = out_direction(outgoing, NORTH_TO_EAST, NORTH_TO_WEST, 0, 0, NORTH_TO_CORE);
|
| 608 |
|
|
}
|
| 609 |
|
|
else if(ch < 15){ //in south
|
| 610 |
|
|
out_temp = out_direction(outgoing, SOUTH_TO_EAST, SOUTH_TO_WEST, 0, 0, NORTH_TO_CORE);
|
| 611 |
|
|
}
|
| 612 |
|
|
//cout << "sel " << hex << out_temp << endl;
|
| 613 |
|
|
control_state |= out_temp;
|
| 614 |
|
|
oi_control.write(control_state);
|
| 615 |
|
|
//cout << "control signal: " << hex << state_temp << endl;
|
| 616 |
|
|
}
|
