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schelleg |
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-----------------------------------------------------------------------------
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-- NoCem -- Network on Chip Emulation Tool for System on Chip Research
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-- and Implementations
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--
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-- Copyright (C) 2006 Graham Schelle, Dirk Grunwald
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--
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-- This program is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU General Public License
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-- as published by the Free Software Foundation; either version 2
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-- of the License, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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-- 02110-1301, USA.
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--
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-- The authors can be contacted by email: <schelleg,grunwald>@cs.colorado.edu
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--
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-- or by mail: Campus Box 430, Department of Computer Science,
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-- University of Colorado at Boulder, Boulder, Colorado 80309
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--------------------------------------------------------------------------------
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--
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2 |
schelleg |
-- Filename: ic_pkt_nocem.vhd
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4 |
schelleg |
--
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2 |
schelleg |
-- Description: the standard interconnect for pkts
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4 |
schelleg |
--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use work.pkg_nocem.all;
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entity ic_pkt_nocem is
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Port (
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-- arbitration lines (usage depends on underlying network)
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arb_req : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
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arb_cntrl_in : in arb_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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arb_grant : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
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arb_cntrl_out : out arb_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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--data and control incoming/outgoing line (usage depends on underlying network)
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datain : in data_array(NOCEM_NUM_AP-1 downto 0);
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datain_valid : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
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datain_recvd : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
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dataout : out data_array(NOCEM_NUM_AP-1 downto 0);
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dataout_valid : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
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dataout_recvd : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
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pkt_cntrl_in : in pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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pkt_cntrl_in_valid : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
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pkt_cntrl_in_recvd : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
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pkt_cntrl_out : out pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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pkt_cntrl_out_valid : out std_logic_vector(NOCEM_NUM_AP-1 downto 0);
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pkt_cntrl_out_recvd : in std_logic_vector(NOCEM_NUM_AP-1 downto 0);
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clk : in std_logic;
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rst : in std_logic
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);
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end ic_pkt_nocem;
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architecture Behavioral of ic_pkt_nocem is
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-- for type conversion of x,y coordinates to std_logic_vector
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signal local_arb_addr_converted : node_addr_array(NOCEM_NUM_AP-1 downto 0);
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-- an aggregration of the data lines, should help in looping to create necessary signals
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signal n_to_fifo_data : data_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_to_s_data : data_array(NOCEM_NUM_AP-1 downto 0);
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signal s_to_fifo_data : data_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_to_n_data : data_array(NOCEM_NUM_AP-1 downto 0);
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signal e_to_fifo_data : data_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_to_w_data : data_array(NOCEM_NUM_AP-1 downto 0);
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signal w_to_fifo_data : data_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_to_e_data : data_array(NOCEM_NUM_AP-1 downto 0);
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signal ap_to_fifo_data : data_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_to_node_data : data_array(NOCEM_NUM_AP-1 downto 0);
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signal node_to_fifo_data : data_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_to_ap_data : data_array(NOCEM_NUM_AP-1 downto 0);
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-- an aggregration of the pkt_cntrls, should help in looping to create necessary signals
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signal n_to_fifo_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_to_s_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal s_to_fifo_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_to_n_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal e_to_fifo_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_to_w_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal w_to_fifo_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_to_e_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal ap_to_fifo_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_to_node_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal node_to_fifo_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_to_ap_pkt_cntrl : pkt_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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-- an aggregration of the channel_cntrls, should help in looping to create necessary signals
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-- naming convention is : <direction from node> _ fifo channel control
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-- fifo _ <direction from node> channel control
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-- example n_fifo_ch_cntrl: from node channel of node to fifo below
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-- fifo_e_ch_cntrl: from fifo to east channel of node
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signal n_fifo_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_n_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal s_fifo_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_s_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal e_fifo_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_e_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal w_fifo_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_w_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal ap_fifo_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal fifo_ap_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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-- node: the actual PE, fifo connecting node to NoC switch
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signal fifo_node_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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signal node_fifo_ch_cntrl : channel_cntrl_array(NOCEM_NUM_AP-1 downto 0);
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-- signals that will be tied to (others => '0');
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signal data_z : data_word;
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signal pkt_cntrl_z : pkt_cntrl_word;
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signal ch_cntrl_z : channel_cntrl_word;
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begin
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data_z <= (others => '0');
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pkt_cntrl_z <= (others => '0');
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ch_cntrl_z <= (others => '0');
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--instantiate nodes, fifos
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g1: for I in NOCEM_NUM_AP-1 downto 0 generate
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local_arb_addr_converted(I) <= addr_gen(I,NOCEM_NUM_ROWS,NOCEM_NUM_COLS,NOCEM_AW);
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g11: if NOCEM_TYPE = NOCEM_VC_TYPE generate
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I_vc_node : vc_node PORT MAP(
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local_arb_addr => local_arb_addr_converted(I),
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n_datain => fifo_to_n_data(I),
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n_pkt_cntrl_in => fifo_to_n_pkt_cntrl(I),
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n_dataout => n_to_fifo_data(I),
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n_pkt_cntrl_out => n_to_fifo_pkt_cntrl(I),
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n_channel_cntrl_in => fifo_n_ch_cntrl(I),
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n_channel_cntrl_out => n_fifo_ch_cntrl(I),
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s_datain => fifo_to_s_data(I),
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s_pkt_cntrl_in => fifo_to_s_pkt_cntrl(I),
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s_dataout => s_to_fifo_data(I),
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s_pkt_cntrl_out => s_to_fifo_pkt_cntrl(I),
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s_channel_cntrl_in => fifo_s_ch_cntrl(I),
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s_channel_cntrl_out => s_fifo_ch_cntrl(I),
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e_datain => fifo_to_e_data(I),
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e_pkt_cntrl_in => fifo_to_e_pkt_cntrl(I),
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e_dataout => e_to_fifo_data(I),
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e_pkt_cntrl_out => e_to_fifo_pkt_cntrl(I),
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e_channel_cntrl_in => fifo_e_ch_cntrl(I),
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e_channel_cntrl_out => e_fifo_ch_cntrl(I),
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w_datain => fifo_to_w_data(I),
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w_pkt_cntrl_in => fifo_to_w_pkt_cntrl(I),
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w_dataout => w_to_fifo_data(I),
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w_pkt_cntrl_out => w_to_fifo_pkt_cntrl(I),
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w_channel_cntrl_in => fifo_w_ch_cntrl(I),
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w_channel_cntrl_out => w_fifo_ch_cntrl(I),
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ap_datain => fifo_to_ap_data(I),
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ap_pkt_cntrl_in => fifo_to_ap_pkt_cntrl(I),
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ap_dataout => ap_to_fifo_data(I),
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ap_pkt_cntrl_out => ap_to_fifo_pkt_cntrl(I),
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ap_channel_cntrl_in => fifo_ap_ch_cntrl(I),
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ap_channel_cntrl_out => ap_fifo_ch_cntrl(I),
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clk => clk,
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rst => rst
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);
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end generate;
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g12: if NOCEM_TYPE = NOCEM_SIMPLE_PKT_TYPE generate
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I_simple_pkt_node : simple_pkt_node PORT MAP(
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local_arb_addr => local_arb_addr_converted(I),
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n_datain => fifo_to_n_data(I),
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n_pkt_cntrl_in => fifo_to_n_pkt_cntrl(I),
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n_dataout => n_to_fifo_data(I),
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n_pkt_cntrl_out => n_to_fifo_pkt_cntrl(I),
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n_channel_cntrl_in => fifo_n_ch_cntrl(I),
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n_channel_cntrl_out => n_fifo_ch_cntrl(I),
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s_datain => fifo_to_s_data(I),
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s_pkt_cntrl_in => fifo_to_s_pkt_cntrl(I),
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s_dataout => s_to_fifo_data(I),
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s_pkt_cntrl_out => s_to_fifo_pkt_cntrl(I),
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s_channel_cntrl_in => fifo_s_ch_cntrl(I),
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s_channel_cntrl_out => s_fifo_ch_cntrl(I),
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e_datain => fifo_to_e_data(I),
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e_pkt_cntrl_in => fifo_to_e_pkt_cntrl(I),
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e_dataout => e_to_fifo_data(I),
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e_pkt_cntrl_out => e_to_fifo_pkt_cntrl(I),
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e_channel_cntrl_in => fifo_e_ch_cntrl(I),
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e_channel_cntrl_out => e_fifo_ch_cntrl(I),
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w_datain => fifo_to_w_data(I),
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w_pkt_cntrl_in => fifo_to_w_pkt_cntrl(I),
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w_dataout => w_to_fifo_data(I),
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w_pkt_cntrl_out => w_to_fifo_pkt_cntrl(I),
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w_channel_cntrl_in => fifo_w_ch_cntrl(I),
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w_channel_cntrl_out => w_fifo_ch_cntrl(I),
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ap_datain => fifo_to_ap_data(I),
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ap_pkt_cntrl_in => fifo_to_ap_pkt_cntrl(I),
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ap_dataout => ap_to_fifo_data(I),
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ap_pkt_cntrl_out => ap_to_fifo_pkt_cntrl(I),
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ap_channel_cntrl_in => fifo_ap_ch_cntrl(I),
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ap_channel_cntrl_out => ap_fifo_ch_cntrl(I),
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clk => clk,
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rst => rst
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);
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end generate;
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end generate;
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-- generate the fifos on outgoing paths
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g2 : for I in NOCEM_NUM_AP-1 downto 0 generate
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---------------------------------------------------------------
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------ TOPLVEL WIRING ----
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---------------------------------------------------------------
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|
|
|
| 291 |
|
|
channel_cntrl_handling : process (arb_cntrl_in,node_fifo_ch_cntrl,datain_valid, arb_req, fifo_node_ch_cntrl, pkt_cntrl_in_valid, dataout_recvd, pkt_cntrl_out_recvd)
|
| 292 |
|
|
begin
|
| 293 |
|
|
|
| 294 |
|
|
arb_cntrl_out(I) <= (others => '0');
|
| 295 |
|
|
|
| 296 |
|
|
-- first set control all to zeroes, let following statements overwrite values
|
| 297 |
|
|
node_fifo_ch_cntrl(I) <= (others => '0');
|
| 298 |
|
|
|
| 299 |
|
|
-- WE gets set when request comes in and the FIFO is not full
|
| 300 |
|
|
if NOCEM_TYPE = NOCEM_VC_TYPE then
|
| 301 |
|
|
-- with VCs, things are a little simpler....
|
| 302 |
|
|
node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_WE_IX) <= arb_req(I) and datain_valid(I);
|
| 303 |
|
|
node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= arb_req(I) and pkt_cntrl_in_valid(I);
|
| 304 |
|
|
|
| 305 |
|
|
-- grant occurs when a write enable is allowed (see lines above)
|
| 306 |
|
|
arb_grant(I) <= node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_WE_IX) or node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_WE_IX);
|
| 307 |
|
|
|
| 308 |
|
|
datain_recvd(I) <= node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_WE_IX);
|
| 309 |
|
|
pkt_cntrl_in_recvd(I) <= node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_WE_IX);
|
| 310 |
|
|
|
| 311 |
|
|
|
| 312 |
|
|
-- handling dataout valid, recvd signals
|
| 313 |
|
|
-- for VCs, the state of dataout is controlled by user watching for full packets
|
| 314 |
|
|
dataout_valid(I) <= '1';
|
| 315 |
|
|
node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_RE_IX) <= dataout_recvd(I);
|
| 316 |
|
|
|
| 317 |
|
|
pkt_cntrl_out_valid(I) <= '1';
|
| 318 |
|
|
node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_RE_IX) <= pkt_cntrl_out_recvd(I);
|
| 319 |
|
|
node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_VC_RD_ADDR_HIX downto NOCEM_CHFIFO_VC_RD_ADDR_LIX) <= arb_cntrl_in(I)(NOCEM_ARB_CNTRL_VC_MUX_RD_HIX downto NOCEM_ARB_CNTRL_VC_MUX_RD_LIX);
|
| 320 |
|
|
|
| 321 |
|
|
else
|
| 322 |
|
|
node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_WE_IX) <= arb_req(I) and datain_valid(I) and fifo_node_ch_cntrl(I)(NOCEM_CHFIFO_DATA_FULL_N_IX);
|
| 323 |
|
|
node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_WE_IX) <= arb_req(I) and pkt_cntrl_in_valid(I) and fifo_node_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_FULL_N_IX);
|
| 324 |
|
|
|
| 325 |
|
|
-- grant occurs when a write enable is allowed (see lines above)
|
| 326 |
|
|
arb_grant(I) <= node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_WE_IX) or node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_WE_IX);
|
| 327 |
|
|
|
| 328 |
|
|
datain_recvd(I) <= node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_WE_IX);
|
| 329 |
|
|
pkt_cntrl_in_recvd(I) <= node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_WE_IX);
|
| 330 |
|
|
|
| 331 |
|
|
-- handling dataout valid, recvd signals
|
| 332 |
|
|
dataout_valid(I) <= fifo_node_ch_cntrl(I)(NOCEM_CHFIFO_DATA_EMPTY_N_IX);
|
| 333 |
|
|
node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_DATA_RE_IX) <= dataout_recvd(I);
|
| 334 |
|
|
|
| 335 |
|
|
pkt_cntrl_out_valid(I) <= fifo_node_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_EMPTY_N_IX);
|
| 336 |
|
|
node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_CNTRL_RE_IX) <= pkt_cntrl_out_recvd(I);
|
| 337 |
|
|
|
| 338 |
|
|
end if;
|
| 339 |
|
|
|
| 340 |
|
|
|
| 341 |
|
|
|
| 342 |
|
|
-- VC signalling to/from node
|
| 343 |
|
|
node_fifo_ch_cntrl(I)(NOCEM_CHFIFO_VC_WR_ADDR_HIX downto NOCEM_CHFIFO_VC_WR_ADDR_LIX) <= arb_cntrl_in(I)(NOCEM_ARB_CNTRL_VC_MUX_WR_HIX downto NOCEM_ARB_CNTRL_VC_MUX_WR_LIX);
|
| 344 |
|
|
arb_cntrl_out(I)(NOCEM_ARB_CNTRL_VC_EOP_WR_HIX downto NOCEM_ARB_CNTRL_VC_EOP_WR_LIX) <= fifo_node_ch_cntrl(I)(NOCEM_CHFIFO_VC_EOP_WR_HIX downto NOCEM_CHFIFO_VC_EOP_WR_LIX);
|
| 345 |
|
|
arb_cntrl_out(I)(NOCEM_ARB_CNTRL_VC_EOP_RD_HIX downto NOCEM_ARB_CNTRL_VC_EOP_RD_LIX) <= fifo_node_ch_cntrl(I)(NOCEM_CHFIFO_VC_EOP_RD_HIX downto NOCEM_CHFIFO_VC_EOP_RD_LIX);
|
| 346 |
|
|
|
| 347 |
|
|
--constant NOCEM_ARB_CNTRL_VC_EOP_RD_LIX : integer := NOCEM_ARB_CNTRL_VC_MUX_RD_HIX+1; --8
|
| 348 |
|
|
--constant NOCEM_ARB_CNTRL_VC_EOP_RD_HIX : integer := NOCEM_ARB_CNTRL_VC_EOP_RD_LIX+NOCEM_NUM_VC-1;
|
| 349 |
|
|
--
|
| 350 |
|
|
--constant NOCEM_ARB_CNTRL_VC_EOP_WR_LIX : integer := NOCEM_ARB_CNTRL_VC_EOP_RD_HIX+1; --12
|
| 351 |
|
|
--constant NOCEM_ARB_CNTRL_VC_EOP_WR_HIX : integer := NOCEM_ARB_CNTRL_VC_EOP_WR_LIX+NOCEM_NUM_VC-1;
|
| 352 |
|
|
--
|
| 353 |
|
|
|
| 354 |
|
|
end process;
|
| 355 |
|
|
|
| 356 |
|
|
|
| 357 |
|
|
---------------------------------------------------------------
|
| 358 |
|
|
---------------------------------------------------------------
|
| 359 |
|
|
------ ACCESS POINT FIFOs ----
|
| 360 |
|
|
---------------------------------------------------------------
|
| 361 |
|
|
---------------------------------------------------------------
|
| 362 |
|
|
|
| 363 |
|
|
channel_ap_noc : channel_fifo
|
| 364 |
|
|
generic map(
|
| 365 |
|
|
P0_NODE_ADDR => I,
|
| 366 |
|
|
P1_NODE_ADDR => I,
|
| 367 |
|
|
IS_AN_ACCESS_POINT_CHANNEL => TRUE
|
| 368 |
|
|
)
|
| 369 |
|
|
PORT MAP(
|
| 370 |
|
|
p0_datain => datain(I),
|
| 371 |
|
|
p0_pkt_cntrl_in => pkt_cntrl_in(I),
|
| 372 |
|
|
p0_dataout => dataout(I),
|
| 373 |
|
|
p0_pkt_cntrl_out => pkt_cntrl_out(I),
|
| 374 |
|
|
p0_channel_cntrl_in => node_fifo_ch_cntrl(I),
|
| 375 |
|
|
p0_channel_cntrl_out => fifo_node_ch_cntrl(I),
|
| 376 |
|
|
p1_datain => ap_to_fifo_data(I),
|
| 377 |
|
|
p1_pkt_cntrl_in => ap_to_fifo_pkt_cntrl(I),
|
| 378 |
|
|
p1_dataout => fifo_to_ap_data(I),
|
| 379 |
|
|
p1_pkt_cntrl_out => fifo_to_ap_pkt_cntrl(I),
|
| 380 |
|
|
p1_channel_cntrl_in => ap_fifo_ch_cntrl(I),
|
| 381 |
|
|
p1_channel_cntrl_out => fifo_ap_ch_cntrl(I),
|
| 382 |
|
|
clk => clk,
|
| 383 |
|
|
rst => rst
|
| 384 |
|
|
);
|
| 385 |
|
|
|
| 386 |
|
|
|
| 387 |
|
|
|
| 388 |
|
|
---------------------------------------------------------------
|
| 389 |
|
|
---------------------------------------------------------------
|
| 390 |
|
|
------ NORTH / SOUTH FIFOs ----
|
| 391 |
|
|
---------------------------------------------------------------
|
| 392 |
|
|
---------------------------------------------------------------
|
| 393 |
|
|
|
| 394 |
|
|
-- top: top of chip, with ap's below it
|
| 395 |
|
|
-- middle: middle of chip, ap's above and beloe
|
| 396 |
|
|
-- bottom: bottom of chip, with ap's above it
|
| 397 |
|
|
-- single row: no need for north south fifos
|
| 398 |
|
|
|
| 399 |
|
|
|
| 400 |
|
|
-- top of chip
|
| 401 |
|
|
g3: if (I+NOCEM_NUM_COLS) / NOCEM_NUM_COLS = NOCEM_NUM_ROWS and NOCEM_NUM_ROWS /= 1 generate
|
| 402 |
|
|
|
| 403 |
|
|
|
| 404 |
|
|
|
| 405 |
|
|
|
| 406 |
|
|
|
| 407 |
|
|
g33: if NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_TORUS or
|
| 408 |
|
|
NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_DTORUS generate
|
| 409 |
|
|
|
| 410 |
|
|
channel_ns_tdt : channel_fifo
|
| 411 |
|
|
generic map(
|
| 412 |
|
|
P0_NODE_ADDR => I,
|
| 413 |
|
|
P1_NODE_ADDR => I mod NOCEM_NUM_COLS,
|
| 414 |
|
|
IS_AN_ACCESS_POINT_CHANNEL => FALSE
|
| 415 |
|
|
)
|
| 416 |
|
|
PORT MAP(
|
| 417 |
|
|
p0_datain => n_to_fifo_data(I),
|
| 418 |
|
|
p0_pkt_cntrl_in => n_to_fifo_pkt_cntrl(I),
|
| 419 |
|
|
p0_dataout => fifo_to_n_data(I),
|
| 420 |
|
|
p0_pkt_cntrl_out => fifo_to_n_pkt_cntrl(I),
|
| 421 |
|
|
p0_channel_cntrl_in => n_fifo_ch_cntrl(I),
|
| 422 |
|
|
p0_channel_cntrl_out => fifo_n_ch_cntrl(I),
|
| 423 |
|
|
p1_datain => s_to_fifo_data(I mod NOCEM_NUM_COLS),
|
| 424 |
|
|
p1_pkt_cntrl_in => s_to_fifo_pkt_cntrl(I mod NOCEM_NUM_COLS),
|
| 425 |
|
|
p1_dataout => fifo_to_s_data(I mod NOCEM_NUM_COLS),
|
| 426 |
|
|
p1_pkt_cntrl_out => fifo_to_s_pkt_cntrl(I mod NOCEM_NUM_COLS),
|
| 427 |
|
|
p1_channel_cntrl_in => s_fifo_ch_cntrl(I mod NOCEM_NUM_COLS),
|
| 428 |
|
|
p1_channel_cntrl_out => fifo_s_ch_cntrl(I mod NOCEM_NUM_COLS),
|
| 429 |
|
|
clk => clk,
|
| 430 |
|
|
rst => rst
|
| 431 |
|
|
);
|
| 432 |
|
|
|
| 433 |
|
|
|
| 434 |
|
|
|
| 435 |
|
|
end generate;
|
| 436 |
|
|
|
| 437 |
|
|
|
| 438 |
|
|
g34: if NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_MESH generate
|
| 439 |
|
|
|
| 440 |
|
|
|
| 441 |
|
|
-- leave here just in case....
|
| 442 |
|
|
-- channel_ns_mesh : channel_fifo PORT MAP(
|
| 443 |
|
|
-- p0_datain => data_z,
|
| 444 |
|
|
-- p0_pkt_cntrl_in => pkt_cntrl_z,
|
| 445 |
|
|
-- p0_dataout => open,
|
| 446 |
|
|
-- p0_pkt_cntrl_out => open,
|
| 447 |
|
|
-- p0_channel_cntrl_in => ch_cntrl_z,
|
| 448 |
|
|
-- p0_channel_cntrl_out => open,
|
| 449 |
|
|
-- p1_datain => data_z,
|
| 450 |
|
|
-- p1_pkt_cntrl_in => pkt_cntrl_z,
|
| 451 |
|
|
-- p1_dataout => open,
|
| 452 |
|
|
-- p1_pkt_cntrl_out => open,
|
| 453 |
|
|
-- p1_channel_cntrl_in => ch_cntrl_z,
|
| 454 |
|
|
-- p1_channel_cntrl_out => open,
|
| 455 |
|
|
-- clk => clk,
|
| 456 |
|
|
-- rst => rst
|
| 457 |
|
|
-- );
|
| 458 |
|
|
|
| 459 |
|
|
end generate;
|
| 460 |
|
|
|
| 461 |
|
|
|
| 462 |
|
|
end generate;
|
| 463 |
|
|
|
| 464 |
|
|
|
| 465 |
|
|
|
| 466 |
|
|
|
| 467 |
|
|
|
| 468 |
|
|
-- bottom of chip
|
| 469 |
|
|
g4: if I / NOCEM_NUM_COLS = 0 and NOCEM_NUM_ROWS /= 1 generate
|
| 470 |
|
|
|
| 471 |
|
|
|
| 472 |
|
|
|
| 473 |
|
|
channel_ns : channel_fifo
|
| 474 |
|
|
generic map(
|
| 475 |
|
|
P0_NODE_ADDR => I,
|
| 476 |
|
|
P1_NODE_ADDR => I+NOCEM_NUM_COLS,
|
| 477 |
|
|
IS_AN_ACCESS_POINT_CHANNEL => FALSE
|
| 478 |
|
|
)
|
| 479 |
|
|
PORT MAP(
|
| 480 |
|
|
p0_datain => n_to_fifo_data(I),
|
| 481 |
|
|
p0_pkt_cntrl_in => n_to_fifo_pkt_cntrl(I),
|
| 482 |
|
|
p0_dataout => fifo_to_n_data(I),
|
| 483 |
|
|
p0_pkt_cntrl_out => fifo_to_n_pkt_cntrl(I),
|
| 484 |
|
|
p0_channel_cntrl_in => n_fifo_ch_cntrl(I),
|
| 485 |
|
|
p0_channel_cntrl_out => fifo_n_ch_cntrl(I),
|
| 486 |
|
|
|
| 487 |
|
|
p1_datain => s_to_fifo_data(I+NOCEM_NUM_COLS),
|
| 488 |
|
|
p1_pkt_cntrl_in => s_to_fifo_pkt_cntrl(I+NOCEM_NUM_COLS),
|
| 489 |
|
|
p1_dataout => fifo_to_s_data(I+NOCEM_NUM_COLS),
|
| 490 |
|
|
p1_pkt_cntrl_out => fifo_to_s_pkt_cntrl(I+NOCEM_NUM_COLS),
|
| 491 |
|
|
p1_channel_cntrl_in => s_fifo_ch_cntrl(I+NOCEM_NUM_COLS),
|
| 492 |
|
|
p1_channel_cntrl_out => fifo_s_ch_cntrl(I+NOCEM_NUM_COLS),
|
| 493 |
|
|
|
| 494 |
|
|
clk => clk,
|
| 495 |
|
|
rst => rst
|
| 496 |
|
|
);
|
| 497 |
|
|
|
| 498 |
|
|
|
| 499 |
|
|
|
| 500 |
|
|
|
| 501 |
|
|
|
| 502 |
|
|
|
| 503 |
|
|
|
| 504 |
|
|
|
| 505 |
|
|
end generate;
|
| 506 |
|
|
|
| 507 |
|
|
-- middle of chip
|
| 508 |
|
|
g5: if I / NOCEM_NUM_COLS /= 0 and (I+NOCEM_NUM_COLS) / NOCEM_NUM_COLS /= NOCEM_NUM_ROWS and NOCEM_NUM_ROWS /= 1 generate
|
| 509 |
|
|
|
| 510 |
|
|
|
| 511 |
|
|
channel_ns : channel_fifo
|
| 512 |
|
|
generic map(
|
| 513 |
|
|
P0_NODE_ADDR => I,
|
| 514 |
|
|
P1_NODE_ADDR => I+NOCEM_NUM_COLS,
|
| 515 |
|
|
IS_AN_ACCESS_POINT_CHANNEL => FALSE
|
| 516 |
|
|
)
|
| 517 |
|
|
PORT MAP(
|
| 518 |
|
|
p0_datain => n_to_fifo_data(I),
|
| 519 |
|
|
p0_pkt_cntrl_in => n_to_fifo_pkt_cntrl(I),
|
| 520 |
|
|
p0_dataout => fifo_to_n_data(I),
|
| 521 |
|
|
p0_pkt_cntrl_out => fifo_to_n_pkt_cntrl(I),
|
| 522 |
|
|
p0_channel_cntrl_in => n_fifo_ch_cntrl(I),
|
| 523 |
|
|
p0_channel_cntrl_out => fifo_n_ch_cntrl(I),
|
| 524 |
|
|
|
| 525 |
|
|
p1_datain => s_to_fifo_data(I+NOCEM_NUM_COLS),
|
| 526 |
|
|
p1_pkt_cntrl_in => s_to_fifo_pkt_cntrl(I+NOCEM_NUM_COLS),
|
| 527 |
|
|
p1_dataout => fifo_to_s_data(I+NOCEM_NUM_COLS),
|
| 528 |
|
|
p1_pkt_cntrl_out => fifo_to_s_pkt_cntrl(I+NOCEM_NUM_COLS),
|
| 529 |
|
|
p1_channel_cntrl_in => s_fifo_ch_cntrl(I+NOCEM_NUM_COLS),
|
| 530 |
|
|
p1_channel_cntrl_out => fifo_s_ch_cntrl(I+NOCEM_NUM_COLS),
|
| 531 |
|
|
|
| 532 |
|
|
clk => clk,
|
| 533 |
|
|
rst => rst
|
| 534 |
|
|
);
|
| 535 |
|
|
|
| 536 |
|
|
|
| 537 |
|
|
|
| 538 |
|
|
|
| 539 |
|
|
|
| 540 |
|
|
|
| 541 |
|
|
|
| 542 |
|
|
end generate;
|
| 543 |
|
|
|
| 544 |
|
|
-- single row
|
| 545 |
|
|
g6: if NOCEM_NUM_ROWS = 1 generate
|
| 546 |
|
|
|
| 547 |
|
|
end generate;
|
| 548 |
|
|
|
| 549 |
|
|
|
| 550 |
|
|
|
| 551 |
|
|
---------------------------------------------------------------
|
| 552 |
|
|
---------------------------------------------------------------
|
| 553 |
|
|
------ EAST / WEST FIFOs ----
|
| 554 |
|
|
---------------------------------------------------------------
|
| 555 |
|
|
---------------------------------------------------------------
|
| 556 |
|
|
|
| 557 |
|
|
|
| 558 |
|
|
-- left side of chip
|
| 559 |
|
|
g7: if I mod NOCEM_NUM_COLS = 0 and NOCEM_NUM_COLS /= 1 generate
|
| 560 |
|
|
|
| 561 |
|
|
|
| 562 |
|
|
|
| 563 |
|
|
|
| 564 |
|
|
|
| 565 |
|
|
|
| 566 |
|
|
|
| 567 |
|
|
|
| 568 |
|
|
channel_ew : channel_fifo
|
| 569 |
|
|
generic map(
|
| 570 |
|
|
P0_NODE_ADDR => I,
|
| 571 |
|
|
P1_NODE_ADDR => I+1,
|
| 572 |
|
|
IS_AN_ACCESS_POINT_CHANNEL => FALSE
|
| 573 |
|
|
)
|
| 574 |
|
|
PORT MAP(
|
| 575 |
|
|
p0_datain => e_to_fifo_data(I),
|
| 576 |
|
|
p0_pkt_cntrl_in => e_to_fifo_pkt_cntrl(I),
|
| 577 |
|
|
p0_dataout => fifo_to_e_data(I),
|
| 578 |
|
|
p0_pkt_cntrl_out => fifo_to_e_pkt_cntrl(I),
|
| 579 |
|
|
p0_channel_cntrl_in => e_fifo_ch_cntrl(I),
|
| 580 |
|
|
p0_channel_cntrl_out => fifo_e_ch_cntrl(I),
|
| 581 |
|
|
|
| 582 |
|
|
p1_datain => w_to_fifo_data(I+1),
|
| 583 |
|
|
p1_pkt_cntrl_in => w_to_fifo_pkt_cntrl(I+1),
|
| 584 |
|
|
p1_dataout => fifo_to_w_data(I+1),
|
| 585 |
|
|
p1_pkt_cntrl_out => fifo_to_w_pkt_cntrl(I+1),
|
| 586 |
|
|
p1_channel_cntrl_in => w_fifo_ch_cntrl(I+1),
|
| 587 |
|
|
p1_channel_cntrl_out => fifo_w_ch_cntrl(I+1),
|
| 588 |
|
|
|
| 589 |
|
|
clk => clk,
|
| 590 |
|
|
rst => rst
|
| 591 |
|
|
);
|
| 592 |
|
|
|
| 593 |
|
|
|
| 594 |
|
|
|
| 595 |
|
|
|
| 596 |
|
|
|
| 597 |
|
|
|
| 598 |
|
|
|
| 599 |
|
|
|
| 600 |
|
|
end generate;
|
| 601 |
|
|
|
| 602 |
|
|
|
| 603 |
|
|
-- right side of chip
|
| 604 |
|
|
g8: if I mod NOCEM_NUM_COLS = NOCEM_NUM_COLS-1 and NOCEM_NUM_COLS /= 1 generate
|
| 605 |
|
|
|
| 606 |
|
|
-- only do this on double torus
|
| 607 |
|
|
g81: if NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_DTORUS generate
|
| 608 |
|
|
|
| 609 |
|
|
channel_ew_dt : channel_fifo
|
| 610 |
|
|
generic map(
|
| 611 |
|
|
P0_NODE_ADDR => I,
|
| 612 |
|
|
P1_NODE_ADDR => I-NOCEM_NUM_COLS+1,
|
| 613 |
|
|
IS_AN_ACCESS_POINT_CHANNEL => FALSE
|
| 614 |
|
|
)
|
| 615 |
|
|
PORT MAP(
|
| 616 |
|
|
p0_datain => e_to_fifo_data(I),
|
| 617 |
|
|
p0_pkt_cntrl_in => e_to_fifo_pkt_cntrl(I),
|
| 618 |
|
|
p0_dataout => fifo_to_e_data(I),
|
| 619 |
|
|
p0_pkt_cntrl_out => fifo_to_e_pkt_cntrl(I),
|
| 620 |
|
|
p0_channel_cntrl_in => e_fifo_ch_cntrl(I),
|
| 621 |
|
|
p0_channel_cntrl_out => fifo_e_ch_cntrl(I),
|
| 622 |
|
|
|
| 623 |
|
|
p1_datain => w_to_fifo_data(I-NOCEM_NUM_COLS+1),
|
| 624 |
|
|
p1_pkt_cntrl_in => w_to_fifo_pkt_cntrl(I-NOCEM_NUM_COLS+1),
|
| 625 |
|
|
p1_dataout => fifo_to_w_data(I-NOCEM_NUM_COLS+1),
|
| 626 |
|
|
p1_pkt_cntrl_out => fifo_to_w_pkt_cntrl(I-NOCEM_NUM_COLS+1),
|
| 627 |
|
|
p1_channel_cntrl_in => w_fifo_ch_cntrl(I-NOCEM_NUM_COLS+1),
|
| 628 |
|
|
p1_channel_cntrl_out => fifo_w_ch_cntrl(I-NOCEM_NUM_COLS+1),
|
| 629 |
|
|
|
| 630 |
|
|
clk => clk,
|
| 631 |
|
|
rst => rst
|
| 632 |
|
|
);
|
| 633 |
|
|
|
| 634 |
|
|
end generate;
|
| 635 |
|
|
|
| 636 |
|
|
|
| 637 |
|
|
g82: if NOCEM_TOPOLOGY_TYPE = NOCEM_TOPOLOGY_MESH generate
|
| 638 |
|
|
|
| 639 |
|
|
-- channel_ew_mesht : channel_fifo PORT MAP(
|
| 640 |
|
|
-- p0_datain => data_z,
|
| 641 |
|
|
-- p0_pkt_cntrl_in => pkt_cntrl_z,
|
| 642 |
|
|
-- p0_dataout => open,
|
| 643 |
|
|
-- p0_pkt_cntrl_out => open,
|
| 644 |
|
|
-- p0_channel_cntrl_in => ch_cntrl_z,
|
| 645 |
|
|
-- p0_channel_cntrl_out => open,
|
| 646 |
|
|
-- p1_datain => data_z,
|
| 647 |
|
|
-- p1_pkt_cntrl_in => pkt_cntrl_z,
|
| 648 |
|
|
-- p1_dataout => open,
|
| 649 |
|
|
-- p1_pkt_cntrl_out => open,
|
| 650 |
|
|
-- p1_channel_cntrl_in => ch_cntrl_z,
|
| 651 |
|
|
-- p1_channel_cntrl_out => open,
|
| 652 |
|
|
-- clk => clk,
|
| 653 |
|
|
-- rst => rst
|
| 654 |
|
|
-- );
|
| 655 |
|
|
--
|
| 656 |
|
|
end generate;
|
| 657 |
|
|
|
| 658 |
|
|
end generate;
|
| 659 |
|
|
|
| 660 |
|
|
|
| 661 |
|
|
-- middle of chip (in terms of columns)
|
| 662 |
|
|
g9: if I mod NOCEM_NUM_COLS /= NOCEM_NUM_COLS-1 and I mod NOCEM_NUM_COLS /= 0 and NOCEM_NUM_COLS /= 1 generate
|
| 663 |
|
|
|
| 664 |
|
|
|
| 665 |
|
|
channel_ew : channel_fifo
|
| 666 |
|
|
generic map(
|
| 667 |
|
|
P0_NODE_ADDR => I,
|
| 668 |
|
|
P1_NODE_ADDR => I+1,
|
| 669 |
|
|
IS_AN_ACCESS_POINT_CHANNEL => FALSE
|
| 670 |
|
|
)
|
| 671 |
|
|
|
| 672 |
|
|
PORT MAP(
|
| 673 |
|
|
p0_datain => e_to_fifo_data(I),
|
| 674 |
|
|
p0_pkt_cntrl_in => e_to_fifo_pkt_cntrl(I),
|
| 675 |
|
|
p0_dataout => fifo_to_e_data(I),
|
| 676 |
|
|
p0_pkt_cntrl_out => fifo_to_e_pkt_cntrl(I),
|
| 677 |
|
|
p0_channel_cntrl_in => e_fifo_ch_cntrl(I),
|
| 678 |
|
|
p0_channel_cntrl_out => fifo_e_ch_cntrl(I),
|
| 679 |
|
|
|
| 680 |
|
|
p1_datain => w_to_fifo_data(I+1),
|
| 681 |
|
|
p1_pkt_cntrl_in => w_to_fifo_pkt_cntrl(I+1),
|
| 682 |
|
|
p1_dataout => fifo_to_w_data(I+1),
|
| 683 |
|
|
p1_pkt_cntrl_out => fifo_to_w_pkt_cntrl(I+1),
|
| 684 |
|
|
p1_channel_cntrl_in => w_fifo_ch_cntrl(I+1),
|
| 685 |
|
|
p1_channel_cntrl_out => fifo_w_ch_cntrl(I+1),
|
| 686 |
|
|
|
| 687 |
|
|
clk => clk,
|
| 688 |
|
|
rst => rst
|
| 689 |
|
|
);
|
| 690 |
|
|
|
| 691 |
|
|
|
| 692 |
|
|
|
| 693 |
|
|
|
| 694 |
|
|
end generate;
|
| 695 |
|
|
|
| 696 |
|
|
|
| 697 |
|
|
-- single column
|
| 698 |
|
|
g10: if NOCEM_NUM_COLS = 1 generate
|
| 699 |
|
|
|
| 700 |
|
|
|
| 701 |
|
|
|
| 702 |
|
|
end generate;
|
| 703 |
|
|
|
| 704 |
|
|
|
| 705 |
|
|
|
| 706 |
|
|
end generate;
|
| 707 |
|
|
|
| 708 |
|
|
|
| 709 |
|
|
|
| 710 |
|
|
end Behavioral;
|
