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[/] [nocem/] [trunk/] [VHDL/] [vc_vc_alloc_arb.vhd] - Blame information for rev 8

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-----------------------------------------------------------------------------
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-- NoCem -- Network on Chip Emulation Tool for System on Chip Research 
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-- and Implementations
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-- 
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-- Copyright (C) 2006  Graham Schelle, Dirk Grunwald
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-- 
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-- This program is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU General Public License
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-- as published by the Free Software Foundation; either version 2
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-- of the License, or (at your option) any later version.
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-- 
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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-- GNU General Public License for more details.
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-- 
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  
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-- 02110-1301, USA.
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-- 
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-- The authors can be contacted by email: <schelleg,grunwald>@cs.colorado.edu 
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-- 
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-- or by mail: Campus Box 430, Department of Computer Science,
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-- University of Colorado at Boulder, Boulder, Colorado 80309
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-------------------------------------------------------------------------------- 
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-- 
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-- Filename: vc_vc_alloc_arb.vhd
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-- 
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-- Description: vc allocation arbiter
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-- 
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--------------------------------------------------------------------------------
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-- Company: 
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-- Engineer:
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--
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-- Create Date:    15:18:42 03/14/06
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-- Design Name:    
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-- Module Name:    vc_vc_alloc_arb - Behavioral
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-- Project Name:   
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-- Target Device:  
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-- Tool versions:  
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-- Description:
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--
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-- Dependencies:
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-- 
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- 
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity vc_vc_alloc_arb is
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    Port ( clk : in std_logic;
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           rst : in std_logic);
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end vc_vc_alloc_arb;
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architecture Behavioral of vc_vc_alloc_arb is
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begin
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end Behavioral;

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