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#!/usr/bin/env python
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# -*- coding: utf-8 -*-
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#
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# NoC Code generator - VHDL generator
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#
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# Author: Oscar Diaz
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# Version: 0.1
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# Date: 11-11-2011
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#
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# This code is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This code is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, write to the
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# Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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# Boston, MA 02111-1307 USA
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#
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#
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# Changelog:
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#
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# 11-11-2011 : (OD) initial release
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#
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"""
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Code generation support for VHDL
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This module defines:
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* Class 'noc_codegen_vhdl'
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* Function 'add_codegen_vhdl_support'
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"""
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from nocmodel import *
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from noc_codegen_base import *
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from myhdl import intbv, bin
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class noc_codegen_vhdl(noc_codegen_base):
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"""
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VHDL generator class
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This class defines methods used to generate VHDL code from any noc object.
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Like base class, this object has this base attributes:
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* docheader
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* libraries
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* modulename
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* generics
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* ports
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* implementation
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"""
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def __init__(self, nocobject_ref, **kwargs):
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noc_codegen_base.__init__(self, nocobject_ref, **kwargs)
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# note: the noc object must be complete, in order to
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# add code generation support
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#self.nocobject_ref = nocobject_ref
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self.modulename = self.to_valid_str(self.nocobject_ref.name)
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# default header and libraries
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self.docheader = "-- Document header"
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self.libraries = "library ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.numeric_std.all;"
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# code generation attributes
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self.usetab = " " # 4-space tabs
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self.full_comments = True
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# main methods
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def generate_file(self):
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"""
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Generate the entire file that implements this object.
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"""
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# Unless code generation is externally generated.
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if self.external_conversion:
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# use "codemodel" object on nocobject_ref
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if hasattr(self.nocobject_ref, "codemodel"):
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return self.nocobject_ref.codemodel.generate_file()
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else:
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raise AttributeError("External conversion flag is enabled, but there's no 'codemodel' object available in nocobject %s" % self.nocobject_ref)
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else:
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# first try to call build_implementation() method
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self.build_implementation()
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sret = self.docheader + "\n\n" + self.libraries + "\n\n"
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if self.full_comments:
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sret += self.make_comment("Object '%s' name '%s' description '%s'\n" % (repr(self.nocobject_ref), self.nocobject_ref.name, self.nocobject_ref.description))
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sret += self.generate_entity_section() + "\n\n"
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sret += self.generate_architecture_section() + "\n"
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return sret
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def generate_component(self):
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"""
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Generate a component definition for this object.
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"""
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sret = "component %s\n" % self.modulename
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stmp = self.generate_generics_section()
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if stmp != "":
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sret += self.add_tab(stmp) + ";\n"
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stmp = self.generate_ports_section()
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if stmp != "":
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sret += self.add_tab(stmp) + ";\n"
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sret += "end component;\n"
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return sret
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def generate_generic_declaration(self, generic=None, with_default=False):
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"""
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Generate a generic declaration for this object.
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Arguments:
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* generic : either a name or a list index for a particular generic
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* with_default : True to add the default value
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Returns:
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* A string when generic argument is used
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* A list of strings with all generics
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"""
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if generic is None:
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# all generics
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l = []
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for i in range(len(self.generics)):
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l.append(self.generate_generic_declaration(i, with_default))
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return l
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else:
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# search for correct index
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if isinstance(generic, int):
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g = self.generics[generic]
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elif isinstance(generic, string):
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g = filter(lambda s: s["name"] == generic, self.generics)[0]
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else:
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raise TypeError("Don't know how to search with '%s'." % repr(generic))
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sret = "%s : %s" % (self.to_valid_str(g["name"]), g["type"])
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if with_default:
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sret += ' := %s' % convert_value(g["default_value"], g["type"], g["type_array"])
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# add string quotes
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# if g["type"] == "string":
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# sret += ' := "%s"' % g["default_value"]
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# else:
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# sret += ' := %s' % g["default_value"]
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return sret
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def generate_port_declaration(self, port=None, with_default=False):
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"""
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Generate a port declaration for this object.
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Arguments:
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* port : either a name or a list index for a particular port
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* with_default : True to add the default value
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Returns:
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* A list of strings with all signals in port when port argument is used
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* A list of strings with all signals in all ports
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"""
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if port is None:
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# all ports
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l = []
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for i in range(len(self.ports)):
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l.append(self.make_comment("Port '%s' : '%s'" % (self.to_valid_str(self.ports[i]["name"]), self.ports[i]["type"])))
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pl = self.generate_port_declaration(i, with_default)
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pl.sort()
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l.extend(pl)
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return l
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else:
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# search for correct index
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if isinstance(port, int):
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idx = port
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elif isinstance(port, string):
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p = filter(lambda s: s["name"] == port, self.ports)[0]
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idx = self.ports.index(p)
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else:
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raise TypeError("Don't know how to search with '%s'." % repr(port))
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return self.generate_signal_declaration(idx, None, with_default)
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def generate_signal_declaration(self, inport=None, signal=None, with_default=False):
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"""
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Generate a signal declaration for this object.
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Arguments:
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* inport : either a name or a list index for a particular port. None
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means use the external_signals list
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* signal : either a name or a list index for a particular signal
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* with_default : True to add the default value
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Returns:
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* A string when signal argument is used
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* A list of strings with all signals
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"""
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if signal is None:
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# all signals
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l = []
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if inport is None:
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r = range(len(self.external_signals))
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else:
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# what port?
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if isinstance(inport, int):
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g = self.ports[inport]
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elif isinstance(inport, string):
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g = filter(lambda s: s["name"] == inport, self.ports)[0]
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else:
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raise TypeError("Don't know how to search with '%s'." % repr(inport))
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r = range(len(g["signal_list"]))
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for i in r:
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l.append(self.generate_signal_declaration(inport, i, with_default))
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return l
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else:
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# locate either port or external_signals
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if inport is None:
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if isinstance(signal, int):
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sig = self.external_signals[signal]
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elif isinstance(signal, string):
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sig = filter(lambda s: s["name"] == signal, self.external_signals)[0]
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else:
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raise TypeError("Don't know how to search with '%s'." % repr(signal))
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# put nothing as signal prefix
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sprefix = ""
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else:
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# what port?
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if isinstance(inport, int):
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p = self.ports[inport]
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elif isinstance(inport, string):
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p = filter(lambda s: s["name"] == inport, self.ports)[0]
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else:
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raise TypeError("Don't know how to search with '%s'." % repr(inport))
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# what signal?
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if isinstance(signal, int):
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sig = p["signal_list"][signal]
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elif isinstance(signal, string):
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sig = filter(lambda s: s["name"] == signal, p["signal_list"])[0]
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else:
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raise TypeError("Don't know how to search with '%s'." % repr(signal))
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# put port name as signal prefix
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#sprefix = self.to_valid_str(p["name"]) + "_"
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sprefix = ""
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sret = "%s%s : %s %s" % (sprefix, self.to_valid_str(sig["name"]), sig["direction"], sig["type"])
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if with_default:
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sret += ' := %s' % convert_value(sig["default_value"], sig["type"])
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# if sig["type"] == "string":
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# sret += ' := "%s"' % sig["default_value"]
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# else:
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# sret += ' := %s' % sig["default_value"]
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return sret
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def make_comment(self, data):
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"""
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Convert string data to language comment
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Argument:
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* data: string or list of strings to convert
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Returns: a new string or list of strings with comments added.
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"""
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if isinstance(data, str):
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return "-- %s%s" % (data[:-1].replace("\n", "\n-- "), data[-1])
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else:
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# don't put exception catch. It is an error if data is not
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# iterable.
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it = iter(data)
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retval = []
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for s in data:
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retval.append("-- %s%s" % (s[:-1].replace("\n", "\n-- "), s[-1]))
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return retval
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def add_tab(self, data, level=1):
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"""
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Add an indentation level to the string
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Argument:
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* data: string or list of strings
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* level: how many indentation levels to add. Default 1
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Returns: string or list of strings with <level> indentation levels.
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"""
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leveltabs = self.usetab*level
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if isinstance(data, str):
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return "%s%s%s" % (leveltabs, data[:-1].replace("\n", "\n%s" % leveltabs), data[-1])
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else:
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# don't put exception catch. It is an error if data is not
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# iterable.
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it = iter(data)
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retval = []
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for s in data:
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retval.append("%s%s%s" % (leveltabs, s[:-1].replace("\n", "\n%s" % leveltabs), s[-1]))
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return retval
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def to_valid_str(self, str_in):
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"""
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Convert an input string, changing special characters used on
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the HDL language. Useful for set names .
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Argument:
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* str_in: string to convert
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Returns: the converted string.
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"""
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# list of transformations:
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# * strip spaces
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# * space,":" with "_"
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s = str_in.strip()
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s = s.replace(" ", "_")
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s = s.replace(":", "_")
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return s
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# codegen model management
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def add_generic(self, name, value, description="", **kwargs):
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"""
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Add a generic to the model - with VHDL type formatting.
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"""
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g = noc_codegen_base.add_generic(self, name, value, description, **kwargs)
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# Set correct type. String by default
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gadd = {"type": "string"}
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if "type" in kwargs:
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# Optional type must be a string with a custom type name.
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if isinstance(kwargs["type"], str):
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# custom type name.
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gadd.update({"type": kwargs["type"]})
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#else:
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# default to use string
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else:
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gadd["type"] = self.calculate_type(value)
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## use type in value
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#gadd["type"] = _pytovhdltype[type(value)]
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## defined range
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#if "type_array" in kwargs:
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#if isinstance(value, int):
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## for an integer it means range
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#gadd["type"] += " range %d to %d" % (kwargs["type_array"][0], kwargs["type_array"][1])
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#elif isinstance(value, intbv):
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## for a intbv it means bit boundaries
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#gadd["type"] += "_vector(%d to %d)" % (kwargs["type_array"][0], kwargs["type_array"][1])
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##else:
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## ignore array range
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|
#else:
|
| 339 |
|
|
## special case
|
| 340 |
|
|
#if isinstance(value, intbv):
|
| 341 |
|
|
## put vector only if necessary
|
| 342 |
|
|
#if value._nrbits > 1:
|
| 343 |
|
|
## extract vector information
|
| 344 |
|
|
#gadd["type_array"] = [0, value._nrbits - 1]
|
| 345 |
|
|
#gadd["type"] += "_vector(%d to %d)" % (0, value._nrbits - 1)
|
| 346 |
|
|
|
| 347 |
|
|
g.update(gadd)
|
| 348 |
|
|
return g
|
| 349 |
|
|
|
| 350 |
|
|
def add_port(self, name, signal_desc=None, description="", **kwargs):
|
| 351 |
|
|
"""
|
| 352 |
|
|
Add a port to the model - with VHDL type formatting.
|
| 353 |
|
|
"""
|
| 354 |
|
|
p = noc_codegen_base.add_port(self, name, signal_desc, description, **kwargs)
|
| 355 |
|
|
if signal_desc is None:
|
| 356 |
|
|
# nothing else to do
|
| 357 |
|
|
return p
|
| 358 |
|
|
# set correct type for the particular signal_desc
|
| 359 |
|
|
sig = filter(lambda x: x["name"] == signal_desc["name"], p["signal_list"])
|
| 360 |
|
|
if len(sig) == 0:
|
| 361 |
|
|
# strange error
|
| 362 |
|
|
raise ValueError("Strange error: recently added signal '%s' to port '%s', but signal cannot be found." % (signal_desc["name"], p["name"]))
|
| 363 |
|
|
else:
|
| 364 |
|
|
sig = sig[0]
|
| 365 |
|
|
# type inferring: only apply if signal_desc has empty type
|
| 366 |
|
|
if sig["type"] != "":
|
| 367 |
|
|
return p
|
| 368 |
|
|
|
| 369 |
|
|
# integer by default
|
| 370 |
|
|
sadd = {"type": "integer"}
|
| 371 |
|
|
if "type" in kwargs:
|
| 372 |
|
|
# Optional type must be a string with a custom type name.
|
| 373 |
|
|
if isinstance(kwargs["type"], str):
|
| 374 |
|
|
# custom type name.
|
| 375 |
|
|
sadd["type"] = kwargs["type"]
|
| 376 |
|
|
# also add if it has default_value
|
| 377 |
|
|
if "default_value" in kwargs:
|
| 378 |
|
|
sadd["default_value"] = kwargs["default_value"]
|
| 379 |
|
|
#else:
|
| 380 |
|
|
# default to use integer
|
| 381 |
|
|
else:
|
| 382 |
|
|
sadd["type"] = self.calculate_type(sig["default_value"])
|
| 383 |
|
|
## use type in value
|
| 384 |
|
|
#sadd["type"] = _pytovhdltype[type(sig["default_value"])]
|
| 385 |
|
|
## defined range
|
| 386 |
|
|
#if "type_array" in kwargs:
|
| 387 |
|
|
#if isinstance(sig["default_value"], int):
|
| 388 |
|
|
#sadd["type"] += " range(%d to %d)" % (kwargs["type_array"][0], kwargs["type_array"][1])
|
| 389 |
|
|
#elif isinstance(sig["default_value"], intbv):
|
| 390 |
|
|
#sadd["type"] += "_vector(%d downto %d)" % (kwargs["type_array"][1], kwargs["type_array"][0])
|
| 391 |
|
|
##else:
|
| 392 |
|
|
## ignore array range
|
| 393 |
|
|
#else:
|
| 394 |
|
|
## special case
|
| 395 |
|
|
#if isinstance(sig["default_value"], intbv):
|
| 396 |
|
|
## put vector only if necessary
|
| 397 |
|
|
#if sig["default_value"]._nrbits > 1:
|
| 398 |
|
|
## extract vector information
|
| 399 |
|
|
#sadd["type_array"] = [0, sig["default_value"]._nrbits - 1]
|
| 400 |
|
|
#sadd["type"] += "_vector(%d downto 0)" % (sig["default_value"]._nrbits - 1)
|
| 401 |
|
|
sig.update(sadd)
|
| 402 |
|
|
return p
|
| 403 |
|
|
|
| 404 |
|
|
def add_external_signal(self, name, direction, value, description="", **kwargs):
|
| 405 |
|
|
"""
|
| 406 |
|
|
Add a external signal to the model - with VHDL type formatting.
|
| 407 |
|
|
"""
|
| 408 |
|
|
sig = noc_codegen_base.add_external_signal(self, name, direction, value, description, **kwargs)
|
| 409 |
|
|
# Set correct type. integer by default
|
| 410 |
|
|
sadd = {"type": "integer"}
|
| 411 |
|
|
if "type" in kwargs:
|
| 412 |
|
|
# Optional type must be a string with a custom type name.
|
| 413 |
|
|
if isinstance(kwargs["type"], str):
|
| 414 |
|
|
# custom type name.
|
| 415 |
|
|
sadd.update({"type": kwargs["type"]})
|
| 416 |
|
|
#else:
|
| 417 |
|
|
# default to use integer
|
| 418 |
|
|
else:
|
| 419 |
|
|
sadd["type"] = self.calculate_type(value)
|
| 420 |
|
|
## use type in value
|
| 421 |
|
|
#sadd["type"] = _pytovhdltype[type(value)]
|
| 422 |
|
|
## defined range
|
| 423 |
|
|
#if "type_array" in kwargs:
|
| 424 |
|
|
#if isinstance(value, int):
|
| 425 |
|
|
#sadd["type"] += " range(%d to %d)" % (kwargs["type_array"][0], kwargs["type_array"][1])
|
| 426 |
|
|
#elif isinstance(value, intbv):
|
| 427 |
|
|
#sadd["type"] += "_vector(%d to %d)" % (kwargs["type_array"][0], kwargs["type_array"][1])
|
| 428 |
|
|
##else:
|
| 429 |
|
|
## ignore array range
|
| 430 |
|
|
#else:
|
| 431 |
|
|
## special case
|
| 432 |
|
|
#if isinstance(value, intbv):
|
| 433 |
|
|
## extract vector information
|
| 434 |
|
|
#sadd["type_array"] = [0, sig["default_value"]._nrbits - 1]
|
| 435 |
|
|
#if None not in sadd["type_array"]:
|
| 436 |
|
|
#sadd["type"] += "_vector(%d to %d)" % (0, sig["default_value"]._nrbits - 1)
|
| 437 |
|
|
sig.update(sadd)
|
| 438 |
|
|
return sig
|
| 439 |
|
|
|
| 440 |
|
|
# particular VHDL methods
|
| 441 |
|
|
def generate_entity_section(self):
|
| 442 |
|
|
"""
|
| 443 |
|
|
Generate entity section
|
| 444 |
|
|
"""
|
| 445 |
|
|
sret = "entity %s is\n" % self.modulename
|
| 446 |
|
|
stmp = self.generate_generics_section()
|
| 447 |
|
|
if stmp != "":
|
| 448 |
|
|
sret += self.add_tab(stmp) + ";\n"
|
| 449 |
|
|
stmp = self.generate_ports_section()
|
| 450 |
|
|
if stmp != "":
|
| 451 |
|
|
sret += self.add_tab(stmp) + ";\n"
|
| 452 |
|
|
sret += "end %s;\n" % self.modulename
|
| 453 |
|
|
return sret
|
| 454 |
|
|
|
| 455 |
|
|
def generate_architecture_section(self, archname="rtl"):
|
| 456 |
|
|
"""
|
| 457 |
|
|
Generate architecture section
|
| 458 |
|
|
"""
|
| 459 |
|
|
sret = "architecture %s of %s is\n" % (archname, self.modulename)
|
| 460 |
|
|
if self.implementation != "":
|
| 461 |
|
|
sret += self.add_tab(self.implementation)
|
| 462 |
|
|
sret += "\nend %s;\n" % archname
|
| 463 |
|
|
return sret
|
| 464 |
|
|
|
| 465 |
|
|
def generate_generics_section(self):
|
| 466 |
|
|
"""
|
| 467 |
|
|
Generate generics section used on entity and component
|
| 468 |
|
|
"""
|
| 469 |
|
|
sret = "generic (\n"
|
| 470 |
|
|
l = self.generate_generic_declaration(None, True)
|
| 471 |
|
|
if len(l) > 0:
|
| 472 |
|
|
l = self.add_tab(l)
|
| 473 |
|
|
sret += ";\n".join(l)
|
| 474 |
|
|
sret += "\n)"
|
| 475 |
|
|
else:
|
| 476 |
|
|
# empty generics section
|
| 477 |
|
|
sret = ""
|
| 478 |
|
|
return sret
|
| 479 |
|
|
|
| 480 |
|
|
def generate_ports_section(self):
|
| 481 |
|
|
"""
|
| 482 |
|
|
Generate ports section used on entity and component
|
| 483 |
|
|
"""
|
| 484 |
|
|
# first ports and then external signals
|
| 485 |
|
|
sret = "port (\n"
|
| 486 |
|
|
l = self.generate_port_declaration(None, False)
|
| 487 |
|
|
l.extend(self.generate_signal_declaration(None, None, False))
|
| 488 |
|
|
if len(l) > 0:
|
| 489 |
|
|
l = self.add_tab(l)
|
| 490 |
|
|
sret += ";\n".join(l)
|
| 491 |
|
|
sret += "\n)"
|
| 492 |
|
|
else:
|
| 493 |
|
|
# empty ports section
|
| 494 |
|
|
sret = ""
|
| 495 |
|
|
return sret
|
| 496 |
|
|
|
| 497 |
|
|
def calculate_type(self, object, with_default=False):
|
| 498 |
|
|
"""
|
| 499 |
|
|
Calculate the correct VHDL type for a particular object
|
| 500 |
|
|
|
| 501 |
|
|
Arguments:
|
| 502 |
|
|
* object:
|
| 503 |
|
|
* with_default: True to add a default value at the end
|
| 504 |
|
|
Returns:
|
| 505 |
|
|
A string with the VHDL equivalent type
|
| 506 |
|
|
"""
|
| 507 |
|
|
if isinstance(object, bool):
|
| 508 |
|
|
return "std_logic"
|
| 509 |
|
|
elif isinstance(object, (int, long)):
|
| 510 |
|
|
# CHECK if this is a correct type translation
|
| 511 |
|
|
return "integer"
|
| 512 |
|
|
elif isinstance(object, str):
|
| 513 |
|
|
return "string"
|
| 514 |
|
|
elif isinstance(object, myhdl.intbv):
|
| 515 |
|
|
width = object._nrbits
|
| 516 |
|
|
initval = object._val
|
| 517 |
|
|
elif isinstance(object, myhdl.SignalType):
|
| 518 |
|
|
width = object._nrbits
|
| 519 |
|
|
initval = object._init
|
| 520 |
|
|
else:
|
| 521 |
|
|
raise ValueError("Type conversion for object %s not found (type: %s)" % (repr(object), type(object)))
|
| 522 |
|
|
if width <= 0:
|
| 523 |
|
|
raise ValueError("Object %s don't have a valid bit width." % repr(object))
|
| 524 |
|
|
if width == 1:
|
| 525 |
|
|
retval = "std_logic"
|
| 526 |
|
|
defval = "'%d'" % int(initval)
|
| 527 |
|
|
else:
|
| 528 |
|
|
retval = "unsigned(%s downto 0)" % (width - 1)
|
| 529 |
|
|
defval = '"%s"' % myhdl.bin(initval, width)
|
| 530 |
|
|
if with_default:
|
| 531 |
|
|
return "%s := %s" % (retval, defval)
|
| 532 |
|
|
else:
|
| 533 |
|
|
return retval
|
| 534 |
|
|
|
| 535 |
|
|
# helper functions
|
| 536 |
|
|
def add_codegen_vhdl_support(instance, **kwargs):
|
| 537 |
|
|
"""
|
| 538 |
|
|
This function will add for every object in instance a noc_codegen object
|
| 539 |
|
|
"""
|
| 540 |
|
|
if isinstance(instance, noc):
|
| 541 |
|
|
# add code generation object
|
| 542 |
|
|
instance.codegen = noc_codegen_vhdl(instance, **kwargs)
|
| 543 |
|
|
# and add cg objects recursively
|
| 544 |
|
|
for obj in instance.all_list(True):
|
| 545 |
|
|
add_codegen_vhdl_support(obj, **kwargs)
|
| 546 |
|
|
elif isinstance(instance, (ipcore, router, channel)):
|
| 547 |
|
|
instance.codegen = noc_codegen_vhdl(instance, **kwargs)
|
| 548 |
|
|
else:
|
| 549 |
|
|
raise TypeError("Unsupported object: type %s" % type(instance))
|
| 550 |
|
|
|
| 551 |
|
|
def convert_value(data, custom_type=None, type_array=[None, None]):
|
| 552 |
|
|
"""
|
| 553 |
|
|
This function converts data to a string valid in VHDL syntax.
|
| 554 |
|
|
"""
|
| 555 |
|
|
retval = ""
|
| 556 |
|
|
numbits = 0
|
| 557 |
|
|
usedata = data
|
| 558 |
|
|
if custom_type is not None:
|
| 559 |
|
|
# custom type
|
| 560 |
|
|
if custom_type == int:
|
| 561 |
|
|
usedata = int(data)
|
| 562 |
|
|
elif custom_type == bool:
|
| 563 |
|
|
usedata = data == True
|
| 564 |
|
|
elif custom_type == intbv:
|
| 565 |
|
|
# need fixed boundaries. Use type_array
|
| 566 |
|
|
if type_array == [None, None]:
|
| 567 |
|
|
# default: one bit width
|
| 568 |
|
|
usedata = intbv(data)[1:]
|
| 569 |
|
|
else:
|
| 570 |
|
|
# intbv boundaries refer to bit width
|
| 571 |
|
|
usedata = intbv(data)[type_array[1]+1:type_array[0]]
|
| 572 |
|
|
elif custom_type == str:
|
| 573 |
|
|
usedata = str(data)
|
| 574 |
|
|
elif isinstance(custom_type, str):
|
| 575 |
|
|
# type in a string format
|
| 576 |
|
|
if custom_type == "integer":
|
| 577 |
|
|
usedata = int(data)
|
| 578 |
|
|
elif custom_type == "std_logic":
|
| 579 |
|
|
usedata = intbv(data)[1:]
|
| 580 |
|
|
elif custom_type == "string":
|
| 581 |
|
|
usedata = str(data)
|
| 582 |
|
|
elif custom_type.find("std_logic_vector") == 0:
|
| 583 |
|
|
# strip values
|
| 584 |
|
|
vecinfo = custom_type.replace("std_logic_vector", "").strip("()").split()
|
| 585 |
|
|
if vecinfo[1] == "to":
|
| 586 |
|
|
vecmin = int(vecinfo[0])
|
| 587 |
|
|
vecmax = int(vecinfo[2])
|
| 588 |
|
|
elif vecinfo[1] == "downto":
|
| 589 |
|
|
vecmin = int(vecinfo[2])
|
| 590 |
|
|
vecmax = int(vecinfo[0])
|
| 591 |
|
|
usedata = intbv(data)[vecmax+1:vecmin]
|
| 592 |
|
|
else:
|
| 593 |
|
|
raise TypeError("Unsupported custom type string '%s' for VHDL conversion." % custom_type)
|
| 594 |
|
|
else:
|
| 595 |
|
|
raise TypeError("Unsupported custom type '%s' for VHDL conversion." % type(custom_type))
|
| 596 |
|
|
# convert
|
| 597 |
|
|
if isinstance(usedata, int):
|
| 598 |
|
|
retval = "%d" % data
|
| 599 |
|
|
elif isinstance(usedata, bool):
|
| 600 |
|
|
retval = "'%d'" % int(data)
|
| 601 |
|
|
elif isinstance(usedata, intbv):
|
| 602 |
|
|
# check boundaries
|
| 603 |
|
|
if usedata._nrbits > 1:
|
| 604 |
|
|
# print vector in bits
|
| 605 |
|
|
retval = '"%s"' % bin(usedata, usedata._nrbits)
|
| 606 |
|
|
else:
|
| 607 |
|
|
retval = "'%d'" % usedata
|
| 608 |
|
|
elif isinstance(usedata, str):
|
| 609 |
|
|
retval = '"%s"' % usedata
|
| 610 |
|
|
else:
|
| 611 |
|
|
raise TypeError("Unsupported type '%s' for VHDL conversion." % type(usedata))
|
| 612 |
|
|
return retval
|
| 613 |
|
|
|
| 614 |
|
|
# helper structures:
|
| 615 |
|
|
# type conversions
|
| 616 |
|
|
_pytovhdltype = {
|
| 617 |
|
|
"bool": "std_logic",
|
| 618 |
|
|
"int": "integer",
|
| 619 |
|
|
"intbv" : "unsigned",
|
| 620 |
|
|
"str" : "string",
|
| 621 |
|
|
bool: "std_logic",
|
| 622 |
|
|
int: "integer",
|
| 623 |
|
|
intbv : "unsigned",
|
| 624 |
|
|
str : "string"
|
| 625 |
|
|
}
|
| 626 |
|
|
_pytovhdlzeroval = {
|
| 627 |
|
|
"bool": "False",
|
| 628 |
|
|
"int": "0",
|
| 629 |
|
|
"intbv" : '"0"',
|
| 630 |
|
|
"str" : '""',
|
| 631 |
|
|
bool: "False",
|
| 632 |
|
|
int: "0",
|
| 633 |
|
|
intbv : '"0"',
|
| 634 |
|
|
str : '""'
|
| 635 |
|
|
}
|
| 636 |
|
|
|
