OpenCores
URL https://opencores.org/ocsvn/noekeoncore/noekeoncore/trunk

Subversion Repositories noekeoncore

[/] [noekeoncore/] [trunk/] [rtl/] [noekeon.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 entactogen 
 
2 
-- Copyright (c) 2013 Antonio de la Piedra
3 
 
4 
-- This program is free software: you can redistribute it and/or modify
5 
-- it under the terms of the GNU General Public License as published by
6 
-- the Free Software Foundation, either version 3 of the License, or
7 
-- (at your option) any later version.
8 
 
9 
-- This program is distributed in the hope that it will be useful,
10 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 
-- GNU General Public License for more details.
13 
 
14 
-- You should have received a copy of the GNU General Public License
15 
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
16 
 
17 
library IEEE;
18 
use IEEE.STD_LOGIC_1164.ALL;
19 
 
20 
entity noekeon is
21 
        port(clk     : in std_logic;
22 
                  rst     : in std_logic;
23 
                  enc     : in std_logic; -- (enc, 0) / (dec, 1)
24 
                  a_0_in  : in std_logic_vector(31 downto 0);
25 
                  a_1_in  : in std_logic_vector(31 downto 0);
26 
                  a_2_in  : in std_logic_vector(31 downto 0);
27 
                  a_3_in  : in std_logic_vector(31 downto 0);
28 
                  k_0_in  : in std_logic_vector(31 downto 0);
29 
                  k_1_in  : in std_logic_vector(31 downto 0);
30 
                  k_2_in  : in std_logic_vector(31 downto 0);
31 
                  k_3_in  : in std_logic_vector(31 downto 0);
32 
                  a_0_out : out std_logic_vector(31 downto 0);
33 
                  a_1_out : out std_logic_vector(31 downto 0);
34 
                  a_2_out : out std_logic_vector(31 downto 0);
35 
                  a_3_out : out std_logic_vector(31 downto 0));
36 
end noekeon;
37 
 
38 
architecture Behavioral of noekeon is
39 
 
40 
        component round_f is
41 
        port(clk     : in std_logic;
42 
             enc : in std_logic;
43 
                  rc_in   : in std_logic_vector(31 downto 0);
44 
                  a_0_in  : in std_logic_vector(31 downto 0);
45 
                  a_1_in  : in std_logic_vector(31 downto 0);
46 
                  a_2_in  : in std_logic_vector(31 downto 0);
47 
                  a_3_in  : in std_logic_vector(31 downto 0);
48 
                  k_0_in  : in std_logic_vector(31 downto 0);
49 
                  k_1_in  : in std_logic_vector(31 downto 0);
50 
                  k_2_in  : in std_logic_vector(31 downto 0);
51 
                  k_3_in  : in std_logic_vector(31 downto 0);
52 
                  a_0_out : out std_logic_vector(31 downto 0);
53 
                  a_1_out : out std_logic_vector(31 downto 0);
54 
                  a_2_out : out std_logic_vector(31 downto 0);
55 
                  a_3_out : out std_logic_vector(31 downto 0));
56 
        end component;
57 
 
58 
        component rc_gen is
59 
        port(clk : in std_logic;
60 
             rst : in std_logic;
61 
                  enc : in std_logic; -- (enc, 0) / (dec, 1)
62 
                  rc_out : out std_logic_vector(7 downto 0));
63 
        end component;
64 
 
65 
        component output_trans is
66 
        port(clk     : in std_logic;
67 
                  enc            : in std_logic; -- (enc, 0) / (dec, 1)
68 
                  rc_in   : in std_logic_vector(31 downto 0);
69 
                  a_0_in  : in std_logic_vector(31 downto 0);
70 
                  a_1_in  : in std_logic_vector(31 downto 0);
71 
                  a_2_in  : in std_logic_vector(31 downto 0);
72 
                  a_3_in  : in std_logic_vector(31 downto 0);
73 
                  k_0_in  : in std_logic_vector(31 downto 0);
74 
                  k_1_in  : in std_logic_vector(31 downto 0);
75 
                  k_2_in  : in std_logic_vector(31 downto 0);
76 
                  k_3_in  : in std_logic_vector(31 downto 0);
77 
                  a_0_out : out std_logic_vector(31 downto 0);
78 
                  a_1_out : out std_logic_vector(31 downto 0);
79 
                  a_2_out : out std_logic_vector(31 downto 0);
80 
                  a_3_out : out std_logic_vector(31 downto 0));
81 
        end component;
82 
 
83 
        component theta is
84 
        port(clk : in std_logic;
85 
 
86 
             a_0_in : in std_logic_vector(31 downto 0);
87 
             a_1_in : in std_logic_vector(31 downto 0);
88 
             a_2_in : in std_logic_vector(31 downto 0);
89 
             a_3_in : in std_logic_vector(31 downto 0);
90 
 
91 
             k_0_in : in std_logic_vector(31 downto 0);
92 
             k_1_in : in std_logic_vector(31 downto 0);
93 
             k_2_in : in std_logic_vector(31 downto 0);
94 
             k_3_in : in std_logic_vector(31 downto 0);
95 
 
96 
             a_0_out : out std_logic_vector(31 downto 0);
97 
             a_1_out : out std_logic_vector(31 downto 0);
98 
             a_2_out : out std_logic_vector(31 downto 0);
99 
             a_3_out : out std_logic_vector(31 downto 0));
100 
        end component;
101 
 
102 
        signal rc_s : std_logic_vector(7 downto 0);
103 
        signal rc_ext_s : std_logic_vector(31 downto 0);
104 
 
105 
        signal a_0_in_s  : std_logic_vector(31 downto 0);
106 
        signal a_1_in_s  : std_logic_vector(31 downto 0);
107 
        signal a_2_in_s  : std_logic_vector(31 downto 0);
108 
        signal a_3_in_s  : std_logic_vector(31 downto 0);
109 
 
110 
        signal out_t_a_0_in_s  : std_logic_vector(31 downto 0);
111 
        signal out_t_a_1_in_s  : std_logic_vector(31 downto 0);
112 
        signal out_t_a_2_in_s  : std_logic_vector(31 downto 0);
113 
        signal out_t_a_3_in_s  : std_logic_vector(31 downto 0);
114 
 
115 
        signal a_0_out_s : std_logic_vector(31 downto 0);
116 
        signal a_1_out_s : std_logic_vector(31 downto 0);
117 
        signal a_2_out_s : std_logic_vector(31 downto 0);
118 
        signal a_3_out_s : std_logic_vector(31 downto 0);
119 
 
120 
        signal k_0_d_s  : std_logic_vector(31 downto 0);
121 
        signal k_1_d_s  : std_logic_vector(31 downto 0);
122 
        signal k_2_d_s  : std_logic_vector(31 downto 0);
123 
        signal k_3_d_s  : std_logic_vector(31 downto 0);
124 
 
125 
        signal k_0_mux_s  : std_logic_vector(31 downto 0);
126 
        signal k_1_mux_s  : std_logic_vector(31 downto 0);
127 
        signal k_2_mux_s  : std_logic_vector(31 downto 0);
128 
        signal k_3_mux_s  : std_logic_vector(31 downto 0);
129 
 
130 
begin
131 
 
132 
        RC_GEN_0 : rc_gen port map (clk, rst, enc, rc_s);
133 
 
134 
        rc_ext_s <= X"000000" & rc_s;
135 
 
136 
        ROUND_F_0 : round_f port map (clk,
137 
                                                                                   enc,
138 
                                                                                   rc_ext_s,
139 
                                                                                        a_0_in_s,
140 
                                                                                        a_1_in_s,
141 
                                                                                   a_2_in_s,
142 
                                                                                        a_3_in_s,
143 
                                                                                        k_0_mux_s,
144 
                                                                                        k_1_mux_s,
145 
                                                                                        k_2_mux_s,
146 
                                                                                        k_3_mux_s,
147 
                                                                                        a_0_out_s,
148 
                                                                                        a_1_out_s,
149 
                                                                                        a_2_out_s,
150 
                                                                                        a_3_out_s);
151 
 
152 
        pr_noe: process(clk, rst, enc)
153 
        begin
154 
                if rising_edge(clk) then
155 
                        if rst = '1' then
156 
                                a_0_in_s <= a_0_in;
157 
                                a_1_in_s <= a_1_in;
158 
                                a_2_in_s <= a_2_in;
159 
                                a_3_in_s <= a_3_in;
160 
                        else
161 
                                a_0_in_s <= a_0_out_s;
162 
                                a_1_in_s <= a_1_out_s;
163 
                                a_2_in_s <= a_2_out_s;
164 
                                a_3_in_s <= a_3_out_s;
165 
                        end if;
166 
                end if;
167 
        end process;
168 
 
169 
--      a_0_out <= a_0_out_s;
170 
--      a_1_out <= a_1_out_s;
171 
--      a_2_out <= a_2_out_s;
172 
--      a_3_out <= a_3_out_s;
173 
 
174 
        out_trans_pr: process(clk, rst, a_0_out_s, a_1_out_s, a_2_out_s, a_3_out_s)
175 
        begin
176 
                if rising_edge(clk) then
177 
                        out_t_a_0_in_s <= a_0_out_s;
178 
                        out_t_a_1_in_s <= a_1_out_s;
179 
                        out_t_a_2_in_s <= a_2_out_s;
180 
                        out_t_a_3_in_s <= a_3_out_s;
181 
                end if;
182 
        end process;
183 
 
184 
        OUT_TRANS_0 : output_trans port map (clk, enc, rc_ext_s,
185 
                        out_t_a_0_in_s,
186 
                        out_t_a_1_in_s,
187 
                        out_t_a_2_in_s,
188 
                        out_t_a_3_in_s,
189 
                        k_0_mux_s,
190 
                        k_1_mux_s,
191 
                        k_2_mux_s,
192 
                        k_3_mux_s,
193 
                        a_0_out,
194 
                        a_1_out,
195 
                        a_2_out,
196 
                        a_3_out);
197 
 
198 
        -- key decrypt
199 
 
200 
        THETA_DECRYPT_0 : theta port map (clk,
201 
                        k_0_in,
202 
                        k_1_in,
203 
                        k_2_in,
204 
                        k_3_in,
205 
                        (others => '0'),
206 
                        (others => '0'),
207 
                        (others => '0'),
208 
                        (others => '0'),
209 
                        k_0_d_s,
210 
              k_1_d_s,
211 
              k_2_d_s,
212 
              k_3_d_s);
213 
 
214 
                        k_0_mux_s <= k_0_in when enc = '0' else k_0_d_s;
215 
                        k_1_mux_s <= k_1_in when enc = '0' else k_1_d_s;
216 
                        k_2_mux_s <= k_2_in when enc = '0' else k_2_d_s;
217 
                        k_3_mux_s <= k_3_in when enc = '0' else k_3_d_s;
218 
 
219 
end Behavioral;
220 
 

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.