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eexuke |
//
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// Copyright (C) 2004 Virtual Silicon Technology Inc.. All Rights Reserved.
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// Silicon Ready, The Heart of Great Silicon, and the Virtual Silicon logo are
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// registered trademarks of Virtual Silicon Technology Inc.
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// All other trademarks are the property of their respective owner.
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//
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// Virtual Silicon Technology Inc.
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// 1322 Orleans Drive
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// Sunnyvale, CA 94089-1135
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// Phone : 408-548-2700
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// Fax : 408-548-2750
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// Web Site : www.virtual-silicon.com
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//
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// VST Library Release: UMCL18G415T3_1.0
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// Product: High Density Single Port SRAM Compiler
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// Process: L180 Generic II
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//
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// High Density one-Port RAM 96 words by 32 bits
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// column mux = 4
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// bytewrite = n
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// test = n
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// powerbus = b
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// frequency = 10
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//
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`timescale 1 ns / 1 ps
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`celldefine
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module rec_DF_RAM0_96x32 (
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CK,
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CEN,
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WEN,
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OEN,
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ADR,
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DI,
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DOUT
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);
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// parameter and port declaration block
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parameter words = 96;
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parameter bits = 32;
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parameter addMsb = 6;
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parameter bytes= 4;
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parameter bitMsb = 31;
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input CK;
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input CEN;
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input WEN;
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input OEN;
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input [addMsb:0] ADR;
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input [bitMsb:0] DI;
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output [bitMsb:0] DOUT;
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// input buffer block
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buf (buf_CK, CK);
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buf (buf_CEN, CEN);
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buf (buf_WEN, WEN);
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buf (buf_OEN, OEN);
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wire [addMsb:0] buf_ADR;
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wire [bitMsb:0] buf_DI;
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assign buf_ADR = ADR;
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assign buf_DI = DI;
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// internal variable declarations
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reg int_CEN;
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reg int_WEN;
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reg [addMsb:0] int_ADR;
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reg [bitMsb:0] int_DI;
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reg [bitMsb:0] int_DOUT;
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reg [bitMsb:0] memory_array [95:0];
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reg old_CK;
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reg write_error;
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reg read_error;
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reg risingTmp;
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always @(posedge buf_CK)
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risingTmp = 1'b1;
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always @(negedge buf_CK)
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risingTmp = 1'b0;
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wire risingCK = risingTmp;
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wire rflag = risingCK & (buf_WEN!==1'b0);
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wire wflag = risingCK & (buf_WEN!==1'b1);
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// DOUT processing
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wire [bitMsb:0] out_DOUT;
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assign out_DOUT = int_DOUT;
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wire int_OEN = buf_OEN;
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bufif0(DOUT[0], out_DOUT[0], int_OEN);
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bufif0(DOUT[1], out_DOUT[1], int_OEN);
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bufif0(DOUT[2], out_DOUT[2], int_OEN);
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bufif0(DOUT[3], out_DOUT[3], int_OEN);
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bufif0(DOUT[4], out_DOUT[4], int_OEN);
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bufif0(DOUT[5], out_DOUT[5], int_OEN);
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bufif0(DOUT[6], out_DOUT[6], int_OEN);
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bufif0(DOUT[7], out_DOUT[7], int_OEN);
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bufif0(DOUT[8], out_DOUT[8], int_OEN);
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bufif0(DOUT[9], out_DOUT[9], int_OEN);
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bufif0(DOUT[10], out_DOUT[10], int_OEN);
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bufif0(DOUT[11], out_DOUT[11], int_OEN);
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bufif0(DOUT[12], out_DOUT[12], int_OEN);
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bufif0(DOUT[13], out_DOUT[13], int_OEN);
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bufif0(DOUT[14], out_DOUT[14], int_OEN);
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bufif0(DOUT[15], out_DOUT[15], int_OEN);
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bufif0(DOUT[16], out_DOUT[16], int_OEN);
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bufif0(DOUT[17], out_DOUT[17], int_OEN);
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bufif0(DOUT[18], out_DOUT[18], int_OEN);
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bufif0(DOUT[19], out_DOUT[19], int_OEN);
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bufif0(DOUT[20], out_DOUT[20], int_OEN);
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bufif0(DOUT[21], out_DOUT[21], int_OEN);
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bufif0(DOUT[22], out_DOUT[22], int_OEN);
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bufif0(DOUT[23], out_DOUT[23], int_OEN);
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bufif0(DOUT[24], out_DOUT[24], int_OEN);
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bufif0(DOUT[25], out_DOUT[25], int_OEN);
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bufif0(DOUT[26], out_DOUT[26], int_OEN);
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bufif0(DOUT[27], out_DOUT[27], int_OEN);
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bufif0(DOUT[28], out_DOUT[28], int_OEN);
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bufif0(DOUT[29], out_DOUT[29], int_OEN);
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bufif0(DOUT[30], out_DOUT[30], int_OEN);
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bufif0(DOUT[31], out_DOUT[31], int_OEN);
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and (chk_DI, ~buf_CEN, ~buf_WEN);
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reg mpwCK_notifier;
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reg pwhCK_notifier;
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reg shCEN_notifier;
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reg shADR_notifier;
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reg shWEN_notifier;
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reg shDI_notifier;
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integer i, j, h, k, m;
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parameter x_data = 32'bx;
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parameter data_0 = {32{1'b0}};
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parameter x_adr = 7'bx;
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parameter adr_0 = {7{1'b0}};
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initial begin
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for (i = 0; i < words; i=i+1)
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memory_array[i] = x_data;
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end
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initial begin
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read_error = 1'b0;
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write_error = 1'b0;
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old_CK = 1'b0;
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// Wait for valid initial transition
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wait (buf_CK === 1'b0);
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forever @(buf_CK) begin
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case ({old_CK,buf_CK})
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// 0->1 transition
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2'b01:
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begin
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int_CEN = buf_CEN;
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int_WEN = buf_WEN;
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int_ADR = buf_ADR;
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int_DI = buf_DI;
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if (int_CEN === 1'b0) begin
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// Read cycle
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if( ^int_ADR === 1'bx) begin
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ADR_error;
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end else if (int_WEN === 1'b1) begin
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int_DOUT = memory_array[int_ADR];
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// Write cycle
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end else if (int_WEN === 1'b0) begin
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if (write_error === 1'b0) begin
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memory_array[int_ADR] = int_DI; // Write cycle
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int_DOUT = int_DI;
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end
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// Unknown cycle
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end else begin // int_WEN = x
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SHWrite_error;
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end
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end else if (int_CEN === 1'bx) begin
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wipe_memory_output;
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end
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// 0->unknown transition, wait until returns to 0
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end
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2'b0x, 2'b1x, 2'bx1, 2'bx0: begin
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int_CEN = 1'bx;
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wipe_memory_output;
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end
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endcase
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old_CK <= #0.002 buf_CK;
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end
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end // end memory loop
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//====================
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// Task and procedure
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//====================
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// This task process entire MEM and OUTPUTs
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task wipe_memory_output;
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integer i;
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begin
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write_error = 1'b1;
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int_DOUT = x_data;
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int_ADR = x_adr;
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int_WEN = 1'bx;
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int_DI = x_data;
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for (i = 0; i < words; i=i+1) begin
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memory_array[i] = x_data;
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end
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write_error = 1'b0;
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end
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endtask
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// This task process write through violation
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task SHWrite_error;
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integer ic, ib;
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begin
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write_error = 1'b1;
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read_error = 1'b1;
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if (int_WEN===1'bx) begin
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memory_array[int_ADR] = x_data;
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int_DOUT = x_data;
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end else if (int_WEN===1'b0) begin
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memory_array[int_ADR] = int_DI;
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int_DOUT = int_DI;
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end
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write_error = 1'b0;
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read_error = 1'b0;
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end
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endtask
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// This task process read violation
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task SHRead_error;
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begin
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read_error = 1'b1;
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int_DOUT = x_data;
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//wait (buf_CK === 1'b0);
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read_error = 1'b0;
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end
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endtask
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// This task process ADR violation
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task ADR_error;
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integer i;
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begin
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write_error = 1'b1;
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read_error = 1'b1;
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int_DOUT = x_data;
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for (i = 0; i < words; i=i+1)
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memory_array[i] = x_data;
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write_error = 1'b0;
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read_error = 1'b0;
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end
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endtask
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//=======================
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// Violation processing
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//=======================
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// CK violation
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always @(pwhCK_notifier) begin
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$display ("%m CLK cycle pulse width high timing violation detected %t", $realtime);
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int_CEN = 1'bx;
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wipe_memory_output;
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end
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always @(mpwCK_notifier) begin
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$display ("%m CLK cycle timing violation detected %t", $realtime);
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#0.001;
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wipe_memory_output;
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risingTmp = 1'b0;
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end
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// CEN violation
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always @(shCEN_notifier) begin
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int_CEN = 1'bx;
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$display ("%m Cell enable timing violation detected %t", $realtime);
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wipe_memory_output;
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end
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// ADR violation
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always @(shADR_notifier) begin
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int_ADR = x_adr;
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$display ("%m Address timing violation detected %t", $realtime);
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ADR_error;
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end
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// WEN violation
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always @(shWEN_notifier) begin
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int_WEN = 1'bx;
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$display ("%m Write enable timing violation detected %t", $realtime);
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if( ^int_ADR !== 1'bx)
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SHWrite_error;
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end
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// DI violation
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always @(shDI_notifier) begin
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int_DI = x_data;
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$display ("%m Input data timing violation detected %t", $realtime);
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if( ^int_ADR !== 1'bx)
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SHWrite_error;
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end
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specify
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// Path delays
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if (rflag) (CK *> DOUT[0]) = 0.1;
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if (wflag) (CK *> DOUT[0]) = 0.1;
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if (rflag) (CK *> DOUT[1]) = 0.1;
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if (wflag) (CK *> DOUT[1]) = 0.1;
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if (rflag) (CK *> DOUT[2]) = 0.1;
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if (wflag) (CK *> DOUT[2]) = 0.1;
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if (rflag) (CK *> DOUT[3]) = 0.1;
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if (wflag) (CK *> DOUT[3]) = 0.1;
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if (rflag) (CK *> DOUT[4]) = 0.1;
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if (wflag) (CK *> DOUT[4]) = 0.1;
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if (rflag) (CK *> DOUT[5]) = 0.1;
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if (wflag) (CK *> DOUT[5]) = 0.1;
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if (rflag) (CK *> DOUT[6]) = 0.1;
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if (wflag) (CK *> DOUT[6]) = 0.1;
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if (rflag) (CK *> DOUT[7]) = 0.1;
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if (wflag) (CK *> DOUT[7]) = 0.1;
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if (rflag) (CK *> DOUT[8]) = 0.1;
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if (wflag) (CK *> DOUT[8]) = 0.1;
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if (rflag) (CK *> DOUT[9]) = 0.1;
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if (wflag) (CK *> DOUT[9]) = 0.1;
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if (rflag) (CK *> DOUT[10]) = 0.1;
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if (wflag) (CK *> DOUT[10]) = 0.1;
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if (rflag) (CK *> DOUT[11]) = 0.1;
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if (wflag) (CK *> DOUT[11]) = 0.1;
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if (rflag) (CK *> DOUT[12]) = 0.1;
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if (wflag) (CK *> DOUT[12]) = 0.1;
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if (rflag) (CK *> DOUT[13]) = 0.1;
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if (wflag) (CK *> DOUT[13]) = 0.1;
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if (rflag) (CK *> DOUT[14]) = 0.1;
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if (wflag) (CK *> DOUT[14]) = 0.1;
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if (rflag) (CK *> DOUT[15]) = 0.1;
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|
|
if (wflag) (CK *> DOUT[15]) = 0.1;
|
347 |
|
|
if (rflag) (CK *> DOUT[16]) = 0.1;
|
348 |
|
|
if (wflag) (CK *> DOUT[16]) = 0.1;
|
349 |
|
|
if (rflag) (CK *> DOUT[17]) = 0.1;
|
350 |
|
|
if (wflag) (CK *> DOUT[17]) = 0.1;
|
351 |
|
|
if (rflag) (CK *> DOUT[18]) = 0.1;
|
352 |
|
|
if (wflag) (CK *> DOUT[18]) = 0.1;
|
353 |
|
|
if (rflag) (CK *> DOUT[19]) = 0.1;
|
354 |
|
|
if (wflag) (CK *> DOUT[19]) = 0.1;
|
355 |
|
|
if (rflag) (CK *> DOUT[20]) = 0.1;
|
356 |
|
|
if (wflag) (CK *> DOUT[20]) = 0.1;
|
357 |
|
|
if (rflag) (CK *> DOUT[21]) = 0.1;
|
358 |
|
|
if (wflag) (CK *> DOUT[21]) = 0.1;
|
359 |
|
|
if (rflag) (CK *> DOUT[22]) = 0.1;
|
360 |
|
|
if (wflag) (CK *> DOUT[22]) = 0.1;
|
361 |
|
|
if (rflag) (CK *> DOUT[23]) = 0.1;
|
362 |
|
|
if (wflag) (CK *> DOUT[23]) = 0.1;
|
363 |
|
|
if (rflag) (CK *> DOUT[24]) = 0.1;
|
364 |
|
|
if (wflag) (CK *> DOUT[24]) = 0.1;
|
365 |
|
|
if (rflag) (CK *> DOUT[25]) = 0.1;
|
366 |
|
|
if (wflag) (CK *> DOUT[25]) = 0.1;
|
367 |
|
|
if (rflag) (CK *> DOUT[26]) = 0.1;
|
368 |
|
|
if (wflag) (CK *> DOUT[26]) = 0.1;
|
369 |
|
|
if (rflag) (CK *> DOUT[27]) = 0.1;
|
370 |
|
|
if (wflag) (CK *> DOUT[27]) = 0.1;
|
371 |
|
|
if (rflag) (CK *> DOUT[28]) = 0.1;
|
372 |
|
|
if (wflag) (CK *> DOUT[28]) = 0.1;
|
373 |
|
|
if (rflag) (CK *> DOUT[29]) = 0.1;
|
374 |
|
|
if (wflag) (CK *> DOUT[29]) = 0.1;
|
375 |
|
|
if (rflag) (CK *> DOUT[30]) = 0.1;
|
376 |
|
|
if (wflag) (CK *> DOUT[30]) = 0.1;
|
377 |
|
|
if (rflag) (CK *> DOUT[31]) = 0.1;
|
378 |
|
|
if (wflag) (CK *> DOUT[31]) = 0.1;
|
379 |
|
|
|
380 |
|
|
(OEN *> DOUT[0]) = 0.1;
|
381 |
|
|
(OEN *> DOUT[1]) = 0.1;
|
382 |
|
|
(OEN *> DOUT[2]) = 0.1;
|
383 |
|
|
(OEN *> DOUT[3]) = 0.1;
|
384 |
|
|
(OEN *> DOUT[4]) = 0.1;
|
385 |
|
|
(OEN *> DOUT[5]) = 0.1;
|
386 |
|
|
(OEN *> DOUT[6]) = 0.1;
|
387 |
|
|
(OEN *> DOUT[7]) = 0.1;
|
388 |
|
|
(OEN *> DOUT[8]) = 0.1;
|
389 |
|
|
(OEN *> DOUT[9]) = 0.1;
|
390 |
|
|
(OEN *> DOUT[10]) = 0.1;
|
391 |
|
|
(OEN *> DOUT[11]) = 0.1;
|
392 |
|
|
(OEN *> DOUT[12]) = 0.1;
|
393 |
|
|
(OEN *> DOUT[13]) = 0.1;
|
394 |
|
|
(OEN *> DOUT[14]) = 0.1;
|
395 |
|
|
(OEN *> DOUT[15]) = 0.1;
|
396 |
|
|
(OEN *> DOUT[16]) = 0.1;
|
397 |
|
|
(OEN *> DOUT[17]) = 0.1;
|
398 |
|
|
(OEN *> DOUT[18]) = 0.1;
|
399 |
|
|
(OEN *> DOUT[19]) = 0.1;
|
400 |
|
|
(OEN *> DOUT[20]) = 0.1;
|
401 |
|
|
(OEN *> DOUT[21]) = 0.1;
|
402 |
|
|
(OEN *> DOUT[22]) = 0.1;
|
403 |
|
|
(OEN *> DOUT[23]) = 0.1;
|
404 |
|
|
(OEN *> DOUT[24]) = 0.1;
|
405 |
|
|
(OEN *> DOUT[25]) = 0.1;
|
406 |
|
|
(OEN *> DOUT[26]) = 0.1;
|
407 |
|
|
(OEN *> DOUT[27]) = 0.1;
|
408 |
|
|
(OEN *> DOUT[28]) = 0.1;
|
409 |
|
|
(OEN *> DOUT[29]) = 0.1;
|
410 |
|
|
(OEN *> DOUT[30]) = 0.1;
|
411 |
|
|
(OEN *> DOUT[31]) = 0.1;
|
412 |
|
|
|
413 |
|
|
|
414 |
|
|
|
415 |
|
|
// Timing check parameters
|
416 |
|
|
specparam tsadrl = 0;
|
417 |
|
|
specparam thadrl = 0;
|
418 |
|
|
specparam tsadrh = 0;
|
419 |
|
|
specparam thadrh = 0;
|
420 |
|
|
specparam tsdil = 0;
|
421 |
|
|
specparam tsdih = 0;
|
422 |
|
|
specparam thdil = 0;
|
423 |
|
|
specparam thdih = 0;
|
424 |
|
|
specparam tscenl = 0;
|
425 |
|
|
specparam thcenl = 0;
|
426 |
|
|
specparam tscenh = 0;
|
427 |
|
|
specparam thcenh = 0;
|
428 |
|
|
specparam tswenl = 0;
|
429 |
|
|
specparam thwenl = 0;
|
430 |
|
|
specparam tswenh = 0;
|
431 |
|
|
specparam thwenh = 0;
|
432 |
|
|
specparam tcyc = 0;
|
433 |
|
|
specparam tlck = 0;
|
434 |
|
|
specparam thck = 0;
|
435 |
|
|
|
436 |
|
|
// Timing checks
|
437 |
|
|
$setuphold(posedge CK, negedge CEN, tscenl, thcenl, shCEN_notifier);
|
438 |
|
|
$setuphold(posedge CK, posedge CEN, tscenh, thcenh, shCEN_notifier);
|
439 |
|
|
|
440 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[0], tsadrl, thadrl, shADR_notifier);
|
441 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[0], tsadrh, thadrh, shADR_notifier);
|
442 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[1], tsadrl, thadrl, shADR_notifier);
|
443 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[1], tsadrh, thadrh, shADR_notifier);
|
444 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[2], tsadrl, thadrl, shADR_notifier);
|
445 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[2], tsadrh, thadrh, shADR_notifier);
|
446 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[3], tsadrl, thadrl, shADR_notifier);
|
447 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[3], tsadrh, thadrh, shADR_notifier);
|
448 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[4], tsadrl, thadrl, shADR_notifier);
|
449 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[4], tsadrh, thadrh, shADR_notifier);
|
450 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[5], tsadrl, thadrl, shADR_notifier);
|
451 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[5], tsadrh, thadrh, shADR_notifier);
|
452 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[6], tsadrl, thadrl, shADR_notifier);
|
453 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[6], tsadrh, thadrh, shADR_notifier);
|
454 |
|
|
|
455 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), negedge WEN, tswenl, thwenl, shWEN_notifier);
|
456 |
|
|
$setuphold(posedge CK &&& (CEN===1'b0), posedge WEN, tswenh, thwenh, shWEN_notifier);
|
457 |
|
|
|
458 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[0], tsdil, thdil, shDI_notifier);
|
459 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[0], tsdih, thdih, shDI_notifier);
|
460 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[1], tsdil, thdil, shDI_notifier);
|
461 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[1], tsdih, thdih, shDI_notifier);
|
462 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[2], tsdil, thdil, shDI_notifier);
|
463 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[2], tsdih, thdih, shDI_notifier);
|
464 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[3], tsdil, thdil, shDI_notifier);
|
465 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[3], tsdih, thdih, shDI_notifier);
|
466 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[4], tsdil, thdil, shDI_notifier);
|
467 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[4], tsdih, thdih, shDI_notifier);
|
468 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[5], tsdil, thdil, shDI_notifier);
|
469 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[5], tsdih, thdih, shDI_notifier);
|
470 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[6], tsdil, thdil, shDI_notifier);
|
471 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[6], tsdih, thdih, shDI_notifier);
|
472 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[7], tsdil, thdil, shDI_notifier);
|
473 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[7], tsdih, thdih, shDI_notifier);
|
474 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[8], tsdil, thdil, shDI_notifier);
|
475 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[8], tsdih, thdih, shDI_notifier);
|
476 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[9], tsdil, thdil, shDI_notifier);
|
477 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[9], tsdih, thdih, shDI_notifier);
|
478 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[10], tsdil, thdil, shDI_notifier);
|
479 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[10], tsdih, thdih, shDI_notifier);
|
480 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[11], tsdil, thdil, shDI_notifier);
|
481 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[11], tsdih, thdih, shDI_notifier);
|
482 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[12], tsdil, thdil, shDI_notifier);
|
483 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[12], tsdih, thdih, shDI_notifier);
|
484 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[13], tsdil, thdil, shDI_notifier);
|
485 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[13], tsdih, thdih, shDI_notifier);
|
486 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[14], tsdil, thdil, shDI_notifier);
|
487 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[14], tsdih, thdih, shDI_notifier);
|
488 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[15], tsdil, thdil, shDI_notifier);
|
489 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[15], tsdih, thdih, shDI_notifier);
|
490 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[16], tsdil, thdil, shDI_notifier);
|
491 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[16], tsdih, thdih, shDI_notifier);
|
492 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[17], tsdil, thdil, shDI_notifier);
|
493 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[17], tsdih, thdih, shDI_notifier);
|
494 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[18], tsdil, thdil, shDI_notifier);
|
495 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[18], tsdih, thdih, shDI_notifier);
|
496 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[19], tsdil, thdil, shDI_notifier);
|
497 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[19], tsdih, thdih, shDI_notifier);
|
498 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[20], tsdil, thdil, shDI_notifier);
|
499 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[20], tsdih, thdih, shDI_notifier);
|
500 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[21], tsdil, thdil, shDI_notifier);
|
501 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[21], tsdih, thdih, shDI_notifier);
|
502 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[22], tsdil, thdil, shDI_notifier);
|
503 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[22], tsdih, thdih, shDI_notifier);
|
504 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[23], tsdil, thdil, shDI_notifier);
|
505 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[23], tsdih, thdih, shDI_notifier);
|
506 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[24], tsdil, thdil, shDI_notifier);
|
507 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[24], tsdih, thdih, shDI_notifier);
|
508 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[25], tsdil, thdil, shDI_notifier);
|
509 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[25], tsdih, thdih, shDI_notifier);
|
510 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[26], tsdil, thdil, shDI_notifier);
|
511 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[26], tsdih, thdih, shDI_notifier);
|
512 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[27], tsdil, thdil, shDI_notifier);
|
513 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[27], tsdih, thdih, shDI_notifier);
|
514 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[28], tsdil, thdil, shDI_notifier);
|
515 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[28], tsdih, thdih, shDI_notifier);
|
516 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[29], tsdil, thdil, shDI_notifier);
|
517 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[29], tsdih, thdih, shDI_notifier);
|
518 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[30], tsdil, thdil, shDI_notifier);
|
519 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[30], tsdih, thdih, shDI_notifier);
|
520 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[31], tsdil, thdil, shDI_notifier);
|
521 |
|
|
$setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[31], tsdih, thdih, shDI_notifier);
|
522 |
|
|
|
523 |
|
|
$period(posedge CK, tcyc, mpwCK_notifier);
|
524 |
|
|
$width(negedge CK, tlck, 0, mpwCK_notifier);
|
525 |
|
|
$width(posedge CK, thck, 0, pwhCK_notifier);
|
526 |
|
|
|
527 |
|
|
endspecify
|
528 |
|
|
|
529 |
|
|
endmodule
|
530 |
|
|
`endcelldefine
|