| 1 |
10 |
eexuke |
//-----------------------------------------------------------------------
|
| 2 |
|
|
// Design : nova
|
| 3 |
|
|
// Author(s) : Ke Xu
|
| 4 |
|
|
// Email : eexuke@yahoo.com
|
| 5 |
|
|
// File : DF_mem_ctrl.v
|
| 6 |
|
|
// Generated : Nov 27,2005
|
| 7 |
|
|
// Copyright (C) 2008 Ke Xu
|
| 8 |
|
|
//-------------------------------------------------------------------------------------------------
|
| 9 |
|
|
// Description
|
| 10 |
|
|
// controller for DF_mbAddrA_RAM & DF_mbAddrB_RAM & dis_frame_RAM
|
| 11 |
|
|
//-------------------------------------------------------------------------------------------------
|
| 12 |
|
|
|
| 13 |
|
|
// synopsys translate_off
|
| 14 |
|
|
`include "timescale.v"
|
| 15 |
|
|
// synopsys translate_on
|
| 16 |
|
|
`include "nova_defines.v"
|
| 17 |
|
|
|
| 18 |
|
|
module DF_mem_ctrl (clk,reset_n,gclk_end_of_MB_DEC,disable_DF,mb_num_h,mb_num_v,
|
| 19 |
|
|
bs_curr_MR,bs_curr_MW,blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order,
|
| 20 |
|
|
DF_edge_counter_MR,DF_edge_counter_MW,one_edge_counter_MR,one_edge_counter_MW,
|
| 21 |
|
|
blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
|
| 22 |
|
|
p3_MW,p2_MW,p1_MW,p0_MW,q3_MW,q2_MW,q1_MW,q0_MW,
|
| 23 |
|
|
buf0_0,buf0_1,buf0_2,buf0_3,
|
| 24 |
|
|
buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3,
|
| 25 |
|
|
t0_0,t0_1,t0_2,t0_3,t1_0,t1_1,t1_2,t1_3,t2_0,t2_1,t2_2,t2_3,
|
| 26 |
|
|
|
| 27 |
|
|
mb_num_h_DF,mb_num_v_DF,end_of_MB_DF,end_of_lastMB_DF,
|
| 28 |
|
|
DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,DF_mbAddrA_RF_rd_addr,DF_mbAddrA_RF_wr_addr,DF_mbAddrA_RF_din,
|
| 29 |
|
|
DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr,DF_mbAddrB_RAM_addr,DF_mbAddrB_RAM_din,
|
| 30 |
|
|
dis_frame_RAM_wr,dis_frame_RAM_wr_addr,dis_frame_RAM_din);
|
| 31 |
|
|
input clk,reset_n;
|
| 32 |
|
|
input disable_DF;
|
| 33 |
|
|
input gclk_end_of_MB_DEC;
|
| 34 |
|
|
input [3:0] mb_num_h;
|
| 35 |
|
|
input [3:0] mb_num_v;
|
| 36 |
|
|
input [2:0] bs_curr_MR,bs_curr_MW;
|
| 37 |
|
|
input [2:0] blk4x4_sum_counter;
|
| 38 |
|
|
input [4:0] blk4x4_rec_counter_2_raster_order;
|
| 39 |
|
|
input [5:0] DF_edge_counter_MR,DF_edge_counter_MW;
|
| 40 |
|
|
input [1:0] one_edge_counter_MR,one_edge_counter_MW;
|
| 41 |
|
|
input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
|
| 42 |
|
|
input [7:0] p3_MW,p2_MW,p1_MW,p0_MW;
|
| 43 |
|
|
input [7:0] q3_MW,q2_MW,q1_MW,q0_MW;
|
| 44 |
|
|
input [31:0] buf0_0,buf0_1,buf0_2,buf0_3;
|
| 45 |
|
|
input [31:0] buf2_0,buf2_1,buf2_2,buf2_3;
|
| 46 |
|
|
input [31:0] buf3_0,buf3_1,buf3_2,buf3_3;
|
| 47 |
|
|
input [31:0] t0_0,t0_1,t0_2,t0_3;
|
| 48 |
|
|
input [31:0] t1_0,t1_1,t1_2,t1_3;
|
| 49 |
|
|
input [31:0] t2_0,t2_1,t2_2,t2_3;
|
| 50 |
|
|
|
| 51 |
|
|
output [3:0] mb_num_h_DF;
|
| 52 |
|
|
output [3:0] mb_num_v_DF;
|
| 53 |
|
|
output end_of_MB_DF;
|
| 54 |
|
|
output end_of_lastMB_DF;
|
| 55 |
|
|
output DF_mbAddrA_RF_rd;
|
| 56 |
|
|
output DF_mbAddrA_RF_wr;
|
| 57 |
|
|
output [4:0] DF_mbAddrA_RF_rd_addr;
|
| 58 |
|
|
output [4:0] DF_mbAddrA_RF_wr_addr;
|
| 59 |
|
|
output [31:0] DF_mbAddrA_RF_din;
|
| 60 |
|
|
|
| 61 |
|
|
output DF_mbAddrB_RAM_rd;
|
| 62 |
|
|
output DF_mbAddrB_RAM_wr;
|
| 63 |
|
|
output [8:0] DF_mbAddrB_RAM_addr;
|
| 64 |
|
|
output [31:0] DF_mbAddrB_RAM_din;
|
| 65 |
|
|
|
| 66 |
|
|
output dis_frame_RAM_wr;
|
| 67 |
|
|
output [13:0] dis_frame_RAM_wr_addr;
|
| 68 |
|
|
output [31:0] dis_frame_RAM_din;
|
| 69 |
|
|
|
| 70 |
|
|
wire Is_mbAddrA_wr;
|
| 71 |
|
|
wire Is_mbAddrA_real_wr;
|
| 72 |
|
|
wire Is_mbAddrA_virtual_wr;
|
| 73 |
|
|
wire Is_mbAddrB_wr;
|
| 74 |
|
|
wire Is_currMB_wr;
|
| 75 |
|
|
wire Is_12cycles_wr;
|
| 76 |
|
|
wire dis_frame_RAM_wr_tmp;
|
| 77 |
|
|
|
| 78 |
|
|
reg [3:0] mb_num_h_DF;
|
| 79 |
|
|
reg [3:0] mb_num_v_DF;
|
| 80 |
|
|
always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)
|
| 81 |
|
|
if (reset_n == 1'b0)
|
| 82 |
|
|
begin mb_num_h_DF <= 0; mb_num_v_DF <= 0; end
|
| 83 |
|
|
else if (!disable_DF)
|
| 84 |
|
|
begin mb_num_h_DF <= mb_num_h; mb_num_v_DF <= mb_num_v; end
|
| 85 |
|
|
|
| 86 |
|
|
|
| 87 |
|
|
reg [3:0] DF_12_cycles;
|
| 88 |
|
|
always @ (posedge clk)
|
| 89 |
|
|
if (reset_n == 1'b0)
|
| 90 |
|
|
DF_12_cycles <= 4'd12;
|
| 91 |
|
|
else if (!disable_DF && DF_edge_counter_MW == 6'd47 && one_edge_counter_MW == 2'd3)
|
| 92 |
|
|
DF_12_cycles <= 0;
|
| 93 |
|
|
else if (DF_12_cycles != 4'd12)
|
| 94 |
|
|
DF_12_cycles <= DF_12_cycles + 1;
|
| 95 |
|
|
|
| 96 |
|
|
reg end_of_MB_DF;
|
| 97 |
|
|
reg end_of_lastMB_DF;//end of MB_DF of 98th MB of one frame.Does not need to rise MB_rec_DF_align since there is only
|
| 98 |
|
|
//DF and no reconstruction.So dispart end_of_lastMB_DF from end_of_MB_DF
|
| 99 |
|
|
|
| 100 |
|
|
always @ (posedge clk)
|
| 101 |
|
|
if (reset_n == 1'b0)
|
| 102 |
|
|
begin
|
| 103 |
|
|
end_of_MB_DF <= 1'b0;
|
| 104 |
|
|
end_of_lastMB_DF <= 1'b0;
|
| 105 |
|
|
end
|
| 106 |
|
|
else if (DF_12_cycles == 4'd11)
|
| 107 |
|
|
begin
|
| 108 |
|
|
end_of_MB_DF <= (!(mb_num_h_DF == 10 && mb_num_v_DF == 8))? 1'b1:1'b0;
|
| 109 |
|
|
end_of_lastMB_DF <= (mb_num_h_DF == 10 && mb_num_v_DF == 8)? 1'b1:1'b0;
|
| 110 |
|
|
end
|
| 111 |
|
|
else
|
| 112 |
|
|
begin
|
| 113 |
|
|
end_of_MB_DF <= 1'b0;
|
| 114 |
|
|
end_of_lastMB_DF <= 1'b0;
|
| 115 |
|
|
end
|
| 116 |
|
|
|
| 117 |
|
|
wire [1:0] write_0to3_cycle;
|
| 118 |
|
|
assign write_0to3_cycle = (DF_12_cycles == 4'd12)? one_edge_counter_MW:DF_12_cycles[1:0];
|
| 119 |
|
|
//-------------------------------------------------------------------
|
| 120 |
|
|
//DF_mbAddrA_RF control
|
| 121 |
|
|
//-------------------------------------------------------------------
|
| 122 |
|
|
|
| 123 |
|
|
//For edge 18,34,42,it will update mbAddrB of left MB.So no matter bs_curr_MR is equal to 0 or not,
|
| 124 |
|
|
//mbAddrA should be read out for writing to mbAddrB of left MB.Otherwise,the value written to left
|
| 125 |
|
|
//mbAddrB will be a wrong value.
|
| 126 |
|
|
assign DF_mbAddrA_RF_rd = (mb_num_h_DF != 0 && (((
|
| 127 |
|
|
DF_edge_counter_MR == 6'd0 || DF_edge_counter_MR == 6'd2 || DF_edge_counter_MR == 6'd16 ||
|
| 128 |
|
|
DF_edge_counter_MR == 6'd32 || DF_edge_counter_MR == 6'd40) && bs_curr_MR != 0) || (
|
| 129 |
|
|
DF_edge_counter_MR == 6'd18 || DF_edge_counter_MR == 6'd34 || DF_edge_counter_MR == 6'd42)));
|
| 130 |
|
|
|
| 131 |
|
|
assign DF_mbAddrA_RF_wr = (DF_edge_counter_MW == 6'd16 || DF_edge_counter_MW == 6'd30 ||
|
| 132 |
|
|
DF_edge_counter_MW == 6'd32 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd40 ||
|
| 133 |
|
|
DF_edge_counter_MW == 6'd41 || DF_12_cycles[3:2] == 2'b01 || DF_12_cycles[3:2] == 2'b10);
|
| 134 |
|
|
//DF_mbAddrA_RF_rd_addr
|
| 135 |
|
|
reg [2:0] DF_mbAddrA_RF_rd_addr_blk4x4;
|
| 136 |
|
|
always @ (DF_mbAddrA_RF_rd or DF_edge_counter_MR)
|
| 137 |
|
|
if (DF_mbAddrA_RF_rd)
|
| 138 |
|
|
case (DF_edge_counter_MR)
|
| 139 |
|
|
6'd0 :DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd0; //mbAddrA0
|
| 140 |
|
|
6'd2 :DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd1; //mbAddrA1
|
| 141 |
|
|
6'd16:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd2; //mbAddrA2
|
| 142 |
|
|
6'd18:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd3; //mbAddrA3
|
| 143 |
|
|
6'd32:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd4; //mbAddrA4
|
| 144 |
|
|
6'd34:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd5; //mbAddrA5
|
| 145 |
|
|
6'd40:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd6; //mbAddrA6
|
| 146 |
|
|
6'd42:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd7; //mbAddrA7
|
| 147 |
|
|
default:DF_mbAddrA_RF_rd_addr_blk4x4 <= 0;
|
| 148 |
|
|
endcase
|
| 149 |
|
|
else
|
| 150 |
|
|
DF_mbAddrA_RF_rd_addr_blk4x4 <= 0;
|
| 151 |
|
|
assign DF_mbAddrA_RF_rd_addr = {5{DF_mbAddrA_RF_rd}} &
|
| 152 |
|
|
({DF_mbAddrA_RF_rd_addr_blk4x4,2'b0} + one_edge_counter_MR);
|
| 153 |
|
|
//DF_mbAddrA_RF_wr_addr
|
| 154 |
|
|
reg [2:0] DF_mbAddrA_RF_wr_addr_blk4x4;
|
| 155 |
|
|
always @ (DF_mbAddrA_RF_wr or DF_edge_counter_MW or DF_12_cycles[3:2])
|
| 156 |
|
|
if (DF_mbAddrA_RF_wr)
|
| 157 |
|
|
begin
|
| 158 |
|
|
if (DF_edge_counter_MW != 6'd48)
|
| 159 |
|
|
case (DF_edge_counter_MW)
|
| 160 |
|
|
6'd16:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd0; //mbAddrA0
|
| 161 |
|
|
6'd30:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd1; //mbAddrA1
|
| 162 |
|
|
6'd32:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd2; //mbAddrA2
|
| 163 |
|
|
6'd33:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd3; //mbAddrA3
|
| 164 |
|
|
6'd40:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd4; //mbAddrA4
|
| 165 |
|
|
6'd41:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd5; //mbAddrA5
|
| 166 |
|
|
default:DF_mbAddrA_RF_wr_addr_blk4x4 <= 0;
|
| 167 |
|
|
endcase
|
| 168 |
|
|
else if (DF_12_cycles[3:2] == 2'b01)
|
| 169 |
|
|
DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd6;
|
| 170 |
|
|
else
|
| 171 |
|
|
DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd7;
|
| 172 |
|
|
end
|
| 173 |
|
|
else
|
| 174 |
|
|
DF_mbAddrA_RF_wr_addr_blk4x4 <= 0;
|
| 175 |
|
|
|
| 176 |
|
|
assign DF_mbAddrA_RF_wr_addr = {5{DF_mbAddrA_RF_wr}} &
|
| 177 |
|
|
({DF_mbAddrA_RF_wr_addr_blk4x4,2'b0} + write_0to3_cycle);
|
| 178 |
|
|
|
| 179 |
|
|
//DF_mbAddrA_RF_din
|
| 180 |
|
|
wire Is_mbAddrA_t1;
|
| 181 |
|
|
assign Is_mbAddrA_t1 = (DF_edge_counter_MW == 6'd30 || DF_edge_counter_MW == 6'd33 ||
|
| 182 |
|
|
DF_edge_counter_MW == 6'd41 || DF_12_cycles[3:2] == 2'b10);
|
| 183 |
|
|
|
| 184 |
|
|
reg [31:0] DF_mbAddrA_RF_din;
|
| 185 |
|
|
always @ (DF_mbAddrA_RF_wr or Is_mbAddrA_t1 or write_0to3_cycle or
|
| 186 |
|
|
t0_0 or t0_1 or t0_2 or t0_3 or t1_0 or t1_1 or t1_2 or t1_3)
|
| 187 |
|
|
if (DF_mbAddrA_RF_wr)
|
| 188 |
|
|
begin
|
| 189 |
|
|
if (Is_mbAddrA_t1)
|
| 190 |
|
|
case (write_0to3_cycle)
|
| 191 |
|
|
2'd0:DF_mbAddrA_RF_din <= t1_0;
|
| 192 |
|
|
2'd1:DF_mbAddrA_RF_din <= t1_1;
|
| 193 |
|
|
2'd2:DF_mbAddrA_RF_din <= t1_2;
|
| 194 |
|
|
2'd3:DF_mbAddrA_RF_din <= t1_3;
|
| 195 |
|
|
endcase
|
| 196 |
|
|
else
|
| 197 |
|
|
case (write_0to3_cycle)
|
| 198 |
|
|
2'd0:DF_mbAddrA_RF_din <= t0_0;
|
| 199 |
|
|
2'd1:DF_mbAddrA_RF_din <= t0_1;
|
| 200 |
|
|
2'd2:DF_mbAddrA_RF_din <= t0_2;
|
| 201 |
|
|
2'd3:DF_mbAddrA_RF_din <= t0_3;
|
| 202 |
|
|
endcase
|
| 203 |
|
|
end
|
| 204 |
|
|
else
|
| 205 |
|
|
DF_mbAddrA_RF_din <= 0;
|
| 206 |
|
|
//-------------------------------------------------------------------
|
| 207 |
|
|
//DF_mbAddrB_RAM control
|
| 208 |
|
|
//-------------------------------------------------------------------
|
| 209 |
|
|
assign DF_mbAddrB_RAM_rd = (((
|
| 210 |
|
|
DF_edge_counter_MR == 6'd4 || DF_edge_counter_MR == 6'd8 || DF_edge_counter_MR == 6'd12 ||
|
| 211 |
|
|
DF_edge_counter_MR == 6'd13 || DF_edge_counter_MR == 6'd36 || DF_edge_counter_MR == 6'd37 ||
|
| 212 |
|
|
DF_edge_counter_MR == 6'd44 || DF_edge_counter_MR == 6'd45) && mb_num_v_DF != 0) ||
|
| 213 |
|
|
DF_edge_counter_MR == 6'd20 || DF_edge_counter_MR == 6'd24 || DF_edge_counter_MR == 6'd28 ||
|
| 214 |
|
|
DF_edge_counter_MR == 6'd29);
|
| 215 |
|
|
|
| 216 |
|
|
wire DF_mbAddrB_RAM_wr_curr;
|
| 217 |
|
|
assign DF_mbAddrB_RAM_wr_curr = (((
|
| 218 |
|
|
DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd30 ||
|
| 219 |
|
|
DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd38 || DF_edge_counter_MW == 6'd39 ||
|
| 220 |
|
|
DF_edge_counter_MW == 6'd46 || DF_edge_counter_MW == 6'd47) && mb_num_v_DF != 4'd8) ||
|
| 221 |
|
|
DF_edge_counter_MW == 6'd5 || DF_edge_counter_MW == 6'd9 || DF_edge_counter_MW == 6'd14 ||
|
| 222 |
|
|
DF_edge_counter_MW == 6'd15);
|
| 223 |
|
|
|
| 224 |
|
|
wire DF_mbAddrB_RAM_wr_leftMB;
|
| 225 |
|
|
assign DF_mbAddrB_RAM_wr_leftMB = (mb_num_h_DF != 0 && mb_num_v_DF != 4'd8 && (
|
| 226 |
|
|
DF_edge_counter_MW == 6'd20 || DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd45));
|
| 227 |
|
|
|
| 228 |
|
|
assign DF_mbAddrB_RAM_wr = DF_mbAddrB_RAM_wr_curr | DF_mbAddrB_RAM_wr_leftMB;
|
| 229 |
|
|
|
| 230 |
|
|
reg [2:0] DF_mbAddrB_RAM_addr_blk4x4;
|
| 231 |
|
|
always @ (DF_mbAddrB_RAM_rd or DF_edge_counter_MR or DF_mbAddrB_RAM_wr_curr
|
| 232 |
|
|
or DF_mbAddrB_RAM_wr_leftMB or DF_edge_counter_MW)
|
| 233 |
|
|
if (DF_mbAddrB_RAM_rd)
|
| 234 |
|
|
case (DF_edge_counter_MR)
|
| 235 |
|
|
6'd4, 6'd20:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd0;
|
| 236 |
|
|
6'd8, 6'd24:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd1;
|
| 237 |
|
|
6'd12,6'd28:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd2;
|
| 238 |
|
|
6'd13,6'd29:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3;
|
| 239 |
|
|
6'd36 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd4;
|
| 240 |
|
|
6'd37 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5;
|
| 241 |
|
|
6'd44 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd6;
|
| 242 |
|
|
6'd45 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7;
|
| 243 |
|
|
default :DF_mbAddrB_RAM_addr_blk4x4 <= 0;
|
| 244 |
|
|
endcase
|
| 245 |
|
|
else if (DF_mbAddrB_RAM_wr_curr)
|
| 246 |
|
|
case (DF_edge_counter_MW)
|
| 247 |
|
|
6'd5, 6'd21:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd0;
|
| 248 |
|
|
6'd9, 6'd25:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd1;
|
| 249 |
|
|
6'd14,6'd30:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd2;
|
| 250 |
|
|
6'd15,6'd31:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3;
|
| 251 |
|
|
6'd38 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd4;
|
| 252 |
|
|
6'd39 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5;
|
| 253 |
|
|
6'd46 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd6;
|
| 254 |
|
|
6'd47 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7;
|
| 255 |
|
|
default :DF_mbAddrB_RAM_addr_blk4x4 <= 0;
|
| 256 |
|
|
endcase
|
| 257 |
|
|
else if (DF_mbAddrB_RAM_wr_leftMB)
|
| 258 |
|
|
case (DF_edge_counter_MW)
|
| 259 |
|
|
6'd20:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3;
|
| 260 |
|
|
6'd37:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5;
|
| 261 |
|
|
default:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7;
|
| 262 |
|
|
endcase
|
| 263 |
|
|
else
|
| 264 |
|
|
DF_mbAddrB_RAM_addr_blk4x4 <= 0;
|
| 265 |
|
|
|
| 266 |
|
|
reg [1:0] DF_mbAddrB_RAM_addr_offset;
|
| 267 |
|
|
always @ (DF_mbAddrB_RAM_rd or one_edge_counter_MR or DF_mbAddrB_RAM_wr or one_edge_counter_MW)
|
| 268 |
|
|
if (DF_mbAddrB_RAM_rd) DF_mbAddrB_RAM_addr_offset <= one_edge_counter_MR;
|
| 269 |
|
|
else if (DF_mbAddrB_RAM_wr) DF_mbAddrB_RAM_addr_offset <= one_edge_counter_MW;
|
| 270 |
|
|
else DF_mbAddrB_RAM_addr_offset <= 0;
|
| 271 |
|
|
|
| 272 |
|
|
wire [3:0] mb_num_h_DF_m1;
|
| 273 |
|
|
assign mb_num_h_DF_m1 = {4{Is_mbAddrA_wr | DF_mbAddrB_RAM_wr_leftMB}} & (mb_num_h_DF - 1);
|
| 274 |
|
|
|
| 275 |
|
|
wire [8:0] mb_num_h_DF_x32;
|
| 276 |
|
|
assign mb_num_h_DF_x32 = (DF_mbAddrB_RAM_wr_leftMB)? {mb_num_h_DF_m1,5'b0}:{mb_num_h_DF,5'b0};
|
| 277 |
|
|
assign DF_mbAddrB_RAM_addr = mb_num_h_DF_x32 + {DF_mbAddrB_RAM_addr_blk4x4,2'b0} + DF_mbAddrB_RAM_addr_offset;
|
| 278 |
|
|
|
| 279 |
|
|
reg [31:0] DF_mbAddrB_RAM_din;
|
| 280 |
|
|
always @ (DF_mbAddrB_RAM_wr_curr or DF_mbAddrB_RAM_wr_leftMB or one_edge_counter_MW
|
| 281 |
|
|
or q0_MW or q1_MW or q2_MW or q3_MW or t2_0 or t2_1 or t2_2 or t2_3)
|
| 282 |
|
|
if (DF_mbAddrB_RAM_wr_curr)
|
| 283 |
|
|
DF_mbAddrB_RAM_din <= {q3_MW,q2_MW,q1_MW,q0_MW};
|
| 284 |
|
|
else if (DF_mbAddrB_RAM_wr_leftMB)
|
| 285 |
|
|
case (one_edge_counter_MW)
|
| 286 |
|
|
2'd0:DF_mbAddrB_RAM_din <= t2_0;
|
| 287 |
|
|
2'd1:DF_mbAddrB_RAM_din <= t2_1;
|
| 288 |
|
|
2'd2:DF_mbAddrB_RAM_din <= t2_2;
|
| 289 |
|
|
2'd3:DF_mbAddrB_RAM_din <= t2_3;
|
| 290 |
|
|
endcase
|
| 291 |
|
|
else
|
| 292 |
|
|
DF_mbAddrB_RAM_din <= 0;
|
| 293 |
|
|
//-------------------------------------------------------------------
|
| 294 |
|
|
//dis_frame_RAM write control
|
| 295 |
|
|
//-------------------------------------------------------------------
|
| 296 |
|
|
//dis_frame_RAM_wr
|
| 297 |
|
|
assign Is_mbAddrA_wr = (mb_num_h_DF != 0 && (
|
| 298 |
|
|
DF_edge_counter_MW == 6'd0 || DF_edge_counter_MW == 6'd2 || DF_edge_counter_MW == 6'd16 ||
|
| 299 |
|
|
DF_edge_counter_MW == 6'd18 || DF_edge_counter_MW == 6'd32 || DF_edge_counter_MW == 6'd34 ||
|
| 300 |
|
|
DF_edge_counter_MW == 6'd40 || DF_edge_counter_MW == 6'd42));
|
| 301 |
|
|
assign Is_mbAddrA_real_wr = (Is_mbAddrA_wr && bs_curr_MW != 0);
|
| 302 |
|
|
assign Is_mbAddrA_virtual_wr = (Is_mbAddrA_wr && bs_curr_MW == 0);
|
| 303 |
|
|
|
| 304 |
|
|
assign Is_mbAddrB_wr = (mb_num_v_DF != 0 && (
|
| 305 |
|
|
DF_edge_counter_MW == 6'd5 || DF_edge_counter_MW == 6'd9 || DF_edge_counter_MW == 6'd13 ||
|
| 306 |
|
|
DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd38 ||
|
| 307 |
|
|
DF_edge_counter_MW == 6'd45 || DF_edge_counter_MW == 6'd46));
|
| 308 |
|
|
assign Is_currMB_wr = ((
|
| 309 |
|
|
DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd15 ||
|
| 310 |
|
|
DF_edge_counter_MW == 6'd17 || DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd22 ||
|
| 311 |
|
|
DF_edge_counter_MW == 6'd23 || DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd26 ||
|
| 312 |
|
|
DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd29 || DF_edge_counter_MW == 6'd30 ||
|
| 313 |
|
|
DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd35 ||
|
| 314 |
|
|
DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd39 || DF_edge_counter_MW == 6'd41 ||
|
| 315 |
|
|
DF_edge_counter_MW == 6'd43 || DF_edge_counter_MW == 6'd44 || DF_edge_counter_MW == 6'd47) &&
|
| 316 |
|
|
one_edge_counter_MW != 3'd4);
|
| 317 |
|
|
assign Is_12cycles_wr = (DF_12_cycles != 4'd12);
|
| 318 |
|
|
|
| 319 |
|
|
assign dis_frame_RAM_wr_tmp =
|
| 320 |
|
|
( disable_DF && blk4x4_sum_counter[2] != 1'b1) ||
|
| 321 |
|
|
(!disable_DF && (Is_mbAddrA_wr || Is_mbAddrB_wr || Is_currMB_wr || Is_12cycles_wr));
|
| 322 |
|
|
assign dis_frame_RAM_wr = (dis_frame_RAM_wr_tmp & (~Is_mbAddrA_virtual_wr));
|
| 323 |
|
|
|
| 324 |
|
|
wire Is_luma_wr;
|
| 325 |
|
|
wire Is_chroma_wr;
|
| 326 |
|
|
wire Is_1st_cycle_wr; //if it is the position of first line of a 4x4 block,for both DF disable & enable
|
| 327 |
|
|
wire Is_MB_LeftTop_wr; //if it is the position of most left-top for a whole MB,only for DF is disabled
|
| 328 |
|
|
assign Is_luma_wr = (dis_frame_RAM_wr_tmp && (
|
| 329 |
|
|
(disable_DF && blk4x4_rec_counter_2_raster_order[4] == 1'b0) ||
|
| 330 |
|
|
(!disable_DF && (((Is_mbAddrA_wr || Is_mbAddrB_wr) && !DF_edge_counter_MW[5]) ||
|
| 331 |
|
|
(Is_currMB_wr && DF_edge_counter_MW < 6'd39)))))? 1'b1:1'b0;
|
| 332 |
|
|
|
| 333 |
|
|
assign Is_chroma_wr = (dis_frame_RAM_wr_tmp && !Is_luma_wr)? 1'b1:1'b0;
|
| 334 |
|
|
|
| 335 |
|
|
assign Is_1st_cycle_wr = (
|
| 336 |
|
|
( disable_DF && blk4x4_sum_counter == 0) ||
|
| 337 |
|
|
(!disable_DF && (one_edge_counter_MW == 0 && (Is_mbAddrA_wr || Is_mbAddrB_wr || Is_currMB_wr)) ||
|
| 338 |
|
|
(DF_12_cycles[1:0] == 2'b00 && DF_12_cycles[3:2] != 2'b11)))? 1'b1:1'b0;
|
| 339 |
|
|
|
| 340 |
|
|
assign Is_MB_LeftTop_wr = (disable_DF && blk4x4_sum_counter == 0 && (
|
| 341 |
|
|
(blk4x4_rec_counter_2_raster_order[4] == 1'b0 && blk4x4_rec_counter_2_raster_order[3:0] == 4'b0) ||
|
| 342 |
|
|
(blk4x4_rec_counter_2_raster_order[4] == 1'b1 && blk4x4_rec_counter_2_raster_order[1:0] == 2'b0))) ? 1'b1:1'b0;
|
| 343 |
|
|
|
| 344 |
|
|
//---------------------------------------------------------------------------------
|
| 345 |
|
|
// dis_frame_RAM_wr_addr_base
|
| 346 |
|
|
// Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged)
|
| 347 |
|
|
// Luma:0 Cb:6336 Cr:7920
|
| 348 |
|
|
//---------------------------------------------------------------------------------
|
| 349 |
|
|
reg [12:0] dis_frame_RAM_wr_addr_base;
|
| 350 |
|
|
always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_12cycles_wr
|
| 351 |
|
|
or blk4x4_rec_counter_2_raster_order[2] or DF_edge_counter_MW)
|
| 352 |
|
|
if (disable_DF)
|
| 353 |
|
|
begin
|
| 354 |
|
|
if (Is_MB_LeftTop_wr)
|
| 355 |
|
|
begin
|
| 356 |
|
|
if (Is_luma_wr) //luma
|
| 357 |
|
|
dis_frame_RAM_wr_addr_base <= 13'd0;
|
| 358 |
|
|
else if (blk4x4_rec_counter_2_raster_order[2] == 1'b0) //Cb
|
| 359 |
|
|
dis_frame_RAM_wr_addr_base <= 13'd6336;
|
| 360 |
|
|
else //Cr
|
| 361 |
|
|
dis_frame_RAM_wr_addr_base <= 13'd7920;
|
| 362 |
|
|
end
|
| 363 |
|
|
else
|
| 364 |
|
|
dis_frame_RAM_wr_addr_base <= 13'd0;
|
| 365 |
|
|
end
|
| 366 |
|
|
else
|
| 367 |
|
|
begin
|
| 368 |
|
|
if (Is_1st_cycle_wr) //update only @ 1st write cycle
|
| 369 |
|
|
begin
|
| 370 |
|
|
if (Is_luma_wr) //luma
|
| 371 |
|
|
dis_frame_RAM_wr_addr_base <= 13'd0;
|
| 372 |
|
|
else if (DF_edge_counter_MW < 6'd45 && DF_edge_counter_MW != 40 && DF_edge_counter_MW != 42) //Cb
|
| 373 |
|
|
dis_frame_RAM_wr_addr_base <= 13'd6336;
|
| 374 |
|
|
else //Cr
|
| 375 |
|
|
dis_frame_RAM_wr_addr_base <= 13'd7920;
|
| 376 |
|
|
end
|
| 377 |
|
|
else
|
| 378 |
|
|
dis_frame_RAM_wr_addr_base <= 0;
|
| 379 |
|
|
end
|
| 380 |
|
|
//---------------------------------------------------------------------------------
|
| 381 |
|
|
// dis_frame_RAM_wr_addr_x
|
| 382 |
|
|
// Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged)
|
| 383 |
|
|
// x position inside a frame,since every 4 horizontal pixels have been combined as
|
| 384 |
|
|
// a single 32bit word,thus 0 ~ 43 for luma and 0 ~ 21 for chroma
|
| 385 |
|
|
//---------------------------------------------------------------------------------
|
| 386 |
|
|
wire [3:0] mb_num_v_DF_m1;
|
| 387 |
|
|
assign mb_num_v_DF_m1 = {4{Is_mbAddrB_wr}} & (mb_num_v_DF - 1);
|
| 388 |
|
|
|
| 389 |
|
|
reg [1:0] blk4x4_xoffset; //0 ~ 3,xoffset for blk4x4 inside a MB
|
| 390 |
|
|
always @ (Is_luma_wr or Is_mbAddrA_wr or Is_mbAddrB_wr or Is_currMB_wr or DF_12_cycles or DF_edge_counter_MW)
|
| 391 |
|
|
case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr})
|
| 392 |
|
|
3'b100: //Is_mbAddrA_wr
|
| 393 |
|
|
if (Is_luma_wr) blk4x4_xoffset <= 2'd3;
|
| 394 |
|
|
else blk4x4_xoffset <= 2'd1;
|
| 395 |
|
|
3'b010: //Is_mbAddrB_wr
|
| 396 |
|
|
case (DF_edge_counter_MW)
|
| 397 |
|
|
6'd5,6'd37,6'd45:blk4x4_xoffset <= 2'd0;
|
| 398 |
|
|
6'd9,6'd38,6'd46:blk4x4_xoffset <= 2'd1;
|
| 399 |
|
|
6'd13 :blk4x4_xoffset <= 2'd2;
|
| 400 |
|
|
6'd14 :blk4x4_xoffset <= 2'd3;
|
| 401 |
|
|
default :blk4x4_xoffset <= 0;
|
| 402 |
|
|
endcase
|
| 403 |
|
|
3'b001: //Is_currMB_wr
|
| 404 |
|
|
case (DF_edge_counter_MW)
|
| 405 |
|
|
//6'd6,6'd21,6'd23,6'd22,6'd39,6'd41,6'd47:blk4x4_xoffset <= 0;
|
| 406 |
|
|
6'd10,6'd25,6'd27,6'd26,6'd43,6'd44 :blk4x4_xoffset <= 2'd1;
|
| 407 |
|
|
6'd15,6'd29,6'd31,6'd33 :blk4x4_xoffset <= 2'd2;
|
| 408 |
|
|
6'd17,6'd30,6'd35,6'd36 :blk4x4_xoffset <= 2'd3;
|
| 409 |
|
|
default :blk4x4_xoffset <= 0;
|
| 410 |
|
|
endcase
|
| 411 |
|
|
default:
|
| 412 |
|
|
if (DF_12_cycles != 4'd12)
|
| 413 |
|
|
case (DF_12_cycles[3:2])
|
| 414 |
|
|
2'b00 :blk4x4_xoffset <= 0; //buf2 -> blk22
|
| 415 |
|
|
2'b01,2'b10 :blk4x4_xoffset <= 2'd1; //T0 -> blk21,T1 -> blk23
|
| 416 |
|
|
default :blk4x4_xoffset <= 0;
|
| 417 |
|
|
endcase
|
| 418 |
|
|
else
|
| 419 |
|
|
blk4x4_xoffset <= 0;
|
| 420 |
|
|
endcase
|
| 421 |
|
|
|
| 422 |
|
|
reg [5:0] dis_frame_RAM_wr_addr_x;
|
| 423 |
|
|
|
| 424 |
|
|
always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_mbAddrA_wr
|
| 425 |
|
|
or Is_mbAddrB_wr or Is_currMB_wr or blk4x4_rec_counter_2_raster_order[1:0]
|
| 426 |
|
|
or mb_num_h or mb_num_h_DF_m1 or mb_num_h_DF or blk4x4_xoffset)
|
| 427 |
|
|
if (disable_DF)
|
| 428 |
|
|
begin
|
| 429 |
|
|
if (Is_MB_LeftTop_wr)
|
| 430 |
|
|
dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h,2'b0} + blk4x4_rec_counter_2_raster_order[1:0]):({1'b0,mb_num_h,1'b0} + blk4x4_rec_counter_2_raster_order[0]);
|
| 431 |
|
|
else
|
| 432 |
|
|
dis_frame_RAM_wr_addr_x <= 0;
|
| 433 |
|
|
end
|
| 434 |
|
|
else
|
| 435 |
|
|
begin
|
| 436 |
|
|
if (Is_1st_cycle_wr)
|
| 437 |
|
|
case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr})
|
| 438 |
|
|
3'b100: //Is_mbAddrA_wr
|
| 439 |
|
|
dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h_DF_m1,2'b0} + blk4x4_xoffset):({1'b0,mb_num_h_DF_m1,1'b0} + blk4x4_xoffset);
|
| 440 |
|
|
3'b010,3'b001: //Is_mbAddrB_wr,Is_currMB_wr
|
| 441 |
|
|
dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h_DF,2'b0} + blk4x4_xoffset):({1'b0,mb_num_h_DF,1'b0} + blk4x4_xoffset);
|
| 442 |
|
|
|
| 443 |
|
|
default: //for DF_12_cycles != 4'd12
|
| 444 |
|
|
dis_frame_RAM_wr_addr_x <= {1'b0,mb_num_h_DF,1'b0} + blk4x4_xoffset;
|
| 445 |
|
|
endcase
|
| 446 |
|
|
else
|
| 447 |
|
|
dis_frame_RAM_wr_addr_x <= 0;
|
| 448 |
|
|
end
|
| 449 |
|
|
//---------------------------------------------------------------------------------
|
| 450 |
|
|
// dis_frame_RAM_wr_addr_y
|
| 451 |
|
|
// a)Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged)
|
| 452 |
|
|
// b)For 2,3,4 write cycles,dis_frame_RAM_wr_addr is directly +44/+22 instead of
|
| 453 |
|
|
// changing dis_frame_RAM_wr_addr_y
|
| 454 |
|
|
// c)y addr increase 1 means +44 for luma or +22 for choma
|
| 455 |
|
|
//---------------------------------------------------------------------------------
|
| 456 |
|
|
reg [1:0] blk4x4_yoffset; //0 ~ 3,yoffset for blk4x4 inside a MB
|
| 457 |
|
|
always @ (Is_mbAddrA_wr or Is_currMB_wr or DF_12_cycles or DF_edge_counter_MW)
|
| 458 |
|
|
if (Is_mbAddrA_wr)
|
| 459 |
|
|
case (DF_edge_counter_MW)
|
| 460 |
|
|
6'd0,6'd32,6'd40:blk4x4_yoffset <= 2'd0;
|
| 461 |
|
|
6'd2,6'd34,6'd42:blk4x4_yoffset <= 2'd1;
|
| 462 |
|
|
6'd16 :blk4x4_yoffset <= 2'd2;
|
| 463 |
|
|
6'd18 :blk4x4_yoffset <= 2'd3;
|
| 464 |
|
|
default :blk4x4_yoffset <= 0;
|
| 465 |
|
|
endcase
|
| 466 |
|
|
else if (Is_currMB_wr)
|
| 467 |
|
|
case (DF_edge_counter_MW)
|
| 468 |
|
|
//6'd6,6'd10,6'd15,6'd17,6'd39,6'd43,6'd47:blk4x4_yoffset <= 0;
|
| 469 |
|
|
6'd21,6'd25,6'd29,6'd30,6'd41,6'd44 :blk4x4_yoffset <= 2'd1;
|
| 470 |
|
|
6'd23,6'd27,6'd31,6'd35 :blk4x4_yoffset <= 2'd2;
|
| 471 |
|
|
6'd22,6'd26,6'd33,6'd36 :blk4x4_yoffset <= 2'd3;
|
| 472 |
|
|
default :blk4x4_yoffset <= 0;
|
| 473 |
|
|
endcase
|
| 474 |
|
|
else if (DF_12_cycles != 4'd12)
|
| 475 |
|
|
case (DF_12_cycles[2])
|
| 476 |
|
|
1'b0:blk4x4_yoffset <= 2'd1; // 0 ~ 3:buf2->22; 8 ~ 11:T1->23
|
| 477 |
|
|
1'b1:blk4x4_yoffset <= 0; // 4 ~ 7:T0->21
|
| 478 |
|
|
endcase
|
| 479 |
|
|
else
|
| 480 |
|
|
blk4x4_yoffset <= 0;
|
| 481 |
|
|
|
| 482 |
|
|
reg [7:0] dis_frame_RAM_wr_addr_y; //y position inside a frame,0 ~ 143 for luma & 0 ~ 71 for chroma
|
| 483 |
|
|
always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr
|
| 484 |
|
|
or Is_mbAddrA_wr or Is_mbAddrB_wr or Is_mbAddrB_wr or Is_currMB_wr
|
| 485 |
|
|
or blk4x4_sum_counter[1:0] or blk4x4_rec_counter_2_raster_order[4:1]
|
| 486 |
|
|
or mb_num_v or mb_num_v_DF or mb_num_v_DF_m1
|
| 487 |
|
|
or one_edge_counter_MW or blk4x4_yoffset or DF_12_cycles)
|
| 488 |
|
|
if (disable_DF)
|
| 489 |
|
|
begin
|
| 490 |
|
|
if (Is_MB_LeftTop_wr)
|
| 491 |
|
|
dis_frame_RAM_wr_addr_y <= (Is_luma_wr)?
|
| 492 |
|
|
({mb_num_v,4'b0} + {blk4x4_rec_counter_2_raster_order[3:2],2'b00} + blk4x4_sum_counter[1:0]):
|
| 493 |
|
|
({1'b0,mb_num_v,3'b0} + {blk4x4_rec_counter_2_raster_order[1], 2'b00} + blk4x4_sum_counter[1:0]);
|
| 494 |
|
|
else
|
| 495 |
|
|
dis_frame_RAM_wr_addr_y <= 0;
|
| 496 |
|
|
end
|
| 497 |
|
|
else
|
| 498 |
|
|
begin
|
| 499 |
|
|
if (Is_1st_cycle_wr)
|
| 500 |
|
|
case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr})
|
| 501 |
|
|
3'b100: //Is_mbAddrA_wr
|
| 502 |
|
|
dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma
|
| 503 |
|
|
(({mb_num_v_DF,4'b0} + {2'b00,blk4x4_yoffset,2'b00}) + one_edge_counter_MW):
|
| 504 |
|
|
(({1'b0,mb_num_v_DF,3'b0} + {2'b00,blk4x4_yoffset,2'b00}) + one_edge_counter_MW);
|
| 505 |
|
|
3'b010: //Is_mbAddrB_wr
|
| 506 |
|
|
dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma
|
| 507 |
|
|
(({mb_num_v_DF_m1,4'b0} + 4'd12) + one_edge_counter_MW):
|
| 508 |
|
|
(({1'b0,mb_num_v_DF_m1,3'b0} + 4'd4 ) + one_edge_counter_MW);
|
| 509 |
|
|
3'b001: //Is_currMB_wr
|
| 510 |
|
|
dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma
|
| 511 |
|
|
(({mb_num_v_DF,4'b0} + {blk4x4_yoffset,2'b0}) + one_edge_counter_MW):
|
| 512 |
|
|
(({1'b0,mb_num_v_DF,3'b0} + {blk4x4_yoffset,2'b0}) + one_edge_counter_MW);
|
| 513 |
|
|
default:
|
| 514 |
|
|
if (DF_12_cycles != 4'd12)
|
| 515 |
|
|
dis_frame_RAM_wr_addr_y <= {mb_num_v_DF,3'b0} + {blk4x4_yoffset,2'b0} + DF_12_cycles[1:0];
|
| 516 |
|
|
else
|
| 517 |
|
|
dis_frame_RAM_wr_addr_y <= 0;
|
| 518 |
|
|
endcase
|
| 519 |
|
|
else
|
| 520 |
|
|
dis_frame_RAM_wr_addr_y <= 0;
|
| 521 |
|
|
end
|
| 522 |
|
|
|
| 523 |
|
|
|
| 524 |
|
|
wire [12:0] dis_frame_RAM_wr_addr_y_ext; //every "y" increase will increase 44(luma) or 22(chroma) for
|
| 525 |
|
|
//dis_frame_RAM address
|
| 526 |
|
|
|
| 527 |
|
|
assign dis_frame_RAM_wr_addr_y_ext = (Is_luma_wr)?
|
| 528 |
|
|
//luma, x44 = x32 + x8 + x4
|
| 529 |
|
|
( {dis_frame_RAM_wr_addr_y,5'b0} + {2'b0,dis_frame_RAM_wr_addr_y,3'b0} + {3'b0,dis_frame_RAM_wr_addr_y,2'b0}):
|
| 530 |
|
|
//chroma,x22 = x16 + x4 + x2
|
| 531 |
|
|
({1'b0,dis_frame_RAM_wr_addr_y,4'b0} + {3'b0,dis_frame_RAM_wr_addr_y,2'b0} + {4'b0,dis_frame_RAM_wr_addr_y,1'b0});
|
| 532 |
|
|
|
| 533 |
|
|
wire [13:0] dis_frame_RAM_wr_addr_tmp;
|
| 534 |
|
|
reg [13:0] dis_frame_RAM_wr_addr_LeftTop_reg;
|
| 535 |
|
|
reg [13:0] dis_frame_RAM_wr_addr_reg;
|
| 536 |
|
|
reg [13:0] dis_frame_RAM_wr_addr;
|
| 537 |
|
|
|
| 538 |
|
|
assign dis_frame_RAM_wr_addr_tmp = dis_frame_RAM_wr_addr_base + dis_frame_RAM_wr_addr_y_ext + dis_frame_RAM_wr_addr_x;
|
| 539 |
|
|
always @ (posedge clk)
|
| 540 |
|
|
if (reset_n == 1'b0)
|
| 541 |
|
|
dis_frame_RAM_wr_addr_LeftTop_reg <= 0;
|
| 542 |
|
|
else if (Is_MB_LeftTop_wr)
|
| 543 |
|
|
dis_frame_RAM_wr_addr_LeftTop_reg <= dis_frame_RAM_wr_addr_tmp;
|
| 544 |
|
|
|
| 545 |
|
|
always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_chroma_wr or dis_frame_RAM_wr_addr_tmp
|
| 546 |
|
|
or dis_frame_RAM_wr_addr_reg or blk4x4_rec_counter_2_raster_order or dis_frame_RAM_wr_addr_LeftTop_reg)
|
| 547 |
|
|
if (disable_DF)
|
| 548 |
|
|
begin
|
| 549 |
|
|
if (Is_MB_LeftTop_wr)
|
| 550 |
|
|
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_tmp;
|
| 551 |
|
|
else if (Is_1st_cycle_wr)
|
| 552 |
|
|
case (blk4x4_rec_counter_2_raster_order[4])
|
| 553 |
|
|
1'b0:
|
| 554 |
|
|
case (blk4x4_rec_counter_2_raster_order[3:2])
|
| 555 |
|
|
2'b00:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0];
|
| 556 |
|
|
2'b01:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 176;
|
| 557 |
|
|
2'b10:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 352;
|
| 558 |
|
|
2'b11:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 528;
|
| 559 |
|
|
endcase
|
| 560 |
|
|
1'b1:
|
| 561 |
|
|
dis_frame_RAM_wr_addr <= (blk4x4_rec_counter_2_raster_order[1])?
|
| 562 |
|
|
(dis_frame_RAM_wr_addr_LeftTop_reg + 88 + blk4x4_rec_counter_2_raster_order[0]):
|
| 563 |
|
|
(dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[0]);
|
| 564 |
|
|
endcase
|
| 565 |
|
|
else if (Is_luma_wr)
|
| 566 |
|
|
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 44;
|
| 567 |
|
|
else if (Is_chroma_wr)
|
| 568 |
|
|
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 22;
|
| 569 |
|
|
else
|
| 570 |
|
|
dis_frame_RAM_wr_addr <= 0;
|
| 571 |
|
|
end
|
| 572 |
|
|
else
|
| 573 |
|
|
begin
|
| 574 |
|
|
if (Is_1st_cycle_wr)
|
| 575 |
|
|
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_tmp;
|
| 576 |
|
|
else if (Is_luma_wr)
|
| 577 |
|
|
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 44;
|
| 578 |
|
|
else if (Is_chroma_wr)
|
| 579 |
|
|
dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 22;
|
| 580 |
|
|
else
|
| 581 |
|
|
dis_frame_RAM_wr_addr <= 0;
|
| 582 |
|
|
end
|
| 583 |
|
|
|
| 584 |
|
|
always @ (posedge clk)
|
| 585 |
|
|
if (reset_n == 1'b0)
|
| 586 |
|
|
dis_frame_RAM_wr_addr_reg <= 0;
|
| 587 |
|
|
else if (dis_frame_RAM_wr_tmp)
|
| 588 |
|
|
dis_frame_RAM_wr_addr_reg <= dis_frame_RAM_wr_addr;
|
| 589 |
|
|
|
| 590 |
|
|
//dis_frame_RAM_din
|
| 591 |
|
|
wire Is_mbAddrB_t1;
|
| 592 |
|
|
wire Is_currMB_buf0;
|
| 593 |
|
|
wire Is_currMB_buf2;
|
| 594 |
|
|
wire Is_currMB_buf3;
|
| 595 |
|
|
wire Is_currMB_t1;
|
| 596 |
|
|
assign Is_mbAddrB_t1 = (DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd38 ||
|
| 597 |
|
|
DF_edge_counter_MW == 6'd46);
|
| 598 |
|
|
assign Is_currMB_buf0 = (DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd15 ||
|
| 599 |
|
|
DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd39 ||
|
| 600 |
|
|
DF_edge_counter_MW == 6'd47);
|
| 601 |
|
|
assign Is_currMB_buf2 = (DF_edge_counter_MW == 6'd22 || DF_edge_counter_MW == 6'd33 ||
|
| 602 |
|
|
DF_edge_counter_MW == 6'd41);
|
| 603 |
|
|
assign Is_currMB_buf3 = (DF_edge_counter_MW == 6'd26);
|
| 604 |
|
|
assign Is_currMB_t1 = (DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd23 ||
|
| 605 |
|
|
DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd30 ||
|
| 606 |
|
|
DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd44);
|
| 607 |
|
|
|
| 608 |
|
|
reg [31:0] dis_frame_RAM_din;
|
| 609 |
|
|
always @ (disable_DF or dis_frame_RAM_wr or blk4x4_sum_counter or one_edge_counter_MW or
|
| 610 |
|
|
DF_12_cycles or Is_mbAddrA_real_wr or Is_mbAddrB_wr or Is_mbAddrB_t1 or Is_currMB_buf0 or
|
| 611 |
|
|
Is_currMB_buf2 or Is_currMB_buf3 or Is_currMB_t1 or Is_currMB_wr or
|
| 612 |
|
|
blk4x4_sum_PE0_out or blk4x4_sum_PE1_out or blk4x4_sum_PE2_out or blk4x4_sum_PE3_out or
|
| 613 |
|
|
p0_MW or p1_MW or p2_MW or p3_MW or
|
| 614 |
|
|
buf0_0 or buf0_1 or buf0_2 or buf0_3 or
|
| 615 |
|
|
buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3 or
|
| 616 |
|
|
t0_0 or t0_1 or t0_2 or t0_3 or t1_0 or t1_1 or t1_2 or t1_3)
|
| 617 |
|
|
if (disable_DF && dis_frame_RAM_wr)
|
| 618 |
|
|
begin
|
| 619 |
|
|
if (blk4x4_sum_counter[2] == 1'b0)
|
| 620 |
|
|
dis_frame_RAM_din <= {blk4x4_sum_PE3_out,blk4x4_sum_PE2_out,blk4x4_sum_PE1_out,blk4x4_sum_PE0_out};
|
| 621 |
|
|
else
|
| 622 |
|
|
dis_frame_RAM_din <= 0;
|
| 623 |
|
|
end
|
| 624 |
|
|
else if (!disable_DF && dis_frame_RAM_wr)
|
| 625 |
|
|
case ({Is_mbAddrA_real_wr,Is_mbAddrB_wr,Is_currMB_wr})
|
| 626 |
|
|
3'b100: //Is_mbAddrA_wr
|
| 627 |
|
|
dis_frame_RAM_din <= {p0_MW,p1_MW,p2_MW,p3_MW};
|
| 628 |
|
|
3'b010: //Is_mbAddrB_wr
|
| 629 |
|
|
begin
|
| 630 |
|
|
if (Is_mbAddrB_t1) //T1 -> mbAddrB
|
| 631 |
|
|
case (one_edge_counter_MW)
|
| 632 |
|
|
2'd0:dis_frame_RAM_din <= t1_0;
|
| 633 |
|
|
2'd1:dis_frame_RAM_din <= t1_1;
|
| 634 |
|
|
2'd2:dis_frame_RAM_din <= t1_2;
|
| 635 |
|
|
2'd3:dis_frame_RAM_din <= t1_3;
|
| 636 |
|
|
endcase
|
| 637 |
|
|
else //T0 -> mbAddrB
|
| 638 |
|
|
case (one_edge_counter_MW)
|
| 639 |
|
|
2'd0:dis_frame_RAM_din <= t0_0;
|
| 640 |
|
|
2'd1:dis_frame_RAM_din <= t0_1;
|
| 641 |
|
|
2'd2:dis_frame_RAM_din <= t0_2;
|
| 642 |
|
|
2'd3:dis_frame_RAM_din <= t0_3;
|
| 643 |
|
|
endcase
|
| 644 |
|
|
end
|
| 645 |
|
|
3'b001: //Is_currMB_wr
|
| 646 |
|
|
case ({Is_currMB_buf0,Is_currMB_buf2,Is_currMB_buf3,Is_currMB_t1})
|
| 647 |
|
|
4'b1000: //Is_currMB_buf0
|
| 648 |
|
|
case (one_edge_counter_MW)
|
| 649 |
|
|
2'd0:dis_frame_RAM_din <= buf0_0;
|
| 650 |
|
|
2'd1:dis_frame_RAM_din <= buf0_1;
|
| 651 |
|
|
2'd2:dis_frame_RAM_din <= buf0_2;
|
| 652 |
|
|
2'd3:dis_frame_RAM_din <= buf0_3;
|
| 653 |
|
|
endcase
|
| 654 |
|
|
4'b0100: //Is_currMB_buf2
|
| 655 |
|
|
case (one_edge_counter_MW)
|
| 656 |
|
|
2'd0:dis_frame_RAM_din <= buf2_0;
|
| 657 |
|
|
2'd1:dis_frame_RAM_din <= buf2_1;
|
| 658 |
|
|
2'd2:dis_frame_RAM_din <= buf2_2;
|
| 659 |
|
|
2'd3:dis_frame_RAM_din <= buf2_3;
|
| 660 |
|
|
endcase
|
| 661 |
|
|
4'b0010: //Is_currMB_buf3
|
| 662 |
|
|
case (one_edge_counter_MW)
|
| 663 |
|
|
2'd0:dis_frame_RAM_din <= buf3_0;
|
| 664 |
|
|
2'd1:dis_frame_RAM_din <= buf3_1;
|
| 665 |
|
|
2'd2:dis_frame_RAM_din <= buf3_2;
|
| 666 |
|
|
2'd3:dis_frame_RAM_din <= buf3_3;
|
| 667 |
|
|
endcase
|
| 668 |
|
|
4'b0001: //Is_currMB_t1
|
| 669 |
|
|
case (one_edge_counter_MW)
|
| 670 |
|
|
2'd0:dis_frame_RAM_din <= t1_0;
|
| 671 |
|
|
2'd1:dis_frame_RAM_din <= t1_1;
|
| 672 |
|
|
2'd2:dis_frame_RAM_din <= t1_2;
|
| 673 |
|
|
2'd3:dis_frame_RAM_din <= t1_3;
|
| 674 |
|
|
endcase
|
| 675 |
|
|
default: //Is_currMB_t0
|
| 676 |
|
|
case (one_edge_counter_MW)
|
| 677 |
|
|
2'd0:dis_frame_RAM_din <= t0_0;
|
| 678 |
|
|
2'd1:dis_frame_RAM_din <= t0_1;
|
| 679 |
|
|
2'd2:dis_frame_RAM_din <= t0_2;
|
| 680 |
|
|
2'd3:dis_frame_RAM_din <= t0_3;
|
| 681 |
|
|
endcase
|
| 682 |
|
|
endcase
|
| 683 |
|
|
default://additional 12 cycles
|
| 684 |
|
|
case (DF_12_cycles[3:2])
|
| 685 |
|
|
2'b00: //0 ~ 3,buf2 -> blk22
|
| 686 |
|
|
case (DF_12_cycles[1:0])
|
| 687 |
|
|
2'd0:dis_frame_RAM_din <= buf2_0;
|
| 688 |
|
|
2'd1:dis_frame_RAM_din <= buf2_1;
|
| 689 |
|
|
2'd2:dis_frame_RAM_din <= buf2_2;
|
| 690 |
|
|
2'd3:dis_frame_RAM_din <= buf2_3;
|
| 691 |
|
|
endcase
|
| 692 |
|
|
2'b01: //4 ~ 7,T0 -> blk21
|
| 693 |
|
|
case (DF_12_cycles[1:0])
|
| 694 |
|
|
2'd0:dis_frame_RAM_din <= t0_0;
|
| 695 |
|
|
2'd1:dis_frame_RAM_din <= t0_1;
|
| 696 |
|
|
2'd2:dis_frame_RAM_din <= t0_2;
|
| 697 |
|
|
2'd3:dis_frame_RAM_din <= t0_3;
|
| 698 |
|
|
endcase
|
| 699 |
|
|
default://8 ~ 11,T1 -> blk23
|
| 700 |
|
|
case (DF_12_cycles[1:0])
|
| 701 |
|
|
2'd0:dis_frame_RAM_din <= t1_0;
|
| 702 |
|
|
2'd1:dis_frame_RAM_din <= t1_1;
|
| 703 |
|
|
2'd2:dis_frame_RAM_din <= t1_2;
|
| 704 |
|
|
2'd3:dis_frame_RAM_din <= t1_3;
|
| 705 |
|
|
endcase
|
| 706 |
|
|
endcase
|
| 707 |
|
|
endcase
|
| 708 |
|
|
else
|
| 709 |
|
|
dis_frame_RAM_din <= 0;
|
| 710 |
|
|
endmodule
|
| 711 |
|
|
|
| 712 |
|
|
|
| 713 |
|
|
|
| 714 |
|
|
|
| 715 |
|
|
|
| 716 |
|
|
|
| 717 |
|
|
|
| 718 |
|
|
|
| 719 |
|
|
|
| 720 |
|
|
|
| 721 |
|
|
|
| 722 |
|
|
|
| 723 |
|
|
|
| 724 |
|
|
|
| 725 |
|
|
|
| 726 |
|
|
|
| 727 |
|
|
|
| 728 |
|
|
|
| 729 |
|
|
|
| 730 |
|
|
|
| 731 |
|
|
|
| 732 |
|
|
|
| 733 |
|
|
|
| 734 |
|
|
|
| 735 |
|
|
|
| 736 |
|
|
|
| 737 |
|
|
|
| 738 |
|
|
|
| 739 |
|
|
|
| 740 |
|
|
|
