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[/] [npigrctrl/] [tags/] [arelease/] [npi_vga_v1_00_b/] [hdl/] [vhdl/] [data_rgb.vhd] - Blame information for rev 3

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----------------------------------------------------------------------
----                                                              ----
---- Data RGBA module                                             ----
----                                                              ----
---- Author(s):                                                   ----
---- - Slavek Valach, s.valach@dspfpga.com                        ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2008 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU General          ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.0 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU General Public License for more details.----
----                                                              ----
---- You should have received a copy of the GNU General           ----
---- Public License along with this source; if not, download it   ----
---- from http://www.gnu.org/licenses/gpl.txt                     ----
----                                                              ----
----------------------------------------------------------------------
 
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-------------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
 
entity data_rgb is
Generic(
   C_FAMILY             : string  := "virtex5";
   C_VD_DATA_WIDTH      : integer := 32;
   V_CNT_SIZE           : integer := 10;
   H_CNT_SIZE           : integer := 10;
   PIXEL_WIDTH          : natural := 32;
   PIXEL_DEPTH          : integer := 6);
port (
   -- System interface      
   Sys_Rst                       : in     std_logic;                    -- System reset
   Sys_Clk                       : in     std_logic;
   NPI_CLK                       : in     std_logic;
 
   VIDEO_CLK                     : in     std_logic;                    -- LCD Clock signal
   VIDEO_DE                      : in     std_logic;
   VIDEO_EN                      : in     std_logic;
 
   VIDEO_R                       : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_G                       : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_B                       : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_A                       : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
 
   INTR                          : out    std_logic;
 
-- DMA Channel input and control
   DMA_INIT                      : in     std_logic;
   DMA_DACK                      : in     std_logic;
   DMA_DATA                      : in     std_logic_vector(C_VD_DATA_WIDTH - 1 downto 0);
   DMA_DREQ                      : out    std_logic;
   DMA_RSYNC                     : out    std_logic;
   DMA_TC                        : in     std_logic;
 
   X_0                           : out    std_logic;
   X_1                           : out    std_logic;
   X_2                           : out    std_logic;
   X_3                           : out    std_logic;
   X_4                           : out    std_logic;
   X_5                           : out    std_logic);
 
end data_rgb;
 
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of data_rgb is
 
component d_fifo
generic (
   C_FAMILY                      : string;
   C_VD_DATA_WIDTH               : integer);
port (
-- System interface      
   Sys_Clk                       : in     std_logic;                    -- Base system clock
   NPI_CLK                       : in     std_logic;
   Sys_Rst                       : in     std_logic;                    -- System reset
 
-- DMA Channel interface
--   DMA_CLK                       : in     std_logic;     -- DMA clock time domain (the asynchronous FIFO will be used)
   DMA_DREQ                      : out    std_logic;     -- Data request
   DMA_DACK                      : in     std_logic;     -- Data ack
   DMA_RSYNC                     : out    std_logic;     -- Synchronization reset (restarts the channel)
   DMA_TC                        : in     std_logic;     -- Terminal count (the signal is generated at the end of the transfer)
   DMA_DATA                      : in     std_logic_vector(C_VD_DATA_WIDTH - 1 downto 0);
 
-- User interface (the reader side)
   USER_CLK                      : in     std_logic;                    -- User clk is used as an asynchronous read clock
   USER_RST                      : in     std_logic;
   USER_DREQ                     : in     std_logic;
   USER_RD                       : in     std_logic;
   USER_DRDY                     : out    std_logic;
 
   XXX                           : out    std_logic_vector(3 downto 0);
 
   USER_DATA                     : out    std_logic_vector(31 downto 0));
end component;
 
constant VCC                     : std_logic := '1';
constant GND                     : std_logic := '0';
 
signal de_i                      : std_logic;
 
-- Fifo signals
signal dreq_i                    : std_logic;
signal dack_i                    : std_logic;
signal rsync                     : std_logic;
signal tc_i                      : std_logic;
signal data_in                   : std_logic_vector(31 downto 0);
signal user_rst                  : std_logic;
signal user_dreq                 : std_logic;
signal user_read                 : std_logic;
signal user_drdy                 : std_logic;
signal fifo_data_out             : std_logic_vector(31 downto 0);
signal fifo_init                 : std_logic;
 
signal de_cnt                    : integer range 0 to (32 / PIXEL_WIDTH) - 1;
signal de_cnt_preset             : integer range 0 to (32 / PIXEL_WIDTH) - 1;
 
signal video_d                   : std_logic_vector(PIXEL_DEPTH - 1 downto 0);
 
signal XXX                       : std_logic_vector(3 downto 0);
 
BEGIN
 
-- Fifo instance and DMA CTRL
INTR <= '0';
dack_i <= DMA_DACK;
DMA_DREQ <= dreq_i;
user_dreq <= VIDEO_EN;
rsync <= '0';
fifo_init <= (Not video_en) Or Sys_Rst Or (Not DMA_INIT);
user_rst <= Not VIDEO_EN;
de_i <= VIDEO_DE;
 
de_cnt_preset <= 0 When PIXEL_WIDTH = 32 Else
                 1 When PIXEL_WIDTH = 16 Else
                 3 When PIXEL_WIDTH = 8 Else 0;
 
PROCESS(VIDEO_CLK, Sys_Rst)
BEGIN
   If Sys_Rst = '1' Then
      de_cnt <= de_cnt_preset;
   ElsIf VIDEO_CLK'event And VIDEO_CLK = '1' Then
      If de_i = '1' Then
         If de_cnt = 0 Then
            de_cnt <= de_cnt_preset;
         Else
            de_cnt <= de_cnt - 1;
         End If;
      Else
      de_cnt <= de_cnt_preset;
      End If;
   End If;
END PROCESS;
 
user_read <= '1' When (de_i = '1') And (de_cnt = 0) And (user_drdy = '1') Else '0';
 
fifo_i : d_fifo
generic map (
   C_FAMILY                      => C_FAMILY,
   C_VD_DATA_WIDTH               => C_VD_DATA_WIDTH)
port map (
-- System interface      
   Sys_Clk                       => Sys_Clk,                    -- Base system clock
   NPI_CLK                       => NPI_CLK,
   Sys_Rst                       => fifo_init,
 
-- DMA Channel interface
   DMA_DREQ                      => dreq_i,
   DMA_DACK                      => dack_i,
   DMA_RSYNC                     => rsync,
   DMA_TC                        => tc_i,
   DMA_DATA                      => DMA_DATA,
 
-- User interface (the reader side)
   USER_CLK                      => VIDEO_CLK,
   USER_RST                      => user_rst,
   USER_DREQ                     => user_dreq,
   USER_RD                       => user_read,
   USER_DRDY                     => user_drdy,
 
   XXX                           => XXX,
 
   USER_DATA                     => fifo_data_out);
 
G_32 : If PIXEL_WIDTH = 32 Generate
   PROCESS(VIDEO_CLK)      -- 32 bits data
   BEGIN
      If VIDEO_CLK'event And VIDEO_CLK = '1' Then
         VIDEO_R <= fifo_data_out(7 downto 2);--fifo_data_out(2 to 7);
         VIDEO_G <= fifo_data_out(15 downto 10);--fifo_data_out(10 to 15);
         VIDEO_B <= fifo_data_out(23 downto 18);--fifo_data_out(18 to 23);
         VIDEO_A <= fifo_data_out(31 downto 26);--fifo_data_out(26 to 31);
      End If;
   END PROCESS;
End Generate;
 
G_16 : If PIXEL_WIDTH = 16 Generate
   PROCESS(VIDEO_CLK)    -- 16 bits data 
   BEGIN
      If VIDEO_CLK'event And VIDEO_CLK = '1' Then
         VIDEO_A <= (Others => '0');
         If de_cnt = 1 Then
            VIDEO_R <= fifo_data_out(4 downto 0) & '0';
            VIDEO_G <= fifo_data_out(9 downto 5) & '0';
            VIDEO_B <= fifo_data_out(14 downto 10) & '0';
         Else
            VIDEO_R <= fifo_data_out(20 downto 16) & '0';
            VIDEO_G <= fifo_data_out(25 downto 21) & '0';
            VIDEO_B <= fifo_data_out(30 downto 26) & '0';
         End If;
      End If;
   END PROCESS;
End Generate;
 
G_8 : If PIXEL_WIDTH = 8 Generate
   PROCESS(VIDEO_CLK)    -- 8 bits data - go through the LUT (will be added later)
   BEGIN
      If VIDEO_CLK'event And VIDEO_CLK = '1' Then
         If de_cnt = 0 Then
            video_d <= fifo_data_out(31 downto 24);
         ElsIf de_cnt = 1 Then
            video_d <= fifo_data_out(23 downto 16);
         ElsIf de_cnt = 2 Then
            video_d <= fifo_data_out(15 downto 8);
         Else
            video_d <= fifo_data_out(7 downto 0);
         End If;
      End If;
   END PROCESS;
 
   VIDEO_R <= video_d;
   VIDEO_G <= video_d;
   VIDEO_B <= video_d;
 
End Generate;
 
 
X_0 <= XXX(0);
X_1 <= XXX(1);
X_2 <= XXX(2);
X_3 <= XXX(3);
 
 
end implementation;
 

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Subversion Repositories npigrctrl

[/] [npigrctrl/] [tags/] [arelease/] [npi_vga_v1_00_b/] [hdl/] [vhdl/] [data_rgb.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	slavek	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- Data RGBA module ----`
4			`---- ----`
5			`---- Author(s): ----`
6			`---- - Slavek Valach, s.valach@dspfpga.com ----`
7			`---- ----`
8			`----------------------------------------------------------------------`
9			`---- ----`
10			`---- Copyright (C) 2008 Authors and OPENCORES.ORG ----`
11			`---- ----`
12			`---- This source file may be used and distributed without ----`
13			`---- restriction provided that this copyright statement is not ----`
14			`---- removed from the file and that any derivative work contains ----`
15			`---- the original copyright notice and the associated disclaimer. ----`
16			`---- ----`
17			`---- This source file is free software; you can redistribute it ----`
18			`---- and/or modify it under the terms of the GNU General ----`
19			`---- Public License as published by the Free Software Foundation; ----`
20			`---- either version 2.0 of the License, or (at your option) any ----`
21			`---- later version. ----`
22			`---- ----`
23			`---- This source is distributed in the hope that it will be ----`
24			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
25			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
26			`---- PURPOSE. See the GNU General Public License for more details.----`
27			`---- ----`
28			`---- You should have received a copy of the GNU General ----`
29			`---- Public License along with this source; if not, download it ----`
30			`---- from http://www.gnu.org/licenses/gpl.txt ----`
31			`---- ----`
32			`----------------------------------------------------------------------`
33
34			`library ieee;`
35			`use IEEE.STD_LOGIC_1164.ALL;`
36			`use IEEE.STD_LOGIC_ARITH.ALL;`
37			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
38
39			`-------------------------------------------------------------------------------`
40			`-- Entity section`
41			`-----------------------------------------------------------------------------`
42
43			`entity data_rgb is`
44			`Generic(`
45			`C_FAMILY : string := "virtex5";`
46			`C_VD_DATA_WIDTH : integer := 32;`
47			`V_CNT_SIZE : integer := 10;`
48			`H_CNT_SIZE : integer := 10;`
49			`PIXEL_WIDTH : natural := 32;`
50			`PIXEL_DEPTH : integer := 6);`
51			`port (`
52			`-- System interface`
53			`Sys_Rst : in std_logic; -- System reset`
54			`Sys_Clk : in std_logic;`
55			`NPI_CLK : in std_logic;`
56
57			`VIDEO_CLK : in std_logic; -- LCD Clock signal`
58			`VIDEO_DE : in std_logic;`
59			`VIDEO_EN : in std_logic;`
60
61			`VIDEO_R : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
62			`VIDEO_G : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
63			`VIDEO_B : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
64			`VIDEO_A : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
65
66			`INTR : out std_logic;`
67
68			`-- DMA Channel input and control`
69			`DMA_INIT : in std_logic;`
70			`DMA_DACK : in std_logic;`
71			`DMA_DATA : in std_logic_vector(C_VD_DATA_WIDTH - 1 downto 0);`
72			`DMA_DREQ : out std_logic;`
73			`DMA_RSYNC : out std_logic;`
74			`DMA_TC : in std_logic;`
75
76			`X_0 : out std_logic;`
77			`X_1 : out std_logic;`
78			`X_2 : out std_logic;`
79			`X_3 : out std_logic;`
80			`X_4 : out std_logic;`
81			`X_5 : out std_logic);`
82
83			`end data_rgb;`
84
85			`-----------------------------------------------------------------------------`
86			`-- Architecture section`
87			`-----------------------------------------------------------------------------`
88			`architecture implementation of data_rgb is`
89
90			`component d_fifo`
91			`generic (`
92			`C_FAMILY : string;`
93			`C_VD_DATA_WIDTH : integer);`
94			`port (`
95			`-- System interface`
96			`Sys_Clk : in std_logic; -- Base system clock`
97			`NPI_CLK : in std_logic;`
98			`Sys_Rst : in std_logic; -- System reset`
99
100			`-- DMA Channel interface`
101			`-- DMA_CLK : in std_logic; -- DMA clock time domain (the asynchronous FIFO will be used)`
102			`DMA_DREQ : out std_logic; -- Data request`
103			`DMA_DACK : in std_logic; -- Data ack`
104			`DMA_RSYNC : out std_logic; -- Synchronization reset (restarts the channel)`
105			`DMA_TC : in std_logic; -- Terminal count (the signal is generated at the end of the transfer)`
106			`DMA_DATA : in std_logic_vector(C_VD_DATA_WIDTH - 1 downto 0);`
107
108			`-- User interface (the reader side)`
109			`USER_CLK : in std_logic; -- User clk is used as an asynchronous read clock`
110			`USER_RST : in std_logic;`
111			`USER_DREQ : in std_logic;`
112			`USER_RD : in std_logic;`
113			`USER_DRDY : out std_logic;`
114
115			`XXX : out std_logic_vector(3 downto 0);`
116
117			`USER_DATA : out std_logic_vector(31 downto 0));`
118			`end component;`
119
120			`constant VCC : std_logic := '1';`
121			`constant GND : std_logic := '0';`
122
123			`signal de_i : std_logic;`
124
125			`-- Fifo signals`
126			`signal dreq_i : std_logic;`
127			`signal dack_i : std_logic;`
128			`signal rsync : std_logic;`
129			`signal tc_i : std_logic;`
130			`signal data_in : std_logic_vector(31 downto 0);`
131			`signal user_rst : std_logic;`
132			`signal user_dreq : std_logic;`
133			`signal user_read : std_logic;`
134			`signal user_drdy : std_logic;`
135			`signal fifo_data_out : std_logic_vector(31 downto 0);`
136			`signal fifo_init : std_logic;`
137
138			`signal de_cnt : integer range 0 to (32 / PIXEL_WIDTH) - 1;`
139			`signal de_cnt_preset : integer range 0 to (32 / PIXEL_WIDTH) - 1;`
140
141			`signal video_d : std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
142
143			`signal XXX : std_logic_vector(3 downto 0);`
144
145			`BEGIN`
146
147			`-- Fifo instance and DMA CTRL`
148			`INTR <= '0';`
149			`dack_i <= DMA_DACK;`
150			`DMA_DREQ <= dreq_i;`
151			`user_dreq <= VIDEO_EN;`
152			`rsync <= '0';`
153			`fifo_init <= (Not video_en) Or Sys_Rst Or (Not DMA_INIT);`
154			`user_rst <= Not VIDEO_EN;`
155			`de_i <= VIDEO_DE;`
156
157			`de_cnt_preset <= 0 When PIXEL_WIDTH = 32 Else`
158			`1 When PIXEL_WIDTH = 16 Else`
159			`3 When PIXEL_WIDTH = 8 Else 0;`
160
161			`PROCESS(VIDEO_CLK, Sys_Rst)`
162			`BEGIN`
163			`If Sys_Rst = '1' Then`
164			`de_cnt <= de_cnt_preset;`
165			`ElsIf VIDEO_CLK'event And VIDEO_CLK = '1' Then`
166			`If de_i = '1' Then`
167			`If de_cnt = 0 Then`
168			`de_cnt <= de_cnt_preset;`
169			`Else`
170			`de_cnt <= de_cnt - 1;`
171			`End If;`
172			`Else`
173			`de_cnt <= de_cnt_preset;`
174			`End If;`
175			`End If;`
176			`END PROCESS;`
177
178			`user_read <= '1' When (de_i = '1') And (de_cnt = 0) And (user_drdy = '1') Else '0';`
179
180			`fifo_i : d_fifo`
181			`generic map (`
182			`C_FAMILY => C_FAMILY,`
183			`C_VD_DATA_WIDTH => C_VD_DATA_WIDTH)`
184			`port map (`
185			`-- System interface`
186			`Sys_Clk => Sys_Clk, -- Base system clock`
187			`NPI_CLK => NPI_CLK,`
188			`Sys_Rst => fifo_init,`
189
190			`-- DMA Channel interface`
191			`DMA_DREQ => dreq_i,`
192			`DMA_DACK => dack_i,`
193			`DMA_RSYNC => rsync,`
194			`DMA_TC => tc_i,`
195			`DMA_DATA => DMA_DATA,`
196
197			`-- User interface (the reader side)`
198			`USER_CLK => VIDEO_CLK,`
199			`USER_RST => user_rst,`
200			`USER_DREQ => user_dreq,`
201			`USER_RD => user_read,`
202			`USER_DRDY => user_drdy,`
203
204			`XXX => XXX,`
205
206			`USER_DATA => fifo_data_out);`
207
208			`G_32 : If PIXEL_WIDTH = 32 Generate`
209			`PROCESS(VIDEO_CLK) -- 32 bits data`
210			`BEGIN`
211			`If VIDEO_CLK'event And VIDEO_CLK = '1' Then`
212			`VIDEO_R <= fifo_data_out(7 downto 2);--fifo_data_out(2 to 7);`
213			`VIDEO_G <= fifo_data_out(15 downto 10);--fifo_data_out(10 to 15);`
214			`VIDEO_B <= fifo_data_out(23 downto 18);--fifo_data_out(18 to 23);`
215			`VIDEO_A <= fifo_data_out(31 downto 26);--fifo_data_out(26 to 31);`
216			`End If;`
217			`END PROCESS;`
218			`End Generate;`
219
220			`G_16 : If PIXEL_WIDTH = 16 Generate`
221			`PROCESS(VIDEO_CLK) -- 16 bits data`
222			`BEGIN`
223			`If VIDEO_CLK'event And VIDEO_CLK = '1' Then`
224			`VIDEO_A <= (Others => '0');`
225			`If de_cnt = 1 Then`
226			`VIDEO_R <= fifo_data_out(4 downto 0) & '0';`
227			`VIDEO_G <= fifo_data_out(9 downto 5) & '0';`
228			`VIDEO_B <= fifo_data_out(14 downto 10) & '0';`
229			`Else`
230			`VIDEO_R <= fifo_data_out(20 downto 16) & '0';`
231			`VIDEO_G <= fifo_data_out(25 downto 21) & '0';`
232			`VIDEO_B <= fifo_data_out(30 downto 26) & '0';`
233			`End If;`
234			`End If;`
235			`END PROCESS;`
236			`End Generate;`
237
238			`G_8 : If PIXEL_WIDTH = 8 Generate`
239			`PROCESS(VIDEO_CLK) -- 8 bits data - go through the LUT (will be added later)`
240			`BEGIN`
241			`If VIDEO_CLK'event And VIDEO_CLK = '1' Then`
242			`If de_cnt = 0 Then`
243			`video_d <= fifo_data_out(31 downto 24);`
244			`ElsIf de_cnt = 1 Then`
245			`video_d <= fifo_data_out(23 downto 16);`
246			`ElsIf de_cnt = 2 Then`
247			`video_d <= fifo_data_out(15 downto 8);`
248			`Else`
249			`video_d <= fifo_data_out(7 downto 0);`
250			`End If;`
251			`End If;`
252			`END PROCESS;`
253
254			`VIDEO_R <= video_d;`
255			`VIDEO_G <= video_d;`
256			`VIDEO_B <= video_d;`
257
258			`End Generate;`
259
260
261			`X_0 <= XXX(0);`
262			`X_1 <= XXX(1);`
263			`X_2 <= XXX(2);`
264			`X_3 <= XXX(3);`
265
266
267			`end implementation;`
268