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slavek |
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---- ----
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---- fifo wrapper ----
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---- ----
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---- Author(s): ----
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---- - Slavek Valach, s.valach@dspfpga.com ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2008 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.0 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU General Public License for more details.----
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---- ----
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---- You should have received a copy of the GNU General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/gpl.txt ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-------------------------------------------------------------------------------
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-- Entity section
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-----------------------------------------------------------------------------
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entity d_fifo is
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generic (
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C_VD_DATA_WIDTH : integer := 64;
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C_FAMILY : string := "virtex5");
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port (
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-- System interface
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Sys_Clk : in std_logic; -- Base system clock
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NPI_CLK : in std_logic;
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Sys_Rst : in std_logic; -- System reset
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-- DMA Channel interface
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-- DMA_CLK : in std_logic; -- DMA clock time domain (the asynchronous FIFO will be used)
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DMA_DREQ : out std_logic; -- Data request
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DMA_DACK : in std_logic; -- Data ack
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DMA_RSYNC : out std_logic; -- Synchronization reset (restarts the channel)
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DMA_TC : in std_logic; -- Terminal count (the signal is generated at the end of the transfer)
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DMA_DATA : in std_logic_vector(C_VD_DATA_WIDTH - 1 downto 0);
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-- User interface (the reader side)
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USER_CLK : in std_logic; -- User clk is used as an asynchronous read clock
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USER_RST : in std_logic;
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USER_DREQ : in std_logic;
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USER_RD : in std_logic;
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USER_DRDY : out std_logic;
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XXX : out std_logic_vector(3 downto 0);
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USER_DATA : out std_logic_vector(31 downto 0));
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end d_fifo;
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-----------------------------------------------------------------------------
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-- Architecture section
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-----------------------------------------------------------------------------
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architecture implementation of d_fifo is
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component fifo_sp_64
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port (
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din : in std_logic_vector(63 downto 0);
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rd_clk : in std_logic;
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rd_en : in std_logic;
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rst : in std_logic;
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wr_clk : in std_logic;
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wr_en : in std_logic;
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dout : out std_logic_vector(31 downto 0);
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empty : out std_logic;
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full : out std_logic;
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prog_empty : out std_logic;
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prog_full : out std_logic);
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end component;
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component fifo_v4_64
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port (
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din : in std_logic_vector(63 downto 0);
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rd_clk : in std_logic;
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rd_en : in std_logic;
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rst : in std_logic;
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wr_clk : in std_logic;
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wr_en : in std_logic;
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dout : out std_logic_vector(31 downto 0);
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empty : out std_logic;
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full : out std_logic;
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prog_empty : out std_logic;
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prog_full : out std_logic);
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end component;
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component fifo_v5_64
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port (
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din : in std_logic_vector(63 downto 0);
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rd_clk : in std_logic;
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rd_en : in std_logic;
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rst : in std_logic;
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wr_clk : in std_logic;
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wr_en : in std_logic;
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dout : out std_logic_vector(31 downto 0);
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empty : out std_logic;
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full : out std_logic;
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prog_empty : out std_logic;
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prog_full : out std_logic);
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end component;
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component fifo_sp_32
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port (
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din : in std_logic_vector(31 downto 0);
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rd_clk : in std_logic;
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rd_en : in std_logic;
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rst : in std_logic;
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wr_clk : in std_logic;
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wr_en : in std_logic;
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dout : out std_logic_vector(31 downto 0);
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empty : out std_logic;
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full : out std_logic;
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prog_empty : out std_logic;
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prog_full : out std_logic);
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end component;
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component fifo_v4_32
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port (
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din : in std_logic_vector(31 downto 0);
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rd_clk : in std_logic;
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rd_en : in std_logic;
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rst : in std_logic;
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wr_clk : in std_logic;
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wr_en : in std_logic;
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dout : out std_logic_vector(31 downto 0);
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empty : out std_logic;
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full : out std_logic;
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prog_empty : out std_logic;
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prog_full : out std_logic);
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end component;
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component fifo_v5_32
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port (
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din : in std_logic_vector(31 downto 0);
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rd_clk : in std_logic;
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rd_en : in std_logic;
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rst : in std_logic;
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wr_clk : in std_logic;
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wr_en : in std_logic;
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dout : out std_logic_vector(31 downto 0);
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empty : out std_logic;
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full : out std_logic;
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prog_empty : out std_logic;
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prog_full : out std_logic);
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end component;
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constant low : std_logic := '0';
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constant high : std_logic := '1';
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signal fifo_prog_full : std_logic;
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signal fifo_rst : std_logic;
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signal fifo_prog_empty : std_logic;
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signal fifo_data_out : std_logic_vector(31 downto 0);
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signal fifo_full : std_logic;
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signal fifo_empty : std_logic;
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signal fifo_wr_en : std_logic;
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begin -- architecture IMP
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DMA_DREQ <= '1' When (USER_DREQ = '1') And (fifo_prog_full = '0') Else '0';
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fifo_rst <= '1' When (Sys_Rst = '1') Or (USER_RST = '1') Else '0';
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USER_DRDY <= Not fifo_prog_empty;
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fifo_wr_en <= '1' When DMA_DACK = '1' And Sys_Rst = '0' Else '0';
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gen_sp : if (C_FAMILY = "spartan3e") Or (C_FAMILY = "spartan3a") generate
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sp_fw_64 : If C_VD_DATA_WIDTH = 64 generate
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data_fifo : fifo_sp_64
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port map (
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din => DMA_DATA,
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rd_clk => User_Clk,
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rd_en => USER_RD,
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rst => fifo_rst,
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wr_clk => NPI_CLK,
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wr_en => fifo_wr_en,--DMA_DACK,
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dout => fifo_data_out,
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empty => fifo_empty,
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full => fifo_full,
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prog_empty => fifo_prog_empty,
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prog_full => fifo_prog_full);
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End Generate;
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sp_fw_32 : If C_VD_DATA_WIDTH = 32 generate
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data_fifo : fifo_sp_32
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port map (
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din => DMA_DATA,
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rd_clk => User_Clk,
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rd_en => USER_RD,
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rst => fifo_rst,
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wr_clk => NPI_CLK,
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wr_en => fifo_wr_en,--DMA_DACK,
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dout => fifo_data_out,
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empty => fifo_empty,
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full => fifo_full,
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prog_empty => fifo_prog_empty,
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prog_full => fifo_prog_full);
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End Generate;
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End Generate;
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gen_v4 : if (C_FAMILY = "virtex4") generate
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v4_fw_64 : If C_VD_DATA_WIDTH = 64 generate
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data_fifo : fifo_v4_64
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port map (
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din => DMA_DATA,
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rd_clk => User_Clk,
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rd_en => USER_RD,
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rst => fifo_rst,
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wr_clk => NPI_CLK,
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wr_en => fifo_wr_en,--DMA_DACK,
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dout => fifo_data_out,
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empty => fifo_empty,
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full => fifo_full,
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prog_empty => fifo_prog_empty,
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prog_full => fifo_prog_full);
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End Generate;
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v4_fw_32 : If C_VD_DATA_WIDTH = 32 generate
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data_fifo : fifo_v4_32
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port map (
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din => DMA_DATA,
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rd_clk => User_Clk,
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rd_en => USER_RD,
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rst => fifo_rst,
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wr_clk => NPI_CLK,
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wr_en => fifo_wr_en,--DMA_DACK,
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dout => fifo_data_out,
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empty => fifo_empty,
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full => fifo_full,
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prog_empty => fifo_prog_empty,
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prog_full => fifo_prog_full);
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End Generate;
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End Generate;
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gen_v5 : if (C_FAMILY = "virtex5") generate
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v5_fw_64 : If C_VD_DATA_WIDTH = 64 generate
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data_fifo : fifo_v5_64
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port map (
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din => DMA_DATA,
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rd_clk => User_Clk,
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rd_en => USER_RD,
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rst => fifo_rst,
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wr_clk => NPI_CLK,
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wr_en => fifo_wr_en,--DMA_DACK,
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dout => fifo_data_out,
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empty => fifo_empty,
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full => fifo_full,
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prog_empty => fifo_prog_empty,
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prog_full => fifo_prog_full);
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End Generate;
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v5_fw_32 : If C_VD_DATA_WIDTH = 32 generate
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data_fifo : fifo_v5_32
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port map (
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din => DMA_DATA,
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rd_clk => User_Clk,
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rd_en => USER_RD,
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rst => fifo_rst,
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wr_clk => NPI_CLK,
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wr_en => fifo_wr_en,--DMA_DACK,
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dout => fifo_data_out,
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empty => fifo_empty,
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full => fifo_full,
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prog_empty => fifo_prog_empty,
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prog_full => fifo_prog_full);
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End Generate;
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End Generate;
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USER_DATA <= fifo_data_out;
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XXX <= fifo_rst & fifo_prog_full & fifo_full & fifo_empty;
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end implementation;
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