URL https://opencores.org/ocsvn/npigrctrl/npigrctrl/trunk

Subversion Repositories npigrctrl

[/] [npigrctrl/] [tags/] [arelease/] [npi_vga_v1_00_b/] [hdl/] [vhdl/] [graphics.vhd] - Blame information for rev 5

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----------------------------------------------------------------------
----                                                              ----
---- Main Graphics controller                                     ----
----                                                              ----
---- Author(s):                                                   ----
---- - Slavek Valach, s.valach@dspfpga.com                        ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2008 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU General          ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.0 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU General Public License for more details.----
----                                                              ----
---- You should have received a copy of the GNU General           ----
---- Public License along with this source; if not, download it   ----
---- from http://www.gnu.org/licenses/gpl.txt                     ----
----                                                              ----
----------------------------------------------------------------------
 
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-------------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
 
entity graphic is
Generic(
   C_FAMILY                : string := "virtex5";
   C_VD_DATA_WIDTH         : integer := 64;
   PIXEL_DEPTH             : integer := 6;
   PIXEL_WIDTH             : natural := 32;
 
   C_VD_V_POL              : std_logic := '0';
   C_VCNT_SIZE             : natural := 10;
   C_VBACK_PORCH           : natural := 25+8;
   C_VFRONT_PORCH          : natural := 2+8;
   C_VVIDEO_ACTIVE         : natural := 480;
   C_VSYNC_PULSE           : natural := 2;
 
   C_VD_H_POL              : std_logic := '0';
   C_HCNT_SIZE             : natural := 10;
   C_HBACK_PORCH           : natural := 40+8;
   C_HFRONT_PORCH          : natural := 8+8+31;
   C_HVIDEO_ACTIVE         : natural := 640;
   C_HSYNC_PULSE           : natural := 96);
 
port (
   -- System interface      
   Sys_Clk                 : in     std_logic;                    -- Base system clock
   NPI_CLK                 : in     std_logic;
   Sys_Rst                 : in     std_logic;                    -- System reset
 
   VIDEO_CLK               : in     std_logic;                    -- LCD Clock signal
 
   VIDEO_VSYNC             : out    std_logic;
   VIDEO_HSYNC             : out    std_logic;
   VIDEO_DE                : out    std_logic;
   VIDEO_CLK_OUT           : out    std_logic;
   VIDEO_R                 : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_G                 : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_B                 : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   INTR                    : out    std_logic;
 
   DMA_INIT                : in     std_logic;
   DMA_DACK                : in     std_logic;
   DMA_DATA                : in     std_logic_vector(C_VD_DATA_WIDTH - 1 downto 0);
   DMA_DREQ                : out    std_logic;
   DMA_RSYNC               : out    std_logic;
   DMA_TC                  : in     std_logic;
 
   GR_DATA_I               : in     std_logic_vector(31 downto 0);
   GR_DATA_O               : out    std_logic_vector(31 downto 0);
   GR_ADDR                 : in     std_logic_vector(15 downto 0);
   GR_RNW                  : in     std_logic;
   GR_CS                   : in     std_logic;
 
   X                       : out    std_logic_vector(7 downto 0));
end graphic;
 
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of graphic is
 
component video_ctrl is
Generic(
 
   C_FAMILY             : string;
   PIXEL_DEPTH          : integer;
 
   C_VCNT_SIZE          : natural;
   C_VBACK_PORCH        : natural;
   C_VFRONT_PORCH       : natural;
   C_VVIDEO_ACTIVE      : natural;
   C_VSYNC_PULSE        : natural;
 
   C_HCNT_SIZE          : natural;
   C_HBACK_PORCH        : natural;
   C_HFRONT_PORCH       : natural;
   C_HVIDEO_ACTIVE      : natural;
   C_HSYNC_PULSE        : natural);
port (
   -- System interface      
   Sys_Rst                       : in     std_logic;                    -- System reset
 
   VSYNC_POL                     : in     std_logic;
   HSYNC_POL                     : in     std_logic;
   DE_POL                        : in     std_logic;
 
   X_HSYNC_DELAY                 : in     std_logic_vector(3 downto 0);
   X_VSYNC_DELAY                 : in     std_logic_vector(3 downto 0);
   X_DE_DELAY                    : in     std_logic_vector(3 downto 0);
 
   VSYNC                         : out    std_logic;
   HSYNC                         : out    std_logic;
   DE                            : out    std_logic;
   VSYNC_VALUE                   : out    std_logic_vector(C_VCNT_SIZE - 1 downto 0);
   HSYNC_VALUE                   : out    std_logic_vector(C_HCNT_SIZE - 1 downto 0);
   LAST_LINE                     : out    std_logic;
   FRAME_END                     : out    std_logic;
 
   VIDEO_EN                      : in     std_logic;
   VIDEO_DATA_R                  : in     std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_DATA_G                  : in     std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_DATA_B                  : in     std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_CLK_IN                  : in     std_logic;                    -- LCD Clock signal
   VIDEO_VSYNC                   : out    std_logic;
   VIDEO_HSYNC                   : out    std_logic;
   VIDEO_DE                      : out    std_logic;
   VIDEO_CLK_OUT                 : out    std_logic;
   VIDEO_R                       : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_G                       : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_B                       : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
 
   X_0                           : out    std_logic;
   X_1                           : out    std_logic;
   X_2                           : out    std_logic;
   X_3                           : out    std_logic;
   X_4                           : out    std_logic;
   X_5                           : out    std_logic);
 
end component;
 
component data_rgb is
Generic(
   C_FAMILY                      : string;
   C_VD_DATA_WIDTH               : integer;
   V_CNT_SIZE                    : integer;
   H_CNT_SIZE                    : integer;
   PIXEL_WIDTH                   : natural;
   PIXEL_DEPTH                   : integer);
port (
   -- System interface      
   Sys_Rst                       : in     std_logic;                    -- System reset
   NPI_CLK                       : in     std_logic;
   Sys_Clk                       : in     std_logic;
   VIDEO_CLK                     : in     std_logic;                    -- LCD Clock signal
   VIDEO_DE                      : in     std_logic;
   VIDEO_EN                      : in     std_logic;
 
   VIDEO_R                       : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_G                       : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_B                       : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_A                       : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
 
   INTR                          : out    std_logic;
 
-- DMA Channel input and control
   DMA_INIT                      : in     std_logic;
   DMA_DACK                      : in     std_logic;
   DMA_DATA                      : in     std_logic_vector(C_VD_DATA_WIDTH - 1 downto 0);
   DMA_DREQ                      : out    std_logic;
   DMA_RSYNC                     : out    std_logic;
   DMA_TC                        : in     std_logic;
 
   X_0                           : out    std_logic;
   X_1                           : out    std_logic;
   X_2                           : out    std_logic;
   X_3                           : out    std_logic;
   X_4                           : out    std_logic;
   X_5                           : out    std_logic);
end component;
 
 
constant VCC                     : std_logic := '1';
constant GND                     : std_logic := '0';
 
signal line_e_i                  : std_logic;
 
signal frame_end                 : std_logic;
 
signal lcd_en_i                  : std_logic;
 
signal vsync_value               : std_logic_vector(C_VCNT_SIZE - 1 downto 0);
signal hsync_value               : std_logic_vector(C_HCNT_SIZE - 1 downto 0);
signal hsync_i                   : std_logic;
signal vsync_i                   : std_logic;
signal de_i                      : std_logic;
 
-- OPB signals section
 
signal video_data_in             : std_logic_vector((3 * PIXEL_DEPTH) - 1 downto 0);
 
signal x_hsync_delay             : std_logic_vector(3 downto 0);
signal x_vsync_delay             : std_logic_vector(3 downto 0);
signal x_de_delay                : std_logic_vector(3 downto 0);
 
signal row_position              : std_logic_vector(C_VCNT_SIZE - 1 downto 0);
signal col_position              : std_logic_vector(C_HCNT_SIZE - 1 downto 0);
 
signal last_line                 : std_logic;
signal video_en                  : std_logic;
 
signal video_en_video_clk        : std_logic;
signal video_en_i_video_clk      : std_logic;
signal video_en_p_video_clk      : std_logic;
 
-- Service signals
signal V_CTRL_X0                 : std_logic;
signal V_CTRL_X1                 : std_logic;
signal V_CTRL_X2                 : std_logic;
signal V_CTRL_X3                 : std_logic;
signal V_CTRL_X4                 : std_logic;
signal V_CTRL_X5                 : std_logic;
 
-- Fifo signals
signal dreq_i                    : std_logic;
signal dack_i                    : std_logic;
signal rsync                     : std_logic;
signal tc_i                      : std_logic;
signal data_in                   : std_logic_vector(31 downto 0);
signal user_rst                  : std_logic;
signal fifo_data_out             : std_logic_vector(31 downto 0);
signal fifo_init                 : std_logic;
 
signal ch0_r                     : std_logic_vector(PIXEL_DEPTH - 1 downto 0);
signal ch0_g                     : std_logic_vector(PIXEL_DEPTH - 1 downto 0);
signal ch0_b                     : std_logic_vector(PIXEL_DEPTH - 1 downto 0);
signal ch0_a                     : std_logic_vector(PIXEL_DEPTH - 1 downto 0);
signal ch0_int                   : std_logic;
 
-- Control Registers and bit aliases
signal video_ctrl_reg            : std_logic_vector(31 downto 0) := (Others => '0');
 
signal xxx                       : std_logic_vector(3 downto 0);
signal xxx_1                     : std_logic_vector(3 downto 0);
 
signal ctrl_data                 : std_logic_vector(31 downto 0);
signal ctrl_addr                 : std_logic_vector(31 downto 0);
signal ctrl_wr                   : std_logic;
 
signal delay_cnt                 : std_logic_vector(20 downto 0);
signal video_en_e                : std_logic;
 
BEGIN
 
-- Fifo instance and DMA CTRL
 
user_rst <= Not video_en_video_clk;
--user_read <= '0';
 
CH0_FIFO_I : data_rgb
Generic map (
   C_FAMILY                      => C_FAMILY,
   C_VD_DATA_WIDTH               => C_VD_DATA_WIDTH,
   V_CNT_SIZE                    => C_VCNT_SIZE,
   H_CNT_SIZE                    => C_HCNT_SIZE,
   PIXEL_WIDTH                   => PIXEL_WIDTH,
   PIXEL_DEPTH                   => PIXEL_DEPTH)
port map (
   -- System interface      
   Sys_Rst                       => Sys_Rst,
   NPI_CLK                       => NPI_CLK,
 
   Sys_Clk                       => Sys_Clk,
   VIDEO_CLK                     => VIDEO_CLK,
   VIDEO_DE                      => de_i,
   VIDEO_EN                      => video_en_video_clk,
 
   VIDEO_R                       => ch0_r,
   VIDEO_G                       => ch0_g,
   VIDEO_B                       => ch0_b,
   VIDEO_A                       => ch0_a,
 
   INTR                          => ch0_int,
 
   DMA_INIT                      => DMA_INIT,
   DMA_DACK                      => DMA_DACK,
   DMA_DATA                      => DMA_DATA,
   DMA_DREQ                      => DMA_DREQ,
   DMA_RSYNC                     => DMA_RSYNC,
   DMA_TC                        => DMA_TC,
 
   X_0                           => open,
   X_1                           => open,
   X_2                           => open,
   X_3                           => open,
   X_4                           => open,
   X_5                           => open);
 
x_hsync_delay <= conv_std_logic_vector(2, x_hsync_delay'length);
x_vsync_delay <= conv_std_logic_vector(2, x_vsync_delay'length);
x_de_delay <= conv_std_logic_vector(0, x_de_delay'length);
 
-- Video CTRL instance
 
PROCESS(sys_clk)
BEGIN
   If Sys_Rst = '1' Then
      delay_cnt <= (others => '1');
   ElsIf sys_clk'event And sys_clk = '1' Then
      If DMA_INIT = '0' Then
         delay_cnt <= (others => '1');
      ElsIf delay_cnt > 0 Then
         delay_cnt <= delay_cnt - 1;
      End If;
   video_en <= video_en_e;
   End If;
END PROCESS;
 
video_en_e <= '1' When delay_cnt = 0 Else '0'; --video_ctrl_reg(0);
 
res_video_en : entity work.resample_r
port map(
   Clk   => VIDEO_CLK,
   Rst   => Sys_Rst,
   D_i   => video_en,
   D_o   => video_en_video_clk);
 
video_ctrl_i : video_ctrl
generic map (
   C_FAMILY                   => C_FAMILY,
   PIXEL_DEPTH                => PIXEL_DEPTH,
 
   C_VCNT_SIZE                => C_VCNT_SIZE,
   C_VBACK_PORCH              => C_VBACK_PORCH,
   C_VFRONT_PORCH             => C_VFRONT_PORCH,
   C_VVIDEO_ACTIVE            => C_VVIDEO_ACTIVE,
   C_VSYNC_PULSE              => C_VSYNC_PULSE,
 
   C_HCNT_SIZE                => C_HCNT_SIZE,
   C_HBACK_PORCH              => C_HBACK_PORCH,
   C_HFRONT_PORCH             => C_HFRONT_PORCH,
   C_HVIDEO_ACTIVE            => C_HVIDEO_ACTIVE,
   C_HSYNC_PULSE              => C_HSYNC_PULSE)
 
port map (
   -- System interface      
   Sys_Rst                       => SYS_RST,                    -- System reset
 
   VSYNC_POL                     => C_VD_V_POL,
   HSYNC_POL                     => C_VD_H_POL,
   DE_POL                        => VCC,
 
   X_HSYNC_DELAY                 => x_hsync_delay,
   X_VSYNC_DELAY                 => x_vsync_delay,
   X_DE_DELAY                    => x_de_delay,
 
   VSYNC                         => vsync_i,
   HSYNC                         => hsync_i,
   DE                            => de_i,
   VSYNC_VALUE                   => row_position,
   HSYNC_VALUE                   => col_position,
   LAST_LINE                     => last_line,
   FRAME_END                     => frame_end,
 
   VIDEO_EN                      => video_en_video_clk,
   VIDEO_DATA_R                  => ch0_r,
   VIDEO_DATA_G                  => ch0_g,
   VIDEO_DATA_B                  => ch0_b,
   VIDEO_CLK_IN                  => VIDEO_CLK,
   VIDEO_VSYNC                   => VIDEO_VSYNC,
   VIDEO_HSYNC                   => VIDEO_HSYNC,
   VIDEO_DE                      => VIDEO_DE,
   VIDEO_CLK_OUT                 => VIDEO_CLK_OUT,
   VIDEO_R                       => VIDEO_R,
   VIDEO_G                       => VIDEO_G,
   VIDEO_B                       => VIDEO_B,
 
   X_0                           => V_CTRL_X0,
   X_1                           => V_CTRL_X1,
   X_2                           => V_CTRL_X2,
   X_3                           => V_CTRL_X3,
   X_4                           => V_CTRL_X4,
   X_5                           => V_CTRL_X5);
 
 
end implementation;
 

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Subversion Repositories npigrctrl

[/] [npigrctrl/] [tags/] [arelease/] [npi_vga_v1_00_b/] [hdl/] [vhdl/] [graphics.vhd] - Blame information for rev 5

Line No.	Rev	Author	Line
1	2	slavek	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- Main Graphics controller ----`
4			`---- ----`
5			`---- Author(s): ----`
6			`---- - Slavek Valach, s.valach@dspfpga.com ----`
7			`---- ----`
8			`----------------------------------------------------------------------`
9			`---- ----`
10			`---- Copyright (C) 2008 Authors and OPENCORES.ORG ----`
11			`---- ----`
12			`---- This source file may be used and distributed without ----`
13			`---- restriction provided that this copyright statement is not ----`
14			`---- removed from the file and that any derivative work contains ----`
15			`---- the original copyright notice and the associated disclaimer. ----`
16			`---- ----`
17			`---- This source file is free software; you can redistribute it ----`
18			`---- and/or modify it under the terms of the GNU General ----`
19			`---- Public License as published by the Free Software Foundation; ----`
20			`---- either version 2.0 of the License, or (at your option) any ----`
21			`---- later version. ----`
22			`---- ----`
23			`---- This source is distributed in the hope that it will be ----`
24			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
25			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
26			`---- PURPOSE. See the GNU General Public License for more details.----`
27			`---- ----`
28			`---- You should have received a copy of the GNU General ----`
29			`---- Public License along with this source; if not, download it ----`
30			`---- from http://www.gnu.org/licenses/gpl.txt ----`
31			`---- ----`
32			`----------------------------------------------------------------------`
33
34			`library ieee;`
35			`use IEEE.STD_LOGIC_1164.ALL;`
36			`use IEEE.STD_LOGIC_ARITH.ALL;`
37			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
38
39			`-------------------------------------------------------------------------------`
40			`-- Entity section`
41			`-----------------------------------------------------------------------------`
42
43			`entity graphic is`
44			`Generic(`
45			`C_FAMILY : string := "virtex5";`
46			`C_VD_DATA_WIDTH : integer := 64;`
47			`PIXEL_DEPTH : integer := 6;`
48			`PIXEL_WIDTH : natural := 32;`
49
50			`C_VD_V_POL : std_logic := '0';`
51			`C_VCNT_SIZE : natural := 10;`
52			`C_VBACK_PORCH : natural := 25+8;`
53			`C_VFRONT_PORCH : natural := 2+8;`
54			`C_VVIDEO_ACTIVE : natural := 480;`
55			`C_VSYNC_PULSE : natural := 2;`
56
57			`C_VD_H_POL : std_logic := '0';`
58			`C_HCNT_SIZE : natural := 10;`
59			`C_HBACK_PORCH : natural := 40+8;`
60			`C_HFRONT_PORCH : natural := 8+8+31;`
61			`C_HVIDEO_ACTIVE : natural := 640;`
62			`C_HSYNC_PULSE : natural := 96);`
63
64			`port (`
65			`-- System interface`
66			`Sys_Clk : in std_logic; -- Base system clock`
67			`NPI_CLK : in std_logic;`
68			`Sys_Rst : in std_logic; -- System reset`
69
70			`VIDEO_CLK : in std_logic; -- LCD Clock signal`
71
72			`VIDEO_VSYNC : out std_logic;`
73			`VIDEO_HSYNC : out std_logic;`
74			`VIDEO_DE : out std_logic;`
75			`VIDEO_CLK_OUT : out std_logic;`
76			`VIDEO_R : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
77			`VIDEO_G : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
78			`VIDEO_B : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
79			`INTR : out std_logic;`
80
81			`DMA_INIT : in std_logic;`
82			`DMA_DACK : in std_logic;`
83			`DMA_DATA : in std_logic_vector(C_VD_DATA_WIDTH - 1 downto 0);`
84			`DMA_DREQ : out std_logic;`
85			`DMA_RSYNC : out std_logic;`
86			`DMA_TC : in std_logic;`
87
88			`GR_DATA_I : in std_logic_vector(31 downto 0);`
89			`GR_DATA_O : out std_logic_vector(31 downto 0);`
90			`GR_ADDR : in std_logic_vector(15 downto 0);`
91			`GR_RNW : in std_logic;`
92			`GR_CS : in std_logic;`
93
94			`X : out std_logic_vector(7 downto 0));`
95			`end graphic;`
96
97			`-----------------------------------------------------------------------------`
98			`-- Architecture section`
99			`-----------------------------------------------------------------------------`
100			`architecture implementation of graphic is`
101
102			`component video_ctrl is`
103			`Generic(`
104
105			`C_FAMILY : string;`
106			`PIXEL_DEPTH : integer;`
107
108			`C_VCNT_SIZE : natural;`
109			`C_VBACK_PORCH : natural;`
110			`C_VFRONT_PORCH : natural;`
111			`C_VVIDEO_ACTIVE : natural;`
112			`C_VSYNC_PULSE : natural;`
113
114			`C_HCNT_SIZE : natural;`
115			`C_HBACK_PORCH : natural;`
116			`C_HFRONT_PORCH : natural;`
117			`C_HVIDEO_ACTIVE : natural;`
118			`C_HSYNC_PULSE : natural);`
119			`port (`
120			`-- System interface`
121			`Sys_Rst : in std_logic; -- System reset`
122
123			`VSYNC_POL : in std_logic;`
124			`HSYNC_POL : in std_logic;`
125			`DE_POL : in std_logic;`
126
127			`X_HSYNC_DELAY : in std_logic_vector(3 downto 0);`
128			`X_VSYNC_DELAY : in std_logic_vector(3 downto 0);`
129			`X_DE_DELAY : in std_logic_vector(3 downto 0);`
130
131			`VSYNC : out std_logic;`
132			`HSYNC : out std_logic;`
133			`DE : out std_logic;`
134			`VSYNC_VALUE : out std_logic_vector(C_VCNT_SIZE - 1 downto 0);`
135			`HSYNC_VALUE : out std_logic_vector(C_HCNT_SIZE - 1 downto 0);`
136			`LAST_LINE : out std_logic;`
137			`FRAME_END : out std_logic;`
138
139			`VIDEO_EN : in std_logic;`
140			`VIDEO_DATA_R : in std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
141			`VIDEO_DATA_G : in std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
142			`VIDEO_DATA_B : in std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
143			`VIDEO_CLK_IN : in std_logic; -- LCD Clock signal`
144			`VIDEO_VSYNC : out std_logic;`
145			`VIDEO_HSYNC : out std_logic;`
146			`VIDEO_DE : out std_logic;`
147			`VIDEO_CLK_OUT : out std_logic;`
148			`VIDEO_R : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
149			`VIDEO_G : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
150			`VIDEO_B : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
151
152			`X_0 : out std_logic;`
153			`X_1 : out std_logic;`
154			`X_2 : out std_logic;`
155			`X_3 : out std_logic;`
156			`X_4 : out std_logic;`
157			`X_5 : out std_logic);`
158
159			`end component;`
160
161			`component data_rgb is`
162			`Generic(`
163			`C_FAMILY : string;`
164			`C_VD_DATA_WIDTH : integer;`
165			`V_CNT_SIZE : integer;`
166			`H_CNT_SIZE : integer;`
167			`PIXEL_WIDTH : natural;`
168			`PIXEL_DEPTH : integer);`
169			`port (`
170			`-- System interface`
171			`Sys_Rst : in std_logic; -- System reset`
172			`NPI_CLK : in std_logic;`
173			`Sys_Clk : in std_logic;`
174			`VIDEO_CLK : in std_logic; -- LCD Clock signal`
175			`VIDEO_DE : in std_logic;`
176			`VIDEO_EN : in std_logic;`
177
178			`VIDEO_R : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
179			`VIDEO_G : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
180			`VIDEO_B : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
181			`VIDEO_A : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
182
183			`INTR : out std_logic;`
184
185			`-- DMA Channel input and control`
186			`DMA_INIT : in std_logic;`
187			`DMA_DACK : in std_logic;`
188			`DMA_DATA : in std_logic_vector(C_VD_DATA_WIDTH - 1 downto 0);`
189			`DMA_DREQ : out std_logic;`
190			`DMA_RSYNC : out std_logic;`
191			`DMA_TC : in std_logic;`
192
193			`X_0 : out std_logic;`
194			`X_1 : out std_logic;`
195			`X_2 : out std_logic;`
196			`X_3 : out std_logic;`
197			`X_4 : out std_logic;`
198			`X_5 : out std_logic);`
199			`end component;`
200
201
202			`constant VCC : std_logic := '1';`
203			`constant GND : std_logic := '0';`
204
205			`signal line_e_i : std_logic;`
206
207			`signal frame_end : std_logic;`
208
209			`signal lcd_en_i : std_logic;`
210
211			`signal vsync_value : std_logic_vector(C_VCNT_SIZE - 1 downto 0);`
212			`signal hsync_value : std_logic_vector(C_HCNT_SIZE - 1 downto 0);`
213			`signal hsync_i : std_logic;`
214			`signal vsync_i : std_logic;`
215			`signal de_i : std_logic;`
216
217			`-- OPB signals section`
218
219			`signal video_data_in : std_logic_vector((3 * PIXEL_DEPTH) - 1 downto 0);`
220
221			`signal x_hsync_delay : std_logic_vector(3 downto 0);`
222			`signal x_vsync_delay : std_logic_vector(3 downto 0);`
223			`signal x_de_delay : std_logic_vector(3 downto 0);`
224
225			`signal row_position : std_logic_vector(C_VCNT_SIZE - 1 downto 0);`
226			`signal col_position : std_logic_vector(C_HCNT_SIZE - 1 downto 0);`
227
228			`signal last_line : std_logic;`
229			`signal video_en : std_logic;`
230
231			`signal video_en_video_clk : std_logic;`
232			`signal video_en_i_video_clk : std_logic;`
233			`signal video_en_p_video_clk : std_logic;`
234
235			`-- Service signals`
236			`signal V_CTRL_X0 : std_logic;`
237			`signal V_CTRL_X1 : std_logic;`
238			`signal V_CTRL_X2 : std_logic;`
239			`signal V_CTRL_X3 : std_logic;`
240			`signal V_CTRL_X4 : std_logic;`
241			`signal V_CTRL_X5 : std_logic;`
242
243			`-- Fifo signals`
244			`signal dreq_i : std_logic;`
245			`signal dack_i : std_logic;`
246			`signal rsync : std_logic;`
247			`signal tc_i : std_logic;`
248			`signal data_in : std_logic_vector(31 downto 0);`
249			`signal user_rst : std_logic;`
250			`signal fifo_data_out : std_logic_vector(31 downto 0);`
251			`signal fifo_init : std_logic;`
252
253			`signal ch0_r : std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
254			`signal ch0_g : std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
255			`signal ch0_b : std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
256			`signal ch0_a : std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
257			`signal ch0_int : std_logic;`
258
259			`-- Control Registers and bit aliases`
260			`signal video_ctrl_reg : std_logic_vector(31 downto 0) := (Others => '0');`
261
262			`signal xxx : std_logic_vector(3 downto 0);`
263			`signal xxx_1 : std_logic_vector(3 downto 0);`
264
265			`signal ctrl_data : std_logic_vector(31 downto 0);`
266			`signal ctrl_addr : std_logic_vector(31 downto 0);`
267			`signal ctrl_wr : std_logic;`
268
269			`signal delay_cnt : std_logic_vector(20 downto 0);`
270			`signal video_en_e : std_logic;`
271
272			`BEGIN`
273
274			`-- Fifo instance and DMA CTRL`
275
276			`user_rst <= Not video_en_video_clk;`
277			`--user_read <= '0';`
278
279			`CH0_FIFO_I : data_rgb`
280			`Generic map (`
281			`C_FAMILY => C_FAMILY,`
282			`C_VD_DATA_WIDTH => C_VD_DATA_WIDTH,`
283			`V_CNT_SIZE => C_VCNT_SIZE,`
284			`H_CNT_SIZE => C_HCNT_SIZE,`
285			`PIXEL_WIDTH => PIXEL_WIDTH,`
286			`PIXEL_DEPTH => PIXEL_DEPTH)`
287			`port map (`
288			`-- System interface`
289			`Sys_Rst => Sys_Rst,`
290			`NPI_CLK => NPI_CLK,`
291
292			`Sys_Clk => Sys_Clk,`
293			`VIDEO_CLK => VIDEO_CLK,`
294			`VIDEO_DE => de_i,`
295			`VIDEO_EN => video_en_video_clk,`
296
297			`VIDEO_R => ch0_r,`
298			`VIDEO_G => ch0_g,`
299			`VIDEO_B => ch0_b,`
300			`VIDEO_A => ch0_a,`
301
302			`INTR => ch0_int,`
303
304			`DMA_INIT => DMA_INIT,`
305			`DMA_DACK => DMA_DACK,`
306			`DMA_DATA => DMA_DATA,`
307			`DMA_DREQ => DMA_DREQ,`
308			`DMA_RSYNC => DMA_RSYNC,`
309			`DMA_TC => DMA_TC,`
310
311			`X_0 => open,`
312			`X_1 => open,`
313			`X_2 => open,`
314			`X_3 => open,`
315			`X_4 => open,`
316			`X_5 => open);`
317
318			`x_hsync_delay <= conv_std_logic_vector(2, x_hsync_delay'length);`
319			`x_vsync_delay <= conv_std_logic_vector(2, x_vsync_delay'length);`
320			`x_de_delay <= conv_std_logic_vector(0, x_de_delay'length);`
321
322			`-- Video CTRL instance`
323
324			`PROCESS(sys_clk)`
325			`BEGIN`
326			`If Sys_Rst = '1' Then`
327			`delay_cnt <= (others => '1');`
328			`ElsIf sys_clk'event And sys_clk = '1' Then`
329			`If DMA_INIT = '0' Then`
330			`delay_cnt <= (others => '1');`
331			`ElsIf delay_cnt > 0 Then`
332			`delay_cnt <= delay_cnt - 1;`
333			`End If;`
334			`video_en <= video_en_e;`
335			`End If;`
336			`END PROCESS;`
337
338			`video_en_e <= '1' When delay_cnt = 0 Else '0'; --video_ctrl_reg(0);`
339
340			`res_video_en : entity work.resample_r`
341			`port map(`
342			`Clk => VIDEO_CLK,`
343			`Rst => Sys_Rst,`
344			`D_i => video_en,`
345			`D_o => video_en_video_clk);`
346
347			`video_ctrl_i : video_ctrl`
348			`generic map (`
349			`C_FAMILY => C_FAMILY,`
350			`PIXEL_DEPTH => PIXEL_DEPTH,`
351
352			`C_VCNT_SIZE => C_VCNT_SIZE,`
353			`C_VBACK_PORCH => C_VBACK_PORCH,`
354			`C_VFRONT_PORCH => C_VFRONT_PORCH,`
355			`C_VVIDEO_ACTIVE => C_VVIDEO_ACTIVE,`
356			`C_VSYNC_PULSE => C_VSYNC_PULSE,`
357
358			`C_HCNT_SIZE => C_HCNT_SIZE,`
359			`C_HBACK_PORCH => C_HBACK_PORCH,`
360			`C_HFRONT_PORCH => C_HFRONT_PORCH,`
361			`C_HVIDEO_ACTIVE => C_HVIDEO_ACTIVE,`
362			`C_HSYNC_PULSE => C_HSYNC_PULSE)`
363
364			`port map (`
365			`-- System interface`
366			`Sys_Rst => SYS_RST, -- System reset`
367
368			`VSYNC_POL => C_VD_V_POL,`
369			`HSYNC_POL => C_VD_H_POL,`
370			`DE_POL => VCC,`
371
372			`X_HSYNC_DELAY => x_hsync_delay,`
373			`X_VSYNC_DELAY => x_vsync_delay,`
374			`X_DE_DELAY => x_de_delay,`
375
376			`VSYNC => vsync_i,`
377			`HSYNC => hsync_i,`
378			`DE => de_i,`
379			`VSYNC_VALUE => row_position,`
380			`HSYNC_VALUE => col_position,`
381			`LAST_LINE => last_line,`
382			`FRAME_END => frame_end,`
383
384			`VIDEO_EN => video_en_video_clk,`
385			`VIDEO_DATA_R => ch0_r,`
386			`VIDEO_DATA_G => ch0_g,`
387			`VIDEO_DATA_B => ch0_b,`
388			`VIDEO_CLK_IN => VIDEO_CLK,`
389			`VIDEO_VSYNC => VIDEO_VSYNC,`
390			`VIDEO_HSYNC => VIDEO_HSYNC,`
391			`VIDEO_DE => VIDEO_DE,`
392			`VIDEO_CLK_OUT => VIDEO_CLK_OUT,`
393			`VIDEO_R => VIDEO_R,`
394			`VIDEO_G => VIDEO_G,`
395			`VIDEO_B => VIDEO_B,`
396
397			`X_0 => V_CTRL_X0,`
398			`X_1 => V_CTRL_X1,`
399			`X_2 => V_CTRL_X2,`
400			`X_3 => V_CTRL_X3,`
401			`X_4 => V_CTRL_X4,`
402			`X_5 => V_CTRL_X5);`
403
404
405			`end implementation;`
406