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---- ----
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---- Vertical V4 clock generator ----
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---- ----
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---- Author(s): ----
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---- - Slavek Valach, s.valach@dspfpga.com ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2008 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.0 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU General Public License for more details.----
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---- ----
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---- You should have received a copy of the GNU General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/gpl.txt ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.all;
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-------------------------------------------------------------------------------
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-- Entity section
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-----------------------------------------------------------------------------
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entity video_clk_gen_v4 is
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Generic (
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POLARITY : natural := 1); -- Define polarity of the output clock signal
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port (
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CLK : in std_logic; -- Input clock
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RST : in std_logic; -- System reset
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CLK_OUT : out std_logic);
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end video_clk_gen_v4;
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-----------------------------------------------------------------------------
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-- Architecture section
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-----------------------------------------------------------------------------
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architecture implementation of video_clk_gen_v4 is
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constant gnd : std_logic := '0';
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constant vcc : std_logic := '1';
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component ODDR
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port (
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Q : out std_logic;
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D1 : in std_logic;
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D2 : in std_logic;
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C : in std_logic;
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CE : in std_logic;
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R : in std_logic;
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S : in std_logic);
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end component;
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signal clk_n : std_logic;
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signal d0_i : std_logic;
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signal d1_i : std_logic;
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BEGIN
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clk_n <= Not clk;
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d0_i <= '1' When POLARITY = 1 Else '0';
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d1_i <= '0' When POLARITY = 1 Else '1';
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GEN_PIXEL_CLK : ODDR
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port map (
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Q => CLK_OUT,
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D1 => d0_i,
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D2 => d1_i,
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C => clk,
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CE => vcc,
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R => gnd,
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S => gnd);
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end implementation;
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