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[/] [npigrctrl/] [trunk/] [npi_vga_v1_00_b/] [data/] [npi_vga_v2_1_0.mpd] - Blame information for rev 5

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## Written by SaVa (c)DFC Design
 
BEGIN npi_vga
 
## Peripheral Options
OPTION RUN_NGCBUILD  = TRUE
OPTION STYLE         = MIX
OPTION IMP_NETLIST   = TRUE
OPTION HDL           = VHDL
OPTION DESC          = npi_vga
OPTION LONG_DESC     = Simple NPI VGA Controller
OPTION ARCH_SUPPORT_MAP = (virtex2p = DEVELOPMENT, virtex4 = DEVELOPMENT, spartan3a = DEVELOPMENT, spartan3e = DEVELOPMENT, virtex5fx = DEVELOPMENT, virtex5lx = DEVELOPMENT)
OPTION IP_GROUP      = MICROBLAZE:PPC:USER
OPTION IPTYPE        = PERIPHERAL
 
## Bus Interfaces
BUS_INTERFACE BUS = MPMC_PIM, BUS_STD = XIL_NPI, BUS_TYPE = INITIATOR
BUS_INTERFACE BUS = SPLB, BUS_TYPE = SLAVE, BUS_STD = PLBV46
 
## Generics for VHDL or Parameters for Verilog
PARAMETER C_VD_PIXEL_DEPTH       = 6, DT = integer
 
 
 
PARAMETER C_NPI_BURST_SIZE       = 128, DT = integer, range = (256, 128, 64, 32, 16, 8)
PARAMETER C_NPI_ADDR_WIDTH       = 32, DT = INTEGER
PARAMETER C_NPI_DATA_WIDTH       = 64, DT = integer, range = (64, 32)
PARAMETER C_NPI_BE_WIDTH         = 8, DT = integer, range = (8, 4)
PARAMETER C_NPI_RDWDADDR_WIDTH   = 4, DT = integer
 
PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
PARAMETER C_SPLB_MID_WIDTH = 1, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
PARAMETER C_FAMILY = virtex5, DT = STRING
PARAMETER C_MEM0_BASEADDR = 0xffffffff, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = BASE, PAIR = C_MEM0_HIGHADDR, MIN_SIZE = 0x10000, ASSIGNMENT = REQUIRE
PARAMETER C_MEM0_HIGHADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = HIGH, PAIR = C_MEM0_BASEADDR, ASSIGNMENT = REQUIRE
PARAMETER C_MEM1_BASEADDR = 0xffffffff, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = BASE, PAIR = C_MEM1_HIGHADDR, MIN_SIZE = 0x10000, ASSIGNMENT = REQUIRE
PARAMETER C_MEM1_HIGHADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = HIGH, PAIR = C_MEM1_BASEADDR, ASSIGNMENT = REQUIRE
PARAMETER C_VD_ADDR        = 0x00800000,  DT = std_logic_vector
PARAMETER C_VD_STRIDE      = 640,         DT = integer
PARAMETER C_VD_WIDTH       = 640,         DT = integer
PARAMETER C_VD_HEIGHT      = 480,         DT = integer
PARAMETER C_VD_PIXEL_D     = 32,          DT = integer, range = (8, 16, 32)
PARAMETER C_VD_H_BP        = 56,          DT = integer
PARAMETER C_VD_H_FP        = 16,          DT = integer
PARAMETER C_VD_H_SYNC_W    = 96,          DT = integer
PARAMETER C_VD_H_POL       = 0,           DT = std_logic
PARAMETER C_VD_V_BP        = 33,          DT = integer
PARAMETER C_VD_V_FP        = 10,          DT = integer
PARAMETER C_VD_V_SYNC_W    = 2,           DT = integer
PARAMETER C_VD_V_POL       = 0,           DT = std_logic
 
## Ports
#
PORT NPI_Clk              = "",             DIR = I
PORT NPI_RST              = "",             DIR = I
PORT NPI_Addr             = Addr,           DIR = O, BUS = MPMC_PIM, VEC = [31:0]
PORT NPI_AddrReq          = AddrReq,        DIR = O, BUS = MPMC_PIM
PORT NPI_AddrAck          = AddrAck,        DIR = I, BUS = MPMC_PIM
PORT NPI_RNW              = RNW,            DIR = O, BUS = MPMC_PIM
PORT NPI_Size             = Size,           DIR = O, BUS = MPMC_PIM, VEC = [3:0]
PORT NPI_RdModWr          = RdModWr,        DIR = O, BUS = MPMC_PIM
PORT NPI_WrFIFO_Data      = WrFIFO_Data,    DIR = O, BUS = MPMC_PIM, VEC = [(C_NPI_DATA_WIDTH-1):0]
PORT NPI_WrFIFO_BE        = WrFIFO_BE,      DIR = O, BUS = MPMC_PIM, VEC = [(C_NPI_DATA_WIDTH/8-1):0]
PORT NPI_WrFIFO_Push      = WrFIFO_Push,    DIR = O, BUS = MPMC_PIM
PORT NPI_RdFIFO_Data      = RdFIFO_Data,    DIR = I, BUS = MPMC_PIM, VEC = [(C_NPI_DATA_WIDTH-1):0]
PORT NPI_RdFIFO_Pop       = RdFIFO_Pop,     DIR = O, BUS = MPMC_PIM
PORT NPI_RdFIFO_RdWdAddr  = RdFIFO_RdWdAddr, DIR = I, BUS = MPMC_PIM, VEC = [3:0]
PORT NPI_WrFIFO_Empty     = WrFIFO_Empty,   DIR = I, BUS = MPMC_PIM
PORT NPI_WrFIFO_AlmostFull= WrFIFO_AlmostFull, DIR = I, BUS = MPMC_PIM
PORT NPI_WrFIFO_Flush     = WrFIFO_Flush,   DIR = O, BUS = MPMC_PIM
PORT NPI_RdFIFO_Empty     = RdFIFO_Empty,   DIR = I, BUS = MPMC_PIM
PORT NPI_RdFIFO_Flush     = RdFIFO_Flush,   DIR = O, BUS = MPMC_PIM
PORT NPI_RdFIFO_Latency   = RDFIFO_Latency, DIR = I, BUS = MPMC_PIM, VEC = [1:0]
PORT NPI_InitDone         = InitDone,       DIR = I, BUS = MPMC_PIM
 
PORT VIDEO_CLK             = "",             DIR = I
PORT VIDEO_VSYNC           = "",             DIR = O
PORT VIDEO_HSYNC           = "",             DIR = O
PORT VIDEO_DE              = "",             DIR = O
PORT VIDEO_CLK_OUT         = "",             DIR = O
PORT VIDEO_R               = "",             DIR = O, VEC = [C_VD_PIXEL_DEPTH - 1 : 0]
PORT VIDEO_G               = "",             DIR = O, VEC = [C_VD_PIXEL_DEPTH - 1 : 0]
PORT VIDEO_B               = "",             DIR = O, VEC = [C_VD_PIXEL_DEPTH - 1 : 0]
 
PORT   X1                 = "",             DIR = O
PORT   X2                 = "",             DIR = O
PORT   X3                 = "",             DIR = O
PORT   X4                 = "",             DIR = O
PORT   X5                 = "",             DIR = O
PORT   X6                 = "",             DIR = O
PORT   X7                 = "",             DIR = O
PORT   X8                 = "",             DIR = O
PORT   X9                 = "",             DIR = O
 
PORT   X                  = "",              DIR = O, VEC = [7 : 0]
 
PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
 
 
 
END

Line No.	Rev	Author	Line
1	2	slavek	`## Written by SaVa (c)DFC Design`
2
3			`BEGIN npi_vga`
4
5			`## Peripheral Options`
6			`OPTION RUN_NGCBUILD = TRUE`
7			`OPTION STYLE = MIX`
8			`OPTION IMP_NETLIST = TRUE`
9			`OPTION HDL = VHDL`
10			`OPTION DESC = npi_vga`
11			`OPTION LONG_DESC = Simple NPI VGA Controller`
12			`OPTION ARCH_SUPPORT_MAP = (virtex2p = DEVELOPMENT, virtex4 = DEVELOPMENT, spartan3a = DEVELOPMENT, spartan3e = DEVELOPMENT, virtex5fx = DEVELOPMENT, virtex5lx = DEVELOPMENT)`
13			`OPTION IP_GROUP = MICROBLAZE:PPC:USER`
14			`OPTION IPTYPE = PERIPHERAL`
15
16			`## Bus Interfaces`
17			`BUS_INTERFACE BUS = MPMC_PIM, BUS_STD = XIL_NPI, BUS_TYPE = INITIATOR`
18			`BUS_INTERFACE BUS = SPLB, BUS_TYPE = SLAVE, BUS_STD = PLBV46`
19
20			`## Generics for VHDL or Parameters for Verilog`
21			`PARAMETER C_VD_PIXEL_DEPTH = 6, DT = integer`
22
23
24
25			`PARAMETER C_NPI_BURST_SIZE = 128, DT = integer, range = (256, 128, 64, 32, 16, 8)`
26			`PARAMETER C_NPI_ADDR_WIDTH = 32, DT = INTEGER`
27			`PARAMETER C_NPI_DATA_WIDTH = 64, DT = integer, range = (64, 32)`
28			`PARAMETER C_NPI_BE_WIDTH = 8, DT = integer, range = (8, 4)`
29			`PARAMETER C_NPI_RDWDADDR_WIDTH = 4, DT = integer`
30
31			`PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT`
32			`PARAMETER C_SPLB_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)`
33			`PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)`
34			`PARAMETER C_SPLB_MID_WIDTH = 1, DT = INTEGER, BUS = SPLB, RANGE = (1:4)`
35			`PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT`
36			`PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)`
37			`PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT`
38			`PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)`
39			`PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB`
40			`PARAMETER C_FAMILY = virtex5, DT = STRING`
41			`PARAMETER C_MEM0_BASEADDR = 0xffffffff, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = BASE, PAIR = C_MEM0_HIGHADDR, MIN_SIZE = 0x10000, ASSIGNMENT = REQUIRE`
42			`PARAMETER C_MEM0_HIGHADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = HIGH, PAIR = C_MEM0_BASEADDR, ASSIGNMENT = REQUIRE`
43			`PARAMETER C_MEM1_BASEADDR = 0xffffffff, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = BASE, PAIR = C_MEM1_HIGHADDR, MIN_SIZE = 0x10000, ASSIGNMENT = REQUIRE`
44			`PARAMETER C_MEM1_HIGHADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = HIGH, PAIR = C_MEM1_BASEADDR, ASSIGNMENT = REQUIRE`
45			`PARAMETER C_VD_ADDR = 0x00800000, DT = std_logic_vector`
46			`PARAMETER C_VD_STRIDE = 640, DT = integer`
47			`PARAMETER C_VD_WIDTH = 640, DT = integer`
48			`PARAMETER C_VD_HEIGHT = 480, DT = integer`
49			`PARAMETER C_VD_PIXEL_D = 32, DT = integer, range = (8, 16, 32)`
50			`PARAMETER C_VD_H_BP = 56, DT = integer`
51			`PARAMETER C_VD_H_FP = 16, DT = integer`
52			`PARAMETER C_VD_H_SYNC_W = 96, DT = integer`
53			`PARAMETER C_VD_H_POL = 0, DT = std_logic`
54			`PARAMETER C_VD_V_BP = 33, DT = integer`
55			`PARAMETER C_VD_V_FP = 10, DT = integer`
56			`PARAMETER C_VD_V_SYNC_W = 2, DT = integer`
57			`PARAMETER C_VD_V_POL = 0, DT = std_logic`
58
59			`## Ports`
60			`#`
61			`PORT NPI_Clk = "", DIR = I`
62			`PORT NPI_RST = "", DIR = I`
63			`PORT NPI_Addr = Addr, DIR = O, BUS = MPMC_PIM, VEC = [31:0]`
64			`PORT NPI_AddrReq = AddrReq, DIR = O, BUS = MPMC_PIM`
65			`PORT NPI_AddrAck = AddrAck, DIR = I, BUS = MPMC_PIM`
66			`PORT NPI_RNW = RNW, DIR = O, BUS = MPMC_PIM`
67			`PORT NPI_Size = Size, DIR = O, BUS = MPMC_PIM, VEC = [3:0]`
68			`PORT NPI_RdModWr = RdModWr, DIR = O, BUS = MPMC_PIM`
69			`PORT NPI_WrFIFO_Data = WrFIFO_Data, DIR = O, BUS = MPMC_PIM, VEC = [(C_NPI_DATA_WIDTH-1):0]`
70			`PORT NPI_WrFIFO_BE = WrFIFO_BE, DIR = O, BUS = MPMC_PIM, VEC = [(C_NPI_DATA_WIDTH/8-1):0]`
71			`PORT NPI_WrFIFO_Push = WrFIFO_Push, DIR = O, BUS = MPMC_PIM`
72			`PORT NPI_RdFIFO_Data = RdFIFO_Data, DIR = I, BUS = MPMC_PIM, VEC = [(C_NPI_DATA_WIDTH-1):0]`
73			`PORT NPI_RdFIFO_Pop = RdFIFO_Pop, DIR = O, BUS = MPMC_PIM`
74			`PORT NPI_RdFIFO_RdWdAddr = RdFIFO_RdWdAddr, DIR = I, BUS = MPMC_PIM, VEC = [3:0]`
75			`PORT NPI_WrFIFO_Empty = WrFIFO_Empty, DIR = I, BUS = MPMC_PIM`
76			`PORT NPI_WrFIFO_AlmostFull= WrFIFO_AlmostFull, DIR = I, BUS = MPMC_PIM`
77			`PORT NPI_WrFIFO_Flush = WrFIFO_Flush, DIR = O, BUS = MPMC_PIM`
78			`PORT NPI_RdFIFO_Empty = RdFIFO_Empty, DIR = I, BUS = MPMC_PIM`
79			`PORT NPI_RdFIFO_Flush = RdFIFO_Flush, DIR = O, BUS = MPMC_PIM`
80			`PORT NPI_RdFIFO_Latency = RDFIFO_Latency, DIR = I, BUS = MPMC_PIM, VEC = [1:0]`
81			`PORT NPI_InitDone = InitDone, DIR = I, BUS = MPMC_PIM`
82
83			`PORT VIDEO_CLK = "", DIR = I`
84			`PORT VIDEO_VSYNC = "", DIR = O`
85			`PORT VIDEO_HSYNC = "", DIR = O`
86			`PORT VIDEO_DE = "", DIR = O`
87			`PORT VIDEO_CLK_OUT = "", DIR = O`
88			`PORT VIDEO_R = "", DIR = O, VEC = [C_VD_PIXEL_DEPTH - 1 : 0]`
89			`PORT VIDEO_G = "", DIR = O, VEC = [C_VD_PIXEL_DEPTH - 1 : 0]`
90			`PORT VIDEO_B = "", DIR = O, VEC = [C_VD_PIXEL_DEPTH - 1 : 0]`
91
92			`PORT X1 = "", DIR = O`
93			`PORT X2 = "", DIR = O`
94			`PORT X3 = "", DIR = O`
95			`PORT X4 = "", DIR = O`
96			`PORT X5 = "", DIR = O`
97			`PORT X6 = "", DIR = O`
98			`PORT X7 = "", DIR = O`
99			`PORT X8 = "", DIR = O`
100			`PORT X9 = "", DIR = O`
101
102			`PORT X = "", DIR = O, VEC = [7 : 0]`
103
104			`PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB`
105			`PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB`
106			`PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB`
107			`PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB`
108			`PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB`
109			`PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB`
110			`PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB`
111			`PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB`
112			`PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB`
113			`PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB`
114			`PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB`
115			`PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB`
116			`PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB`
117			`PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB`
118			`PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB`
119			`PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB`
120			`PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB`
121			`PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB`
122			`PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB`
123			`PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB`
124			`PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB`
125			`PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB`
126			`PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB`
127			`PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB`
128			`PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB`
129			`PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB`
130			`PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB`
131			`PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB`
132			`PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB`
133			`PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB`
134			`PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB`
135			`PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB`
136			`PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB`
137			`PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB`
138			`PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB`
139			`PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB`
140			`PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB`
141			`PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB`
142			`PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB`
143			`PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB`
144			`PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB`
145			`PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB`
146
147
148
149			`END`

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[/] [npigrctrl/] [trunk/] [npi_vga_v1_00_b/] [data/] [npi_vga_v2_1_0.mpd] - Blame information for rev 5