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slavek |
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---- ----
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---- Shift register ----
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---- ----
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---- Author(s): ----
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---- - Slavek Valach, s.valach@dspfpga.com ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2008 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.0 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU General Public License for more details.----
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---- ----
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---- You should have received a copy of the GNU General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/gpl.txt ----
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---- ----
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----------------------------------------------------------------------
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library ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.all;
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-------------------------------------------------------------------------------
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-- Entity section
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-----------------------------------------------------------------------------
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entity delay is
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port (
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CLK : in std_logic; -- Input clock
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ADD_DELAY : in std_logic_vector(3 downto 0);
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D_IN : in std_logic;
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D_OUT : out std_logic);
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end delay;
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-----------------------------------------------------------------------------
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-- Architecture section
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-----------------------------------------------------------------------------
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architecture implementation of delay is
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constant gnd : std_logic := '0';
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constant vcc : std_logic := '1';
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BEGIN
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SRL16_I : SRL16
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-- pragma translate_off
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generic map (
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INIT => x"0000")
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-- pragma translate_on
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port map (
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D => D_IN,
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Clk => Clk,
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A0 => ADD_DELAY(0),
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A1 => ADD_DELAY(1),
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A2 => ADD_DELAY(2),
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A3 => ADD_DELAY(3),
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Q => D_OUT);
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end implementation;
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