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[/] [npigrctrl/] [trunk/] [npi_vga_v1_00_b/] [hdl/] [vhdl/] [dvi_out.vhd] - Blame information for rev 5

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
library UNISIM;
use UNISIM.VComponents.all;
 
entity dvi_out is
Generic (
   C_FAMILY : string := "spartan3adsp");
    Port ( clk        : in  STD_LOGIC;
           ce         : in  STD_LOGIC;
           de_i       : in  STD_LOGIC;
           vsync_i    : in  STD_LOGIC;
           hsync_i    : in  STD_LOGIC;
           red_i      : in  STD_LOGIC_VECTOR (7 downto 0);
           green_i    : in  STD_LOGIC_VECTOR (7 downto 0);
           blue_i     : in  STD_LOGIC_VECTOR (7 downto 0);
           de         : out STD_LOGIC;
           vsync      : out STD_LOGIC;
           hsync      : out STD_LOGIC;
           dvi_data   : out STD_LOGIC_VECTOR (11 downto 0);
           dvi_clk_p  : out STD_LOGIC;
           dvi_clk_n  : out STD_LOGIC;
           reset_n    : out STD_LOGIC);
end dvi_out;
 
architecture Behavioral of dvi_out is
 
   signal d1        : STD_LOGIC_VECTOR (11 downto 0);
   signal d2        : STD_LOGIC_VECTOR (11 downto 0);
   signal d2_r      : STD_LOGIC_VECTOR (11 downto 0);
 
begin
 
   reset_n <= '1';
 
   d1    <= green_i(3 downto 0) & blue_i;
   d2    <= red_i & green_i(7 downto 4);
 
   OUT_Reg : process (clk)
   begin
      if clk'event and clk = '1' then
         de    <= de_i;
         vsync <= vsync_i;
         hsync <= hsync_i;
      end if;
   end process;
 
   V5_GEN : if (C_FAMILY /= "spartan3adsp") generate
      R1: for I in 0 to 11 generate
         ODDR_inst : ODDR
         generic map(
            DDR_CLK_EDGE => "SAME_EDGE")
         port map(
            Q  => dvi_data(I),
            C  => clk,
            CE => '1',
            D1 => d1(I),
            D2 => d2(I),
            R  => '0',
            S  => '0');
      end generate R1;
 
      ODDR_dvi_clk_p : ODDR
      generic map(
         DDR_CLK_EDGE => "OPPOSITE_EDGE")
      port map (
         Q  => dvi_clk_p,
         C  => clk,
         CE => '1',
         D1 => '0',
         D2 => '1',
         R  => '0',
         S  => '0');
 
      ODDR_dvi_clk_n : ODDR
      generic map(
         DDR_CLK_EDGE => "OPPOSITE_EDGE")
      port map (
         Q  => dvi_clk_n,
         C  => clk,
         CE => '1',
         D1 => '1',
         D2 => '0',
         R  => '0',
         S  => '0');
 
   end generate V5_GEN;
 
   S3ADSP_GEN : if (C_FAMILY = "spartan3adsp") generate
 
      Delay_Reg : process (clk)
      begin
         if (clk'event and (clk = '1')) then
            d2_r <= d2;
         end if;
      end process;
 
      R1: for I in 0 to 11 generate
         ODDR_inst : ODDR2
           generic map (
              DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1" 
              INIT => '1',             -- Sets initial state of Q  
              SRTYPE => "ASYNC")       -- Reset type
            port map (
               Q  => dvi_data(I),
               C0 => clk,
               C1 => not clk,
               CE => '1',
               D0 => d1(I),
               D1 => d2_r(I),
               R  => '0',
               S  => '0');
      end generate R1;
 
      ODDR_dvi_clk_p : ODDR2
         generic map (
            DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1" 
            INIT => '1',             -- Sets initial state of Q  
            SRTYPE => "ASYNC")       -- Reset type     
         port map (
            Q  => dvi_clk_p,
            C0 => clk,
            C1 => not clk,
            CE => '1',
            D0 => '0',
            D1 => '1',
            R  => '0',
            S  => '0');
 
      ODDR_dvi_clk_n : ODDR2
         generic map (
            DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1" 
            INIT => '1',             -- Sets initial state of Q  
            SRTYPE => "ASYNC")       -- Reset type
         port map (
            Q  => dvi_clk_n,
            C0 => clk,
            C1 => not clk,
            CE => '1',
            D0 => '1',
            D1 => '0',
            R  => '0',
            S  => '0');
 
    end generate S3ADSP_GEN;
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	2	slavek	`library IEEE;`
2			`use IEEE.STD_LOGIC_1164.ALL;`
3			`use IEEE.STD_LOGIC_ARITH.ALL;`
4			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
5
6			`library UNISIM;`
7			`use UNISIM.VComponents.all;`
8
9			`entity dvi_out is`
10			`Generic (`
11			`C_FAMILY : string := "spartan3adsp");`
12			`Port ( clk : in STD_LOGIC;`
13			`ce : in STD_LOGIC;`
14			`de_i : in STD_LOGIC;`
15			`vsync_i : in STD_LOGIC;`
16			`hsync_i : in STD_LOGIC;`
17			`red_i : in STD_LOGIC_VECTOR (7 downto 0);`
18			`green_i : in STD_LOGIC_VECTOR (7 downto 0);`
19			`blue_i : in STD_LOGIC_VECTOR (7 downto 0);`
20			`de : out STD_LOGIC;`
21			`vsync : out STD_LOGIC;`
22			`hsync : out STD_LOGIC;`
23			`dvi_data : out STD_LOGIC_VECTOR (11 downto 0);`
24			`dvi_clk_p : out STD_LOGIC;`
25			`dvi_clk_n : out STD_LOGIC;`
26			`reset_n : out STD_LOGIC);`
27			`end dvi_out;`
28
29			`architecture Behavioral of dvi_out is`
30
31			`signal d1 : STD_LOGIC_VECTOR (11 downto 0);`
32			`signal d2 : STD_LOGIC_VECTOR (11 downto 0);`
33			`signal d2_r : STD_LOGIC_VECTOR (11 downto 0);`
34
35			`begin`
36
37			`reset_n <= '1';`
38
39			`d1 <= green_i(3 downto 0) & blue_i;`
40			`d2 <= red_i & green_i(7 downto 4);`
41
42			`OUT_Reg : process (clk)`
43			`begin`
44			`if clk'event and clk = '1' then`
45			`de <= de_i;`
46			`vsync <= vsync_i;`
47			`hsync <= hsync_i;`
48			`end if;`
49			`end process;`
50
51			`V5_GEN : if (C_FAMILY /= "spartan3adsp") generate`
52			`R1: for I in 0 to 11 generate`
53			`ODDR_inst : ODDR`
54			`generic map(`
55			`DDR_CLK_EDGE => "SAME_EDGE")`
56			`port map(`
57			`Q => dvi_data(I),`
58			`C => clk,`
59			`CE => '1',`
60			`D1 => d1(I),`
61			`D2 => d2(I),`
62			`R => '0',`
63			`S => '0');`
64			`end generate R1;`
65
66			`ODDR_dvi_clk_p : ODDR`
67			`generic map(`
68			`DDR_CLK_EDGE => "OPPOSITE_EDGE")`
69			`port map (`
70			`Q => dvi_clk_p,`
71			`C => clk,`
72			`CE => '1',`
73			`D1 => '0',`
74			`D2 => '1',`
75			`R => '0',`
76			`S => '0');`
77
78			`ODDR_dvi_clk_n : ODDR`
79			`generic map(`
80			`DDR_CLK_EDGE => "OPPOSITE_EDGE")`
81			`port map (`
82			`Q => dvi_clk_n,`
83			`C => clk,`
84			`CE => '1',`
85			`D1 => '1',`
86			`D2 => '0',`
87			`R => '0',`
88			`S => '0');`
89
90			`end generate V5_GEN;`
91
92			`S3ADSP_GEN : if (C_FAMILY = "spartan3adsp") generate`
93
94			`Delay_Reg : process (clk)`
95			`begin`
96			`if (clk'event and (clk = '1')) then`
97			`d2_r <= d2;`
98			`end if;`
99			`end process;`
100
101			`R1: for I in 0 to 11 generate`
102			`ODDR_inst : ODDR2`
103			`generic map (`
104			`DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1"`
105			`INIT => '1', -- Sets initial state of Q`
106			`SRTYPE => "ASYNC") -- Reset type`
107			`port map (`
108			`Q => dvi_data(I),`
109			`C0 => clk,`
110			`C1 => not clk,`
111			`CE => '1',`
112			`D0 => d1(I),`
113			`D1 => d2_r(I),`
114			`R => '0',`
115			`S => '0');`
116			`end generate R1;`
117
118			`ODDR_dvi_clk_p : ODDR2`
119			`generic map (`
120			`DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1"`
121			`INIT => '1', -- Sets initial state of Q`
122			`SRTYPE => "ASYNC") -- Reset type`
123			`port map (`
124			`Q => dvi_clk_p,`
125			`C0 => clk,`
126			`C1 => not clk,`
127			`CE => '1',`
128			`D0 => '0',`
129			`D1 => '1',`
130			`R => '0',`
131			`S => '0');`
132
133			`ODDR_dvi_clk_n : ODDR2`
134			`generic map (`
135			`DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1"`
136			`INIT => '1', -- Sets initial state of Q`
137			`SRTYPE => "ASYNC") -- Reset type`
138			`port map (`
139			`Q => dvi_clk_n,`
140			`C0 => clk,`
141			`C1 => not clk,`
142			`CE => '1',`
143			`D0 => '1',`
144			`D1 => '0',`
145			`R => '0',`
146			`S => '0');`
147
148			`end generate S3ADSP_GEN;`
149
150			`end Behavioral;`
151

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[/] [npigrctrl/] [trunk/] [npi_vga_v1_00_b/] [hdl/] [vhdl/] [dvi_out.vhd] - Blame information for rev 5