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[/] [npigrctrl/] [trunk/] [npi_vga_v1_00_b/] [hdl/] [vhdl/] [fifo.vhd] - Blame information for rev 7

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----------------------------------------------------------------------
----                                                              ----
---- fifo wrapper                                                 ----
----                                                              ----
---- Author(s):                                                   ----
---- - Slavek Valach, s.valach@dspfpga.com                        ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2008 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU General          ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.0 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU General Public License for more details.----
----                                                              ----
---- You should have received a copy of the GNU General           ----
---- Public License along with this source; if not, download it   ----
---- from http://www.gnu.org/licenses/gpl.txt                     ----
----                                                              ----
----------------------------------------------------------------------
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-------------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
 
entity d_fifo is
generic (
   C_VD_DATA_WIDTH               : integer := 64;
   C_FAMILY                      : string  := "virtex5");
port (
-- System interface      
   Sys_Clk                       : in     std_logic;                    -- Base system clock
   NPI_CLK                       : in     std_logic;
   Sys_Rst                       : in     std_logic;                    -- System reset
 
-- DMA Channel interface
--   DMA_CLK                       : in     std_logic;     -- DMA clock time domain (the asynchronous FIFO will be used)
   DMA_DREQ                      : out    std_logic;     -- Data request
   DMA_DACK                      : in     std_logic;     -- Data ack
   DMA_RSYNC                     : out    std_logic;     -- Synchronization reset (restarts the channel)
   DMA_TC                        : in     std_logic;     -- Terminal count (the signal is generated at the end of the transfer)
   DMA_DATA                      : in     std_logic_vector(C_VD_DATA_WIDTH - 1 downto 0);
 
-- User interface (the reader side)
   USER_CLK                      : in     std_logic;                    -- User clk is used as an asynchronous read clock
   USER_RST                      : in     std_logic;
   USER_DREQ                     : in     std_logic;
   USER_RD                       : in     std_logic;
   USER_DRDY                     : out    std_logic;
 
   XXX                           : out    std_logic_vector(3 downto 0);
 
   USER_DATA                     : out    std_logic_vector(31 downto 0));
 
end d_fifo;
 
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of d_fifo is
 
component fifo_sp_64
port (
   din                        : in     std_logic_vector(63 downto 0);
   rd_clk                     : in     std_logic;
   rd_en                      : in     std_logic;
   rst                        : in     std_logic;
   wr_clk                     : in     std_logic;
   wr_en                      : in     std_logic;
   dout                       : out    std_logic_vector(31 downto 0);
   empty                      : out    std_logic;
   full                       : out    std_logic;
   prog_empty                 : out    std_logic;
   prog_full                  : out    std_logic);
end component;
 
component fifo_v4_64
port (
   din                        : in     std_logic_vector(63 downto 0);
   rd_clk                     : in     std_logic;
   rd_en                      : in     std_logic;
   rst                        : in     std_logic;
   wr_clk                     : in     std_logic;
   wr_en                      : in     std_logic;
   dout                       : out    std_logic_vector(31 downto 0);
   empty                      : out    std_logic;
   full                       : out    std_logic;
   prog_empty                 : out    std_logic;
   prog_full                  : out    std_logic);
end component;
 
component fifo_v5_64
port (
   din                        : in     std_logic_vector(63 downto 0);
   rd_clk                     : in     std_logic;
   rd_en                      : in     std_logic;
   rst                        : in     std_logic;
   wr_clk                     : in     std_logic;
   wr_en                      : in     std_logic;
   dout                       : out    std_logic_vector(31 downto 0);
   empty                      : out    std_logic;
   full                       : out    std_logic;
   prog_empty                 : out    std_logic;
   prog_full                  : out    std_logic);
end component;
 
component fifo_sp_32
port (
   din                        : in     std_logic_vector(31 downto 0);
   rd_clk                     : in     std_logic;
   rd_en                      : in     std_logic;
   rst                        : in     std_logic;
   wr_clk                     : in     std_logic;
   wr_en                      : in     std_logic;
   dout                       : out    std_logic_vector(31 downto 0);
   empty                      : out    std_logic;
   full                       : out    std_logic;
   prog_empty                 : out    std_logic;
   prog_full                  : out    std_logic);
end component;
 
component fifo_v4_32
port (
   din                        : in     std_logic_vector(31 downto 0);
   rd_clk                     : in     std_logic;
   rd_en                      : in     std_logic;
   rst                        : in     std_logic;
   wr_clk                     : in     std_logic;
   wr_en                      : in     std_logic;
   dout                       : out    std_logic_vector(31 downto 0);
   empty                      : out    std_logic;
   full                       : out    std_logic;
   prog_empty                 : out    std_logic;
   prog_full                  : out    std_logic);
end component;
 
component fifo_v5_32
port (
   din                        : in     std_logic_vector(31 downto 0);
   rd_clk                     : in     std_logic;
   rd_en                      : in     std_logic;
   rst                        : in     std_logic;
   wr_clk                     : in     std_logic;
   wr_en                      : in     std_logic;
   dout                       : out    std_logic_vector(31 downto 0);
   empty                      : out    std_logic;
   full                       : out    std_logic;
   prog_empty                 : out    std_logic;
   prog_full                  : out    std_logic);
end component;
 
constant low                     : std_logic := '0';
constant high                    : std_logic := '1';
 
signal fifo_prog_full            : std_logic;
signal fifo_rst                  : std_logic;
signal fifo_prog_empty           : std_logic;
signal fifo_data_out             : std_logic_vector(31 downto 0);
signal fifo_full                 : std_logic;
signal fifo_empty                : std_logic;
signal fifo_wr_en                : std_logic;
 
begin -- architecture IMP
 
   DMA_DREQ <= '1' When (USER_DREQ = '1') And (fifo_prog_full = '0') Else '0';
   fifo_rst <= '1' When (Sys_Rst = '1') Or (USER_RST = '1') Else '0';
   USER_DRDY <= Not fifo_prog_empty;
 
  fifo_wr_en <= '1' When DMA_DACK = '1' And Sys_Rst = '0' Else '0';
 
gen_sp : if (C_FAMILY = "spartan3e") Or (C_FAMILY = "spartan3a") generate
   sp_fw_64 :  If C_VD_DATA_WIDTH = 64 generate
      data_fifo : fifo_sp_64
      port map (
         din                     => DMA_DATA,
         rd_clk                  => User_Clk,
         rd_en                   => USER_RD,
         rst                     => fifo_rst,
         wr_clk                  => NPI_CLK,
         wr_en                   => fifo_wr_en,--DMA_DACK,
         dout                    => fifo_data_out,
         empty                   => fifo_empty,
         full                    => fifo_full,
         prog_empty              => fifo_prog_empty,
         prog_full               => fifo_prog_full);
   End Generate;
   sp_fw_32 :  If C_VD_DATA_WIDTH = 32 generate
      data_fifo : fifo_sp_32
      port map (
         din                     => DMA_DATA,
         rd_clk                  => User_Clk,
         rd_en                   => USER_RD,
         rst                     => fifo_rst,
         wr_clk                  => NPI_CLK,
         wr_en                   => fifo_wr_en,--DMA_DACK,
         dout                    => fifo_data_out,
         empty                   => fifo_empty,
         full                    => fifo_full,
         prog_empty              => fifo_prog_empty,
         prog_full               => fifo_prog_full);
   End Generate;
End Generate;
 
gen_v4 : if (C_FAMILY = "virtex4") generate
   v4_fw_64 :  If C_VD_DATA_WIDTH = 64 generate
      data_fifo : fifo_v4_64
      port map (
         din                     => DMA_DATA,
         rd_clk                  => User_Clk,
         rd_en                   => USER_RD,
         rst                     => fifo_rst,
         wr_clk                  => NPI_CLK,
         wr_en                   => fifo_wr_en,--DMA_DACK,
         dout                    => fifo_data_out,
         empty                   => fifo_empty,
         full                    => fifo_full,
         prog_empty              => fifo_prog_empty,
         prog_full               => fifo_prog_full);
   End Generate;
   v4_fw_32 :  If C_VD_DATA_WIDTH = 32 generate
      data_fifo : fifo_v4_32
      port map (
         din                     => DMA_DATA,
         rd_clk                  => User_Clk,
         rd_en                   => USER_RD,
         rst                     => fifo_rst,
         wr_clk                  => NPI_CLK,
         wr_en                   => fifo_wr_en,--DMA_DACK,
         dout                    => fifo_data_out,
         empty                   => fifo_empty,
         full                    => fifo_full,
         prog_empty              => fifo_prog_empty,
         prog_full               => fifo_prog_full);
   End Generate;
End Generate;
 
gen_v5 : if (C_FAMILY = "virtex5") generate
   v5_fw_64 :  If C_VD_DATA_WIDTH = 64 generate
      data_fifo : fifo_v5_64
      port map (
         din                     => DMA_DATA,
         rd_clk                  => User_Clk,
         rd_en                   => USER_RD,
         rst                     => fifo_rst,
         wr_clk                  => NPI_CLK,
         wr_en                   => fifo_wr_en,--DMA_DACK,
         dout                    => fifo_data_out,
         empty                   => fifo_empty,
         full                    => fifo_full,
         prog_empty              => fifo_prog_empty,
         prog_full               => fifo_prog_full);
   End Generate;
   v5_fw_32 :  If C_VD_DATA_WIDTH = 32 generate
      data_fifo : fifo_v5_32
      port map (
         din                     => DMA_DATA,
         rd_clk                  => User_Clk,
         rd_en                   => USER_RD,
         rst                     => fifo_rst,
         wr_clk                  => NPI_CLK,
         wr_en                   => fifo_wr_en,--DMA_DACK,
         dout                    => fifo_data_out,
         empty                   => fifo_empty,
         full                    => fifo_full,
         prog_empty              => fifo_prog_empty,
         prog_full               => fifo_prog_full);
   End Generate;
End Generate;
 
USER_DATA <= fifo_data_out;
 
XXX <= fifo_rst & fifo_prog_full & fifo_full & fifo_empty;
 
end implementation;

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Subversion Repositories npigrctrl

[/] [npigrctrl/] [trunk/] [npi_vga_v1_00_b/] [hdl/] [vhdl/] [fifo.vhd] - Blame information for rev 7

Line No.	Rev	Author	Line
1	2	slavek	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- fifo wrapper ----`
4			`---- ----`
5			`---- Author(s): ----`
6			`---- - Slavek Valach, s.valach@dspfpga.com ----`
7			`---- ----`
8			`----------------------------------------------------------------------`
9			`---- ----`
10			`---- Copyright (C) 2008 Authors and OPENCORES.ORG ----`
11			`---- ----`
12			`---- This source file may be used and distributed without ----`
13			`---- restriction provided that this copyright statement is not ----`
14			`---- removed from the file and that any derivative work contains ----`
15			`---- the original copyright notice and the associated disclaimer. ----`
16			`---- ----`
17			`---- This source file is free software; you can redistribute it ----`
18			`---- and/or modify it under the terms of the GNU General ----`
19			`---- Public License as published by the Free Software Foundation; ----`
20			`---- either version 2.0 of the License, or (at your option) any ----`
21			`---- later version. ----`
22			`---- ----`
23			`---- This source is distributed in the hope that it will be ----`
24			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
25			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
26			`---- PURPOSE. See the GNU General Public License for more details.----`
27			`---- ----`
28			`---- You should have received a copy of the GNU General ----`
29			`---- Public License along with this source; if not, download it ----`
30			`---- from http://www.gnu.org/licenses/gpl.txt ----`
31			`---- ----`
32			`----------------------------------------------------------------------`
33			`library ieee;`
34			`use IEEE.STD_LOGIC_1164.ALL;`
35			`use IEEE.STD_LOGIC_ARITH.ALL;`
36			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
37
38			`-------------------------------------------------------------------------------`
39			`-- Entity section`
40			`-----------------------------------------------------------------------------`
41
42			`entity d_fifo is`
43			`generic (`
44			`C_VD_DATA_WIDTH : integer := 64;`
45			`C_FAMILY : string := "virtex5");`
46			`port (`
47			`-- System interface`
48			`Sys_Clk : in std_logic; -- Base system clock`
49			`NPI_CLK : in std_logic;`
50			`Sys_Rst : in std_logic; -- System reset`
51
52			`-- DMA Channel interface`
53			`-- DMA_CLK : in std_logic; -- DMA clock time domain (the asynchronous FIFO will be used)`
54			`DMA_DREQ : out std_logic; -- Data request`
55			`DMA_DACK : in std_logic; -- Data ack`
56			`DMA_RSYNC : out std_logic; -- Synchronization reset (restarts the channel)`
57			`DMA_TC : in std_logic; -- Terminal count (the signal is generated at the end of the transfer)`
58			`DMA_DATA : in std_logic_vector(C_VD_DATA_WIDTH - 1 downto 0);`
59
60			`-- User interface (the reader side)`
61			`USER_CLK : in std_logic; -- User clk is used as an asynchronous read clock`
62			`USER_RST : in std_logic;`
63			`USER_DREQ : in std_logic;`
64			`USER_RD : in std_logic;`
65			`USER_DRDY : out std_logic;`
66
67			`XXX : out std_logic_vector(3 downto 0);`
68
69			`USER_DATA : out std_logic_vector(31 downto 0));`
70
71			`end d_fifo;`
72
73			`-----------------------------------------------------------------------------`
74			`-- Architecture section`
75			`-----------------------------------------------------------------------------`
76			`architecture implementation of d_fifo is`
77
78			`component fifo_sp_64`
79			`port (`
80			`din : in std_logic_vector(63 downto 0);`
81			`rd_clk : in std_logic;`
82			`rd_en : in std_logic;`
83			`rst : in std_logic;`
84			`wr_clk : in std_logic;`
85			`wr_en : in std_logic;`
86			`dout : out std_logic_vector(31 downto 0);`
87			`empty : out std_logic;`
88			`full : out std_logic;`
89			`prog_empty : out std_logic;`
90			`prog_full : out std_logic);`
91			`end component;`
92
93			`component fifo_v4_64`
94			`port (`
95			`din : in std_logic_vector(63 downto 0);`
96			`rd_clk : in std_logic;`
97			`rd_en : in std_logic;`
98			`rst : in std_logic;`
99			`wr_clk : in std_logic;`
100			`wr_en : in std_logic;`
101			`dout : out std_logic_vector(31 downto 0);`
102			`empty : out std_logic;`
103			`full : out std_logic;`
104			`prog_empty : out std_logic;`
105			`prog_full : out std_logic);`
106			`end component;`
107
108			`component fifo_v5_64`
109			`port (`
110			`din : in std_logic_vector(63 downto 0);`
111			`rd_clk : in std_logic;`
112			`rd_en : in std_logic;`
113			`rst : in std_logic;`
114			`wr_clk : in std_logic;`
115			`wr_en : in std_logic;`
116			`dout : out std_logic_vector(31 downto 0);`
117			`empty : out std_logic;`
118			`full : out std_logic;`
119			`prog_empty : out std_logic;`
120			`prog_full : out std_logic);`
121			`end component;`
122
123			`component fifo_sp_32`
124			`port (`
125			`din : in std_logic_vector(31 downto 0);`
126			`rd_clk : in std_logic;`
127			`rd_en : in std_logic;`
128			`rst : in std_logic;`
129			`wr_clk : in std_logic;`
130			`wr_en : in std_logic;`
131			`dout : out std_logic_vector(31 downto 0);`
132			`empty : out std_logic;`
133			`full : out std_logic;`
134			`prog_empty : out std_logic;`
135			`prog_full : out std_logic);`
136			`end component;`
137
138			`component fifo_v4_32`
139			`port (`
140			`din : in std_logic_vector(31 downto 0);`
141			`rd_clk : in std_logic;`
142			`rd_en : in std_logic;`
143			`rst : in std_logic;`
144			`wr_clk : in std_logic;`
145			`wr_en : in std_logic;`
146			`dout : out std_logic_vector(31 downto 0);`
147			`empty : out std_logic;`
148			`full : out std_logic;`
149			`prog_empty : out std_logic;`
150			`prog_full : out std_logic);`
151			`end component;`
152
153			`component fifo_v5_32`
154			`port (`
155			`din : in std_logic_vector(31 downto 0);`
156			`rd_clk : in std_logic;`
157			`rd_en : in std_logic;`
158			`rst : in std_logic;`
159			`wr_clk : in std_logic;`
160			`wr_en : in std_logic;`
161			`dout : out std_logic_vector(31 downto 0);`
162			`empty : out std_logic;`
163			`full : out std_logic;`
164			`prog_empty : out std_logic;`
165			`prog_full : out std_logic);`
166			`end component;`
167
168			`constant low : std_logic := '0';`
169			`constant high : std_logic := '1';`
170
171			`signal fifo_prog_full : std_logic;`
172			`signal fifo_rst : std_logic;`
173			`signal fifo_prog_empty : std_logic;`
174			`signal fifo_data_out : std_logic_vector(31 downto 0);`
175			`signal fifo_full : std_logic;`
176			`signal fifo_empty : std_logic;`
177			`signal fifo_wr_en : std_logic;`
178
179			`begin -- architecture IMP`
180
181			`DMA_DREQ <= '1' When (USER_DREQ = '1') And (fifo_prog_full = '0') Else '0';`
182			`fifo_rst <= '1' When (Sys_Rst = '1') Or (USER_RST = '1') Else '0';`
183			`USER_DRDY <= Not fifo_prog_empty;`
184
185			`fifo_wr_en <= '1' When DMA_DACK = '1' And Sys_Rst = '0' Else '0';`
186
187			`gen_sp : if (C_FAMILY = "spartan3e") Or (C_FAMILY = "spartan3a") generate`
188			`sp_fw_64 : If C_VD_DATA_WIDTH = 64 generate`
189			`data_fifo : fifo_sp_64`
190			`port map (`
191			`din => DMA_DATA,`
192			`rd_clk => User_Clk,`
193			`rd_en => USER_RD,`
194			`rst => fifo_rst,`
195			`wr_clk => NPI_CLK,`
196			`wr_en => fifo_wr_en,--DMA_DACK,`
197			`dout => fifo_data_out,`
198			`empty => fifo_empty,`
199			`full => fifo_full,`
200			`prog_empty => fifo_prog_empty,`
201			`prog_full => fifo_prog_full);`
202			`End Generate;`
203			`sp_fw_32 : If C_VD_DATA_WIDTH = 32 generate`
204			`data_fifo : fifo_sp_32`
205			`port map (`
206			`din => DMA_DATA,`
207			`rd_clk => User_Clk,`
208			`rd_en => USER_RD,`
209			`rst => fifo_rst,`
210			`wr_clk => NPI_CLK,`
211			`wr_en => fifo_wr_en,--DMA_DACK,`
212			`dout => fifo_data_out,`
213			`empty => fifo_empty,`
214			`full => fifo_full,`
215			`prog_empty => fifo_prog_empty,`
216			`prog_full => fifo_prog_full);`
217			`End Generate;`
218			`End Generate;`
219
220			`gen_v4 : if (C_FAMILY = "virtex4") generate`
221			`v4_fw_64 : If C_VD_DATA_WIDTH = 64 generate`
222			`data_fifo : fifo_v4_64`
223			`port map (`
224			`din => DMA_DATA,`
225			`rd_clk => User_Clk,`
226			`rd_en => USER_RD,`
227			`rst => fifo_rst,`
228			`wr_clk => NPI_CLK,`
229			`wr_en => fifo_wr_en,--DMA_DACK,`
230			`dout => fifo_data_out,`
231			`empty => fifo_empty,`
232			`full => fifo_full,`
233			`prog_empty => fifo_prog_empty,`
234			`prog_full => fifo_prog_full);`
235			`End Generate;`
236			`v4_fw_32 : If C_VD_DATA_WIDTH = 32 generate`
237			`data_fifo : fifo_v4_32`
238			`port map (`
239			`din => DMA_DATA,`
240			`rd_clk => User_Clk,`
241			`rd_en => USER_RD,`
242			`rst => fifo_rst,`
243			`wr_clk => NPI_CLK,`
244			`wr_en => fifo_wr_en,--DMA_DACK,`
245			`dout => fifo_data_out,`
246			`empty => fifo_empty,`
247			`full => fifo_full,`
248			`prog_empty => fifo_prog_empty,`
249			`prog_full => fifo_prog_full);`
250			`End Generate;`
251			`End Generate;`
252
253			`gen_v5 : if (C_FAMILY = "virtex5") generate`
254			`v5_fw_64 : If C_VD_DATA_WIDTH = 64 generate`
255			`data_fifo : fifo_v5_64`
256			`port map (`
257			`din => DMA_DATA,`
258			`rd_clk => User_Clk,`
259			`rd_en => USER_RD,`
260			`rst => fifo_rst,`
261			`wr_clk => NPI_CLK,`
262			`wr_en => fifo_wr_en,--DMA_DACK,`
263			`dout => fifo_data_out,`
264			`empty => fifo_empty,`
265			`full => fifo_full,`
266			`prog_empty => fifo_prog_empty,`
267			`prog_full => fifo_prog_full);`
268			`End Generate;`
269			`v5_fw_32 : If C_VD_DATA_WIDTH = 32 generate`
270			`data_fifo : fifo_v5_32`
271			`port map (`
272			`din => DMA_DATA,`
273			`rd_clk => User_Clk,`
274			`rd_en => USER_RD,`
275			`rst => fifo_rst,`
276			`wr_clk => NPI_CLK,`
277			`wr_en => fifo_wr_en,--DMA_DACK,`
278			`dout => fifo_data_out,`
279			`empty => fifo_empty,`
280			`full => fifo_full,`
281			`prog_empty => fifo_prog_empty,`
282			`prog_full => fifo_prog_full);`
283			`End Generate;`
284			`End Generate;`
285
286			`USER_DATA <= fifo_data_out;`
287
288			`XXX <= fifo_rst & fifo_prog_full & fifo_full & fifo_empty;`
289
290			`end implementation;`