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slavek |
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---- ----
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---- Horizontal generator ----
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---- ----
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---- Author(s): ----
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---- - Slavek Valach, s.valach@dspfpga.com ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2008 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.0 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU General Public License for more details.----
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---- ----
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---- You should have received a copy of the GNU General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/gpl.txt ----
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---- ----
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----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library UNISIM;
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use UNISIM.VComponents.all;
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entity hsync_gen is
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Generic (
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C_HCNT_SIZE : natural := 11;
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C_BACK_PORCH : natural := 40+8;
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C_FRONT_PORCH : natural := 8+8;
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C_VIDEO_ACTIVE : natural := 640;
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C_HSYNC_PULSE : natural := 96);
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Port (
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CLK : in std_logic;
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RST : in std_logic;
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HSYNC_VALUE : out std_logic_vector(C_HCNT_SIZE - 1 downto 0);
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HSYNC_EN : in std_logic;
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LINE_E : out std_logic;
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DE : out std_logic;
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HSYNC : out std_logic);
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end hsync_gen;
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architecture Behavioral of hsync_gen is
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constant c_scan_line : std_logic_vector(C_HCNT_SIZE - 1 downto 0) :=
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CONV_STD_LOGIC_VECTOR(C_BACK_PORCH + C_FRONT_PORCH +
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C_VIDEO_ACTIVE + C_HSYNC_PULSE, C_HCNT_SIZE);
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signal pixel_cnt : std_logic_vector(C_HCNT_SIZE - 1 downto 0);
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signal hsync_i : std_logic;
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signal de_i : std_logic;
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signal line_rst : std_logic;
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signal rst_i : std_logic;
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begin
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rst_i <= line_rst Or (Not HSYNC_EN);
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hsync_cnt : PROCESS(CLK, rst_i, pixel_cnt)
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BEGIN
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If RST = '1' Then
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pixel_cnt <= (Others => '0');
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ElsIf CLK'event And CLK = '1' Then
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If rst_i = '1' Then
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pixel_cnt <= (Others => '0');
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Else
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pixel_cnt <= pixel_cnt + 1;
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End If;
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End If;
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END PROCESS;
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line_rst <= '0' When pixel_cnt < c_scan_line - 1 Else '1' after 1 ns;
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hsync_i <= '1' When (pixel_cnt >= 0) And (pixel_cnt < C_HSYNC_PULSE) Else '0';
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de_i <= '1' When (pixel_cnt >= C_HSYNC_PULSE + C_BACK_PORCH) And (pixel_cnt <
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C_HSYNC_PULSE + C_BACK_PORCH + C_VIDEO_ACTIVE) Else '0';
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HSYNC <= hsync_i;
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DE <= de_i;
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LINE_E <= line_rst;
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HSYNC_VALUE <= pixel_cnt;
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end Behavioral;
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