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[/] [npigrctrl/] [trunk/] [npi_vga_v1_00_b/] [hdl/] [vhdl/] [reclock.vhd] - Blame information for rev 5

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----------------------------------------------------------------------
----                                                              ----
---- Misc utility                                                 ----
----                                                              ----
---- Author(s):                                                   ----
---- - Slavek Valach, s.valach@dspfpga.com                        ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2008 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU General          ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.0 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU General Public License for more details.----
----                                                              ----
---- You should have received a copy of the GNU General           ----
---- Public License along with this source; if not, download it   ----
---- from http://www.gnu.org/licenses/gpl.txt                     ----
----                                                              ----
----------------------------------------------------------------------
 
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-------------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
 
entity resample_r is             -- Resample signal at rising edges
port (
   Clk                           : in     std_logic;     -- A new clock domain          
   Rst                           : in     std_logic;     -- System reset
   D_i                           : in     std_logic;     -- Input data
   D_o                           : out    std_logic);     -- Output data with new time domain
end resample_r;
 
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of resample_r is
 
signal r_1                       : std_logic;      -- Avoid metastability
 
BEGIN
 
PROCESS(Clk, Rst, D_i)
BEGIN
   If Rst = '1' Then
      r_1 <= '0';
      D_o <= '0';
   ElsIf Clk'event And Clk = '1' Then
      r_1 <= D_i;
      D_o <= r_1;
   End If;
END PROCESS;
 
END Implementation;
 
-- ********************
-- *** Start det_re ***
-- ********************
 
-- Detects rising edge on signal D_i
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-------------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
 
entity det_re is             -- Run process on the rising edge at signal D_i which belong to Clk1 time domain
port (
   Clk                           : in     std_logic;     -- Clock 
   Rst                           : in     std_logic;     -- System reset
   D_i                           : in     std_logic;     -- Input data
   D_o                           : out    std_logic);    -- Output data with new time domain
end det_re;
 
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of det_re is
 
signal r_1                       : std_logic;      -- Avoid metastability
 
BEGIN
 
PROCESS(Clk)
BEGIN
   If Clk'event And Clk = '1' Then
      r_1 <= D_i;       -- generates one clock delay
   End If;
End PROCESS;
 
D_o <= '1' When (r_1 = '0') And (D_i = '1') Else '0';
 
End Implementation;
 
-- ******************
-- *** End det_re ***
-- ******************
 

Line No.	Rev	Author	Line
1	2	slavek	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- Misc utility ----`
4			`---- ----`
5			`---- Author(s): ----`
6			`---- - Slavek Valach, s.valach@dspfpga.com ----`
7			`---- ----`
8			`----------------------------------------------------------------------`
9			`---- ----`
10			`---- Copyright (C) 2008 Authors and OPENCORES.ORG ----`
11			`---- ----`
12			`---- This source file may be used and distributed without ----`
13			`---- restriction provided that this copyright statement is not ----`
14			`---- removed from the file and that any derivative work contains ----`
15			`---- the original copyright notice and the associated disclaimer. ----`
16			`---- ----`
17			`---- This source file is free software; you can redistribute it ----`
18			`---- and/or modify it under the terms of the GNU General ----`
19			`---- Public License as published by the Free Software Foundation; ----`
20			`---- either version 2.0 of the License, or (at your option) any ----`
21			`---- later version. ----`
22			`---- ----`
23			`---- This source is distributed in the hope that it will be ----`
24			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
25			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
26			`---- PURPOSE. See the GNU General Public License for more details.----`
27			`---- ----`
28			`---- You should have received a copy of the GNU General ----`
29			`---- Public License along with this source; if not, download it ----`
30			`---- from http://www.gnu.org/licenses/gpl.txt ----`
31			`---- ----`
32			`----------------------------------------------------------------------`
33
34			`library ieee;`
35			`use IEEE.STD_LOGIC_1164.ALL;`
36			`use IEEE.STD_LOGIC_ARITH.ALL;`
37			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
38
39			`-------------------------------------------------------------------------------`
40			`-- Entity section`
41			`-----------------------------------------------------------------------------`
42
43			`entity resample_r is -- Resample signal at rising edges`
44			`port (`
45			`Clk : in std_logic; -- A new clock domain`
46			`Rst : in std_logic; -- System reset`
47			`D_i : in std_logic; -- Input data`
48			`D_o : out std_logic); -- Output data with new time domain`
49			`end resample_r;`
50
51			`-----------------------------------------------------------------------------`
52			`-- Architecture section`
53			`-----------------------------------------------------------------------------`
54			`architecture implementation of resample_r is`
55
56			`signal r_1 : std_logic; -- Avoid metastability`
57
58			`BEGIN`
59
60			`PROCESS(Clk, Rst, D_i)`
61			`BEGIN`
62			`If Rst = '1' Then`
63			`r_1 <= '0';`
64			`D_o <= '0';`
65			`ElsIf Clk'event And Clk = '1' Then`
66			`r_1 <= D_i;`
67			`D_o <= r_1;`
68			`End If;`
69			`END PROCESS;`
70
71			`END Implementation;`
72
73			`-- ********************`
74			`-- * Start det_re *`
75			`-- ********************`
76
77			`-- Detects rising edge on signal D_i`
78			`library ieee;`
79			`use IEEE.STD_LOGIC_1164.ALL;`
80			`use IEEE.STD_LOGIC_ARITH.ALL;`
81			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
82
83			`-------------------------------------------------------------------------------`
84			`-- Entity section`
85			`-----------------------------------------------------------------------------`
86
87			`entity det_re is -- Run process on the rising edge at signal D_i which belong to Clk1 time domain`
88			`port (`
89			`Clk : in std_logic; -- Clock`
90			`Rst : in std_logic; -- System reset`
91			`D_i : in std_logic; -- Input data`
92			`D_o : out std_logic); -- Output data with new time domain`
93			`end det_re;`
94
95			`-----------------------------------------------------------------------------`
96			`-- Architecture section`
97			`-----------------------------------------------------------------------------`
98			`architecture implementation of det_re is`
99
100			`signal r_1 : std_logic; -- Avoid metastability`
101
102			`BEGIN`
103
104			`PROCESS(Clk)`
105			`BEGIN`
106			`If Clk'event And Clk = '1' Then`
107			`r_1 <= D_i; -- generates one clock delay`
108			`End If;`
109			`End PROCESS;`
110
111			`D_o <= '1' When (r_1 = '0') And (D_i = '1') Else '0';`
112
113			`End Implementation;`
114
115			`-- ******************`
116			`-- * End det_re *`
117			`-- ******************`
118

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[/] [npigrctrl/] [trunk/] [npi_vga_v1_00_b/] [hdl/] [vhdl/] [reclock.vhd] - Blame information for rev 5