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[/] [npigrctrl/] [trunk/] [npi_vga_v1_00_b/] [hdl/] [vhdl/] [reclock.vhd] - Blame information for rev 7

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1 2 slavek 
----------------------------------------------------------------------
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----                                                              ----
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---- Misc utility                                                 ----
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----                                                              ----
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---- Author(s):                                                   ----
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---- - Slavek Valach, s.valach@dspfpga.com                        ----
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----                                                              ----
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----------------------------------------------------------------------
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----                                                              ----
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---- Copyright (C) 2008 Authors and OPENCORES.ORG                 ----
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----                                                              ----
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---- This source file may be used and distributed without         ----
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---- restriction provided that this copyright statement is not    ----
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---- removed from the file and that any derivative work contains  ----
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---- the original copyright notice and the associated disclaimer. ----
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----                                                              ----
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---- This source file is free software; you can redistribute it   ----
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---- and/or modify it under the terms of the GNU General          ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.0 of the License, or (at your option) any   ----
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---- later version.                                               ----
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----                                                              ----
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---- This source is distributed in the hope that it will be       ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
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---- PURPOSE. See the GNU General Public License for more details.----
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----                                                              ----
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---- You should have received a copy of the GNU General           ----
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---- Public License along with this source; if not, download it   ----
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---- from http://www.gnu.org/licenses/gpl.txt                     ----
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----                                                              ----
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----------------------------------------------------------------------
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library ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-------------------------------------------------------------------------------
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-- Entity section
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-----------------------------------------------------------------------------
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entity resample_r is             -- Resample signal at rising edges
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port (
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   Clk                           : in     std_logic;     -- A new clock domain
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   Rst                           : in     std_logic;     -- System reset
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   D_i                           : in     std_logic;     -- Input data
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   D_o                           : out    std_logic);     -- Output data with new time domain
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end resample_r;
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-----------------------------------------------------------------------------
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-- Architecture section
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-----------------------------------------------------------------------------
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architecture implementation of resample_r is
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signal r_1                       : std_logic;      -- Avoid metastability
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BEGIN
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PROCESS(Clk, Rst, D_i)
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BEGIN
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   If Rst = '1' Then
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      r_1 <= '0';
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      D_o <= '0';
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   ElsIf Clk'event And Clk = '1' Then
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      r_1 <= D_i;
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      D_o <= r_1;
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   End If;
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END PROCESS;
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END Implementation;
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-- ********************
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-- *** Start det_re ***
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-- ********************
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-- Detects rising edge on signal D_i
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library ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-------------------------------------------------------------------------------
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-- Entity section
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-----------------------------------------------------------------------------
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entity det_re is             -- Run process on the rising edge at signal D_i which belong to Clk1 time domain
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port (
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   Clk                           : in     std_logic;     -- Clock
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   Rst                           : in     std_logic;     -- System reset
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   D_i                           : in     std_logic;     -- Input data
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   D_o                           : out    std_logic);    -- Output data with new time domain
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end det_re;
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-----------------------------------------------------------------------------
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-- Architecture section
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-----------------------------------------------------------------------------
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architecture implementation of det_re is
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signal r_1                       : std_logic;      -- Avoid metastability
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BEGIN
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PROCESS(Clk)
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BEGIN
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   If Clk'event And Clk = '1' Then
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      r_1 <= D_i;       -- generates one clock delay
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   End If;
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End PROCESS;
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D_o <= '1' When (r_1 = '0') And (D_i = '1') Else '0';
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End Implementation;
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-- ******************
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-- *** End det_re ***
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-- ******************
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