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Subversion Repositories npigrctrl

[/] [npigrctrl/] [trunk/] [npi_vga_v1_00_b/] [hdl/] [vhdl/] [video_ctrl.vhd] - Blame information for rev 5

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----------------------------------------------------------------------
----                                                              ----
---- Video Control Module                                         ----
----                                                              ----
---- Author(s):                                                   ----
---- - Slavek Valach, s.valach@dspfpga.com                        ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2008 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU General          ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.0 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU General Public License for more details.----
----                                                              ----
---- You should have received a copy of the GNU General           ----
---- Public License along with this source; if not, download it   ----
---- from http://www.gnu.org/licenses/gpl.txt                     ----
----                                                              ----
----------------------------------------------------------------------
 
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-------------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
 
entity video_ctrl is
Generic(
   C_FAMILY             : string := "virtex5";
   PIXEL_DEPTH          : integer := 6;
 
   C_VCNT_SIZE          : natural := 10;
   C_VBACK_PORCH        : natural := 25+8;
   C_VFRONT_PORCH       : natural := 2+8;
   C_VVIDEO_ACTIVE      : natural := 480;
   C_VSYNC_PULSE        : natural := 2;
 
   C_HCNT_SIZE          : natural := 10;
   C_HBACK_PORCH        : natural := 40+8;
   C_HFRONT_PORCH       : natural := 8+8+31;
   C_HVIDEO_ACTIVE      : natural := 640;
   C_HSYNC_PULSE        : natural := 96);
 
port (
   -- System interface      
   Sys_Rst                       : in     std_logic;                    -- System reset
 
   VSYNC_POL                     : in     std_logic;
   HSYNC_POL                     : in     std_logic;
   DE_POL                        : in     std_logic;
 
   X_HSYNC_DELAY                 : in     std_logic_vector(3 downto 0);
   X_VSYNC_DELAY                 : in     std_logic_vector(3 downto 0);
   X_DE_DELAY                    : in     std_logic_vector(3 downto 0);
 
   VSYNC                         : out    std_logic;
   HSYNC                         : out    std_logic;
   DE                            : out    std_logic;
   VSYNC_VALUE                   : out    std_logic_vector(C_VCNT_SIZE - 1 downto 0);
   HSYNC_VALUE                   : out    std_logic_vector(C_HCNT_SIZE - 1 downto 0);
   LAST_LINE                     : out    std_logic;
   FRAME_END                     : out    std_logic;
 
   VIDEO_EN                      : in     std_logic;
   VIDEO_DATA_R                  : in     std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_DATA_G                  : in     std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_DATA_B                  : in     std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_CLK_IN                  : in     std_logic;                    -- LCD Clock signal
   VIDEO_VSYNC                   : out    std_logic;
   VIDEO_HSYNC                   : out    std_logic;
   VIDEO_DE                      : out    std_logic;
   VIDEO_CLK_OUT                 : out    std_logic;
   VIDEO_R                       : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_G                       : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
   VIDEO_B                       : out    std_logic_vector(PIXEL_DEPTH - 1 downto 0);
 
   X_0                           : out    std_logic;
   X_1                           : out    std_logic;
   X_2                           : out    std_logic;
   X_3                           : out    std_logic;
   X_4                           : out    std_logic;
   X_5                           : out    std_logic);
 
end video_ctrl;
 
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of video_ctrl is
 
constant arch : string := "SPARTAN";
 
component hsync_gen is
Generic (
   C_HCNT_SIZE          : natural;
   C_BACK_PORCH         : natural;
   C_FRONT_PORCH        : natural;
   C_VIDEO_ACTIVE       : natural;
   C_HSYNC_PULSE        : natural);
Port (
   CLK                  : in     std_logic;
   RST                  : in     std_logic;
 
   HSYNC_VALUE          : out    std_logic_vector(C_HCNT_SIZE - 1 downto 0);
   HSYNC_EN             : in     std_logic;
   LINE_E               : out    std_logic;
   DE                   : out    std_logic;
   HSYNC                : out    std_logic);
end component;
 
component vsync_gen is
Generic(
   C_VCNT_SIZE          : natural;
   C_BACK_PORCH         : natural;
   C_FRONT_PORCH        : natural;
   C_VIDEO_ACTIVE       : natural;
   C_VSYNC_PULSE        : natural);
Port(
   CLK                  : in     std_logic;
   RST                  : in     std_logic;
   VSYNC_VALUE          : out    std_logic_vector(C_VCNT_SIZE - 1 downto 0);
   LCD_EN               : in     std_logic;
   LINE_E               : in     std_logic;
   FRAME_E              : out    std_logic;
   LAST_LINE            : out    std_logic;
   V_DE                 : out    std_logic;
   VSYNC                : out    std_logic);
end component;
 
component video_clk_gen is
Generic (
   POLARITY             : natural);                       -- Define polarity of the output clock signal
port (
   CLK                  : in     std_logic;                    -- Input clock
   RST                  : in     std_logic;                    -- System reset
   CLK_OUT              : out    std_logic);
end component;
 
component video_clk_gen_v4 is
Generic (
   POLARITY             : natural);                       -- Define polarity of the output clock signal
port (
   CLK                  : in     std_logic;                    -- Input clock
   RST                  : in     std_logic;                    -- System reset
   CLK_OUT              : out    std_logic);
end component;
 
component delay is
port (
   CLK                  : in     std_logic;                    -- Input clock
   ADD_DELAY            : in     std_logic_vector(3 downto 0);
   D_IN                 : in     std_logic;
   D_OUT                : out    std_logic);
end component;
 
constant R_MSB                   : natural := 0;
constant G_MSB                   : natural := 6;
constant B_MSB                   : natural := 12;
 
constant VCC                     : std_logic := '1';
constant GND                     : std_logic := '0';
 
signal line_e_i                  : std_logic;
signal hsync_de                  : std_logic;
signal hsync_i                   : std_logic;
signal hsync_d                   : std_logic;
signal vsync_de                  : std_logic;
signal vsync_i                   : std_logic;
signal vsync_d                   : std_logic;
 
signal de_i                      : std_logic;
signal de_d                      : std_logic;
 
BEGIN
 
gen_sp_cp : If (C_FAMILY = "spartan3e") Or (C_FAMILY = "spartan3a") generate
begin
   video_clk_gen_i : entity video_clk_gen
   Generic map (
      POLARITY             => 1)                       -- Define polarity of the output clock signal
   port map (
      CLK                  => VIDEO_CLK_IN,                    -- Input clock
      RST                  => sys_rst,                    -- System reset
      CLK_OUT              => VIDEO_CLK_OUT);
end generate;
 
gen_v_cp : If (C_FAMILY = "virtex4") Or (C_FAMILY = "virtex5fx") Or
              (C_FAMILY = "virtex5lx") generate
begin
 
   video_clk_gen_i : entity video_clk_gen_v4
   Generic map (
      POLARITY             => 1)                       -- Define polarity of the output clock signal
   port map (
      CLK                  => VIDEO_CLK_IN,                    -- Input clock
      RST                  => sys_rst,                    -- System reset
      CLK_OUT              => VIDEO_CLK_OUT);
 
end generate;
 
hsync_g : hsync_gen
Generic map (
   C_HCNT_SIZE          => C_HCNT_SIZE,
   C_BACK_PORCH         => C_HBACK_PORCH,
   C_FRONT_PORCH        => C_HFRONT_PORCH,
   C_VIDEO_ACTIVE       => C_HVIDEO_ACTIVE,
   C_HSYNC_PULSE        => C_HSYNC_PULSE)
Port map(
   CLK                  => VIDEO_CLK_IN,
   RST                  => sys_rst,
   HSYNC_VALUE          => hsync_value,
   HSYNC_EN             => VIDEO_EN,
   LINE_E               => line_e_i,
   DE                   => hsync_de,
   HSYNC                => hsync_i);
 
hsync_delay : delay
port map (
   CLK                  => VIDEO_CLK_IN,
   ADD_DELAY            => X_HSYNC_DELAY,
   D_IN                 => hsync_i,
   D_OUT                => hsync_d);
 
vsync_g : vsync_gen
Generic map (
   C_VCNT_SIZE          => C_VCNT_SIZE,
   C_BACK_PORCH         => C_VBACK_PORCH,
   C_FRONT_PORCH        => C_VFRONT_PORCH,
   C_VIDEO_ACTIVE       => C_VVIDEO_ACTIVE,
   C_VSYNC_PULSE        => C_VSYNC_PULSE)
Port map(
   CLK                  => VIDEO_CLK_IN,
   RST                  => sys_rst,
   VSYNC_VALUE          => vsync_value,
   LCD_EN               => VIDEO_EN,
   LINE_E               => line_e_i,
   FRAME_E              => frame_end,
   LAST_LINE            => last_line,
   V_DE                 => vsync_de,
   VSYNC                => vsync_i);
 
vsync_delay : delay
port map (
   CLK                  => VIDEO_CLK_IN,
   ADD_DELAY            => X_VSYNC_DELAY,
   D_IN                 => vsync_i,
   D_OUT                => vsync_d);
 
de_i <= vsync_de And hsync_de;      -- Valid video
DE <= de_i;
 
de_delay : delay
port map (
   CLK                  => VIDEO_CLK_IN,
   ADD_DELAY            => X_DE_DELAY,
   D_IN                 => de_i,
   D_OUT                => de_d);
 
GEN_VSYNC_OUT : PROCESS(VIDEO_CLK_IN, VSYNC_POL, vsync_d)
BEGIN
   If VIDEO_CLK_IN'event And VIDEO_CLK_IN = '1' Then
      If VSYNC_POL = '1' Then
         VIDEO_VSYNC <= vsync_d;
      Else
         VIDEO_VSYNC <= Not vsync_d;
      End If;
   End If;
END PROCESS;
 
GEN_HSYNC_OUT : PROCESS(VIDEO_CLK_IN, HSYNC_POL, hsync_d)
BEGIN
   If VIDEO_CLK_IN'event And VIDEO_CLK_IN = '1' Then
      If HSYNC_POL = '1' Then
         VIDEO_HSYNC <= hsync_d;
      Else
         VIDEO_HSYNC <= Not hsync_d;
      End If;
   End If;
END PROCESS;
 
GEN_DE_OUT : PROCESS(VIDEO_CLK_IN, DE_POL, de_d)
BEGIN
   If VIDEO_CLK_IN'event And VIDEO_CLK_IN = '1' Then
      If DE_POL = '1' Then
         VIDEO_DE <= de_d;
      Else
         VIDEO_DE <= Not de_d;
      End If;
   End If;
END PROCESS;
 
GEN_DATA_OUT : PROCESS(VIDEO_CLK_IN, DE_POL, de_d)
BEGIN
   If Sys_Rst = '1' Then
      VIDEO_R <= (Others => '0');
      VIDEO_G <= (Others => '0');
      VIDEO_B <= (Others => '0');
   ElsIf VIDEO_CLK_IN'event And VIDEO_CLK_IN = '1' Then
      If de_d = '1' Then
         VIDEO_R <= VIDEO_DATA_R;
         VIDEO_G <= VIDEO_DATA_G;
         VIDEO_B <= VIDEO_DATA_B;
      Else
         VIDEO_R <= (Others => '0');
         VIDEO_G <= (Others => '0');
         VIDEO_B <= (Others => '0');
      End If;
   End If;
END PROCESS;
 
end implementation;
 
 

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Subversion Repositories npigrctrl

[/] [npigrctrl/] [trunk/] [npi_vga_v1_00_b/] [hdl/] [vhdl/] [video_ctrl.vhd] - Blame information for rev 5

Line No.	Rev	Author	Line
1	2	slavek	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- Video Control Module ----`
4			`---- ----`
5			`---- Author(s): ----`
6			`---- - Slavek Valach, s.valach@dspfpga.com ----`
7			`---- ----`
8			`----------------------------------------------------------------------`
9			`---- ----`
10			`---- Copyright (C) 2008 Authors and OPENCORES.ORG ----`
11			`---- ----`
12			`---- This source file may be used and distributed without ----`
13			`---- restriction provided that this copyright statement is not ----`
14			`---- removed from the file and that any derivative work contains ----`
15			`---- the original copyright notice and the associated disclaimer. ----`
16			`---- ----`
17			`---- This source file is free software; you can redistribute it ----`
18			`---- and/or modify it under the terms of the GNU General ----`
19			`---- Public License as published by the Free Software Foundation; ----`
20			`---- either version 2.0 of the License, or (at your option) any ----`
21			`---- later version. ----`
22			`---- ----`
23			`---- This source is distributed in the hope that it will be ----`
24			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
25			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
26			`---- PURPOSE. See the GNU General Public License for more details.----`
27			`---- ----`
28			`---- You should have received a copy of the GNU General ----`
29			`---- Public License along with this source; if not, download it ----`
30			`---- from http://www.gnu.org/licenses/gpl.txt ----`
31			`---- ----`
32			`----------------------------------------------------------------------`
33
34			`library ieee;`
35			`use IEEE.STD_LOGIC_1164.ALL;`
36			`use IEEE.STD_LOGIC_ARITH.ALL;`
37			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
38
39			`-------------------------------------------------------------------------------`
40			`-- Entity section`
41			`-----------------------------------------------------------------------------`
42
43			`entity video_ctrl is`
44			`Generic(`
45			`C_FAMILY : string := "virtex5";`
46			`PIXEL_DEPTH : integer := 6;`
47
48			`C_VCNT_SIZE : natural := 10;`
49			`C_VBACK_PORCH : natural := 25+8;`
50			`C_VFRONT_PORCH : natural := 2+8;`
51			`C_VVIDEO_ACTIVE : natural := 480;`
52			`C_VSYNC_PULSE : natural := 2;`
53
54			`C_HCNT_SIZE : natural := 10;`
55			`C_HBACK_PORCH : natural := 40+8;`
56			`C_HFRONT_PORCH : natural := 8+8+31;`
57			`C_HVIDEO_ACTIVE : natural := 640;`
58			`C_HSYNC_PULSE : natural := 96);`
59
60			`port (`
61			`-- System interface`
62			`Sys_Rst : in std_logic; -- System reset`
63
64			`VSYNC_POL : in std_logic;`
65			`HSYNC_POL : in std_logic;`
66			`DE_POL : in std_logic;`
67
68			`X_HSYNC_DELAY : in std_logic_vector(3 downto 0);`
69			`X_VSYNC_DELAY : in std_logic_vector(3 downto 0);`
70			`X_DE_DELAY : in std_logic_vector(3 downto 0);`
71
72			`VSYNC : out std_logic;`
73			`HSYNC : out std_logic;`
74			`DE : out std_logic;`
75			`VSYNC_VALUE : out std_logic_vector(C_VCNT_SIZE - 1 downto 0);`
76			`HSYNC_VALUE : out std_logic_vector(C_HCNT_SIZE - 1 downto 0);`
77			`LAST_LINE : out std_logic;`
78			`FRAME_END : out std_logic;`
79
80			`VIDEO_EN : in std_logic;`
81			`VIDEO_DATA_R : in std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
82			`VIDEO_DATA_G : in std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
83			`VIDEO_DATA_B : in std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
84			`VIDEO_CLK_IN : in std_logic; -- LCD Clock signal`
85			`VIDEO_VSYNC : out std_logic;`
86			`VIDEO_HSYNC : out std_logic;`
87			`VIDEO_DE : out std_logic;`
88			`VIDEO_CLK_OUT : out std_logic;`
89			`VIDEO_R : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
90			`VIDEO_G : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
91			`VIDEO_B : out std_logic_vector(PIXEL_DEPTH - 1 downto 0);`
92
93			`X_0 : out std_logic;`
94			`X_1 : out std_logic;`
95			`X_2 : out std_logic;`
96			`X_3 : out std_logic;`
97			`X_4 : out std_logic;`
98			`X_5 : out std_logic);`
99
100			`end video_ctrl;`
101
102			`-----------------------------------------------------------------------------`
103			`-- Architecture section`
104			`-----------------------------------------------------------------------------`
105			`architecture implementation of video_ctrl is`
106
107			`constant arch : string := "SPARTAN";`
108
109			`component hsync_gen is`
110			`Generic (`
111			`C_HCNT_SIZE : natural;`
112			`C_BACK_PORCH : natural;`
113			`C_FRONT_PORCH : natural;`
114			`C_VIDEO_ACTIVE : natural;`
115			`C_HSYNC_PULSE : natural);`
116			`Port (`
117			`CLK : in std_logic;`
118			`RST : in std_logic;`
119
120			`HSYNC_VALUE : out std_logic_vector(C_HCNT_SIZE - 1 downto 0);`
121			`HSYNC_EN : in std_logic;`
122			`LINE_E : out std_logic;`
123			`DE : out std_logic;`
124			`HSYNC : out std_logic);`
125			`end component;`
126
127			`component vsync_gen is`
128			`Generic(`
129			`C_VCNT_SIZE : natural;`
130			`C_BACK_PORCH : natural;`
131			`C_FRONT_PORCH : natural;`
132			`C_VIDEO_ACTIVE : natural;`
133			`C_VSYNC_PULSE : natural);`
134			`Port(`
135			`CLK : in std_logic;`
136			`RST : in std_logic;`
137			`VSYNC_VALUE : out std_logic_vector(C_VCNT_SIZE - 1 downto 0);`
138			`LCD_EN : in std_logic;`
139			`LINE_E : in std_logic;`
140			`FRAME_E : out std_logic;`
141			`LAST_LINE : out std_logic;`
142			`V_DE : out std_logic;`
143			`VSYNC : out std_logic);`
144			`end component;`
145
146			`component video_clk_gen is`
147			`Generic (`
148			`POLARITY : natural); -- Define polarity of the output clock signal`
149			`port (`
150			`CLK : in std_logic; -- Input clock`
151			`RST : in std_logic; -- System reset`
152			`CLK_OUT : out std_logic);`
153			`end component;`
154
155			`component video_clk_gen_v4 is`
156			`Generic (`
157			`POLARITY : natural); -- Define polarity of the output clock signal`
158			`port (`
159			`CLK : in std_logic; -- Input clock`
160			`RST : in std_logic; -- System reset`
161			`CLK_OUT : out std_logic);`
162			`end component;`
163
164			`component delay is`
165			`port (`
166			`CLK : in std_logic; -- Input clock`
167			`ADD_DELAY : in std_logic_vector(3 downto 0);`
168			`D_IN : in std_logic;`
169			`D_OUT : out std_logic);`
170			`end component;`
171
172			`constant R_MSB : natural := 0;`
173			`constant G_MSB : natural := 6;`
174			`constant B_MSB : natural := 12;`
175
176			`constant VCC : std_logic := '1';`
177			`constant GND : std_logic := '0';`
178
179			`signal line_e_i : std_logic;`
180			`signal hsync_de : std_logic;`
181			`signal hsync_i : std_logic;`
182			`signal hsync_d : std_logic;`
183			`signal vsync_de : std_logic;`
184			`signal vsync_i : std_logic;`
185			`signal vsync_d : std_logic;`
186
187			`signal de_i : std_logic;`
188			`signal de_d : std_logic;`
189
190			`BEGIN`
191
192			`gen_sp_cp : If (C_FAMILY = "spartan3e") Or (C_FAMILY = "spartan3a") generate`
193			`begin`
194			`video_clk_gen_i : entity video_clk_gen`
195			`Generic map (`
196			`POLARITY => 1) -- Define polarity of the output clock signal`
197			`port map (`
198			`CLK => VIDEO_CLK_IN, -- Input clock`
199			`RST => sys_rst, -- System reset`
200			`CLK_OUT => VIDEO_CLK_OUT);`
201			`end generate;`
202
203			`gen_v_cp : If (C_FAMILY = "virtex4") Or (C_FAMILY = "virtex5fx") Or`
204			`(C_FAMILY = "virtex5lx") generate`
205			`begin`
206
207			`video_clk_gen_i : entity video_clk_gen_v4`
208			`Generic map (`
209			`POLARITY => 1) -- Define polarity of the output clock signal`
210			`port map (`
211			`CLK => VIDEO_CLK_IN, -- Input clock`
212			`RST => sys_rst, -- System reset`
213			`CLK_OUT => VIDEO_CLK_OUT);`
214
215			`end generate;`
216
217			`hsync_g : hsync_gen`
218			`Generic map (`
219			`C_HCNT_SIZE => C_HCNT_SIZE,`
220			`C_BACK_PORCH => C_HBACK_PORCH,`
221			`C_FRONT_PORCH => C_HFRONT_PORCH,`
222			`C_VIDEO_ACTIVE => C_HVIDEO_ACTIVE,`
223			`C_HSYNC_PULSE => C_HSYNC_PULSE)`
224			`Port map(`
225			`CLK => VIDEO_CLK_IN,`
226			`RST => sys_rst,`
227			`HSYNC_VALUE => hsync_value,`
228			`HSYNC_EN => VIDEO_EN,`
229			`LINE_E => line_e_i,`
230			`DE => hsync_de,`
231			`HSYNC => hsync_i);`
232
233			`hsync_delay : delay`
234			`port map (`
235			`CLK => VIDEO_CLK_IN,`
236			`ADD_DELAY => X_HSYNC_DELAY,`
237			`D_IN => hsync_i,`
238			`D_OUT => hsync_d);`
239
240			`vsync_g : vsync_gen`
241			`Generic map (`
242			`C_VCNT_SIZE => C_VCNT_SIZE,`
243			`C_BACK_PORCH => C_VBACK_PORCH,`
244			`C_FRONT_PORCH => C_VFRONT_PORCH,`
245			`C_VIDEO_ACTIVE => C_VVIDEO_ACTIVE,`
246			`C_VSYNC_PULSE => C_VSYNC_PULSE)`
247			`Port map(`
248			`CLK => VIDEO_CLK_IN,`
249			`RST => sys_rst,`
250			`VSYNC_VALUE => vsync_value,`
251			`LCD_EN => VIDEO_EN,`
252			`LINE_E => line_e_i,`
253			`FRAME_E => frame_end,`
254			`LAST_LINE => last_line,`
255			`V_DE => vsync_de,`
256			`VSYNC => vsync_i);`
257
258			`vsync_delay : delay`
259			`port map (`
260			`CLK => VIDEO_CLK_IN,`
261			`ADD_DELAY => X_VSYNC_DELAY,`
262			`D_IN => vsync_i,`
263			`D_OUT => vsync_d);`
264
265			`de_i <= vsync_de And hsync_de; -- Valid video`
266			`DE <= de_i;`
267
268			`de_delay : delay`
269			`port map (`
270			`CLK => VIDEO_CLK_IN,`
271			`ADD_DELAY => X_DE_DELAY,`
272			`D_IN => de_i,`
273			`D_OUT => de_d);`
274
275			`GEN_VSYNC_OUT : PROCESS(VIDEO_CLK_IN, VSYNC_POL, vsync_d)`
276			`BEGIN`
277			`If VIDEO_CLK_IN'event And VIDEO_CLK_IN = '1' Then`
278			`If VSYNC_POL = '1' Then`
279			`VIDEO_VSYNC <= vsync_d;`
280			`Else`
281			`VIDEO_VSYNC <= Not vsync_d;`
282			`End If;`
283			`End If;`
284			`END PROCESS;`
285
286			`GEN_HSYNC_OUT : PROCESS(VIDEO_CLK_IN, HSYNC_POL, hsync_d)`
287			`BEGIN`
288			`If VIDEO_CLK_IN'event And VIDEO_CLK_IN = '1' Then`
289			`If HSYNC_POL = '1' Then`
290			`VIDEO_HSYNC <= hsync_d;`
291			`Else`
292			`VIDEO_HSYNC <= Not hsync_d;`
293			`End If;`
294			`End If;`
295			`END PROCESS;`
296
297			`GEN_DE_OUT : PROCESS(VIDEO_CLK_IN, DE_POL, de_d)`
298			`BEGIN`
299			`If VIDEO_CLK_IN'event And VIDEO_CLK_IN = '1' Then`
300			`If DE_POL = '1' Then`
301			`VIDEO_DE <= de_d;`
302			`Else`
303			`VIDEO_DE <= Not de_d;`
304			`End If;`
305			`End If;`
306			`END PROCESS;`
307
308			`GEN_DATA_OUT : PROCESS(VIDEO_CLK_IN, DE_POL, de_d)`
309			`BEGIN`
310			`If Sys_Rst = '1' Then`
311			`VIDEO_R <= (Others => '0');`
312			`VIDEO_G <= (Others => '0');`
313			`VIDEO_B <= (Others => '0');`
314			`ElsIf VIDEO_CLK_IN'event And VIDEO_CLK_IN = '1' Then`
315			`If de_d = '1' Then`
316			`VIDEO_R <= VIDEO_DATA_R;`
317			`VIDEO_G <= VIDEO_DATA_G;`
318			`VIDEO_B <= VIDEO_DATA_B;`
319			`Else`
320			`VIDEO_R <= (Others => '0');`
321			`VIDEO_G <= (Others => '0');`
322			`VIDEO_B <= (Others => '0');`
323			`End If;`
324			`End If;`
325			`END PROCESS;`
326
327			`end implementation;`
328
329