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[/] [npigrctrl/] [web_uploads/] [npi_eng.vhd] - Blame information for rev 7

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----------------------------------------------------------------------
----                                                              ----
---- NPI DMA Engine                                               ----
----                                                              ----
---- Author(s):                                                   ----
---- - Slavek Valach, s.valach@dspfpga.com                        ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2008 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU General          ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.0 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU General Public License for more details.----
----                                                              ----
---- You should have received a copy of the GNU General           ----
---- Public License along with this source; if not, download it   ----
---- from http://www.gnu.org/licenses/gpl.txt                     ----
----                                                              ----
----------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use npi_vga_v1_00_b.video_cfg.all;
 
entity npi_eng is
generic (
   C_FAMILY                : string := "virtex5";
   C_VD_ADDR               : std_logic_vector := x"00800000";
   C_VD_PIXEL_D            : natural := 32;
   C_VD_STRIDE             : natural := 640;
   C_VD_WIDTH              : natural := 640;
   C_VD_HEIGHT             : natural := 480;
   C_NPI_BURST_SIZE        : natural := 256;
   C_NPI_ADDR_WIDTH        : natural := 32;
   C_NPI_DATA_WIDTH        : natural := 64;
   C_NPI_BE_WIDTH          : natural := 8;
   C_NPI_RDWDADDR_WIDTH    : natural := 4);
port(
 
   NPI_Clk                 : in     std_logic;
   Sys_Clk                 : in     std_logic;
   NPI_RST                 : in     std_logic;
 
   NPI_Addr                : out    std_logic_vector(C_NPI_ADDR_WIDTH - 1 downto 0);
   NPI_AddrReq             : out    std_logic;
   NPI_AddrAck             : in     std_logic;
   NPI_RNW                 : out    std_logic;
   NPI_Size                : out    std_logic_vector(3 downto 0);
   NPI_WrFIFO_Data         : out    std_logic_vector(C_NPI_DATA_WIDTH - 1 downto 0);
   NPI_WrFIFO_BE           : out    std_logic_vector(C_NPI_BE_WIDTH - 1 downto 0);
   NPI_WrFIFO_Push         : out    std_logic;
   NPI_RdFIFO_Data         : in     std_logic_vector(C_NPI_DATA_WIDTH - 1 downto 0);
   NPI_RdFIFO_Pop          : out    std_logic;
   NPI_RdFIFO_RdWdAddr     : in     std_logic_vector(C_NPI_RDWDADDR_WIDTH - 1 downto 0);
   NPI_WrFIFO_Empty        : in     std_logic;
   NPI_WrFIFO_AlmostFull   : in     std_logic;
   NPI_WrFIFO_Flush        : out    std_logic;
   NPI_RdFIFO_Empty        : in     std_logic;
   NPI_RdFIFO_Flush        : out    std_logic;
   NPI_RdFIFO_Latency      : in     std_logic_vector(1 downto 0);
   NPI_RdModWr             : out    std_logic;
   NPI_InitDone            : in     std_logic;
 
   GR_DATA_I               : in     std_logic_vector(31 downto 0);
   GR_DATA_O               : out    std_logic_vector(31 downto 0);
   GR_ADDR                 : in     std_logic_vector(15 downto 0);
   GR_RNW                  : in     std_logic;
   GR_CS                   : in     std_logic;
 
   DMA_INIT                : out    std_logic;
   DMA_DREQ                : in     std_logic;     -- Data request
   DMA_DACK                : out    std_logic;     -- Data ack
   DMA_RSYNC               : in     std_logic;     -- Synchronization reset (restarts the channel)
   DMA_TC                  : out    std_logic;     -- Terminal count (the signal is generated at the end of the transfer)
   DMA_DATA                : out    std_logic_vector(C_NPI_DATA_WIDTH - 1 downto 0);
 
   X                       : out    std_logic_vector(7 downto 0));
end entity;
 
architecture arch_npi_eng of npi_eng is
 
constant BYTES_PER_PIXEL      : natural := (C_VD_PIXEL_D / 8);
constant VD_STRIDE            : natural := C_VD_STRIDE * BYTES_PER_PIXEL;
constant BURST_LENGHT         : natural := (C_VD_WIDTH * BYTES_PER_PIXEL) / C_NPI_BURST_SIZE;
 
signal burst_cnt              : integer range 0 to BURST_LENGHT;
signal burst_cnt_one          : std_logic;
 
signal line_cnt               : integer range 0 to C_VD_HEIGHT;
signal line_cnt_one           : std_logic;
 
signal addr_cnt_i             : std_logic_vector(C_NPI_ADDR_WIDTH - 1 downto 0);
signal line_addr              : std_logic_vector(C_NPI_ADDR_WIDTH - 1 downto 0);
 
signal NPI_AddrReq_i          : std_logic;
signal NPI_RNW_i              : std_logic;
signal NPI_RdFIFO_Pop_i       : std_logic;
 
signal NPI_RST_i              : std_logic;
signal RD_Req                 : std_logic;
 
signal DMA_DataReq            : std_logic;
 
signal dma_dack_d0            : std_logic;
signal dma_dack_d1            : std_logic;
 
signal vd_addr_i              : std_logic_vector(C_NPI_ADDR_WIDTH - 1 downto 0);
 
BEGIN
 
PROCESS(Sys_Clk)
BEGIN
   If Sys_Clk'event And Sys_Clk = '1' Then
      If (NPI_RST_i = '1') Then
         vd_addr_i <= C_VD_ADDR;
      Else
         If gr_cs = '1' And gr_rnw = '0' Then
            vd_addr_i <= GR_DATA_I;
         End If;
      End If;
   End If;
END PROCESS;
 
PROCESS(NPI_Clk)
BEGIN
   If NPI_Clk'event And NPI_Clk = '1' Then
      If (NPI_RST_i = '1') Then
         burst_cnt <= BURST_LENGHT;
      ElsIf NPI_AddrAck = '1' Then
         If burst_cnt_one = '1' Then
            burst_cnt <= BURST_LENGHT;
         Else
            burst_cnt <= burst_cnt - 1;
         End If;
      End If;
   End If;
END PROCESS;
 
burst_cnt_one <= '1' When burst_cnt = 1 Else '0';
 
PROCESS(NPI_Clk)
BEGIN
   If NPI_Clk'event And NPI_Clk = '1' Then
      If (NPI_RST_i = '1') Then
         line_cnt <= C_VD_HEIGHT;
      ElsIf NPI_AddrAck = '1' And burst_cnt_one = '1' Then
         If line_cnt_one = '1' Then
            line_cnt <= C_VD_HEIGHT;
         Else
            line_cnt <= line_cnt - 1;
         End If;
      End If;
   End If;
END PROCESS;
 
line_cnt_one <= '1' When line_cnt = 1 Else '0';
 
PROCESS(NPI_Clk)
BEGIN
   If NPI_Clk'event And NPI_Clk = '1' Then
      If NPI_RST_i = '1' Then
         line_addr <= C_VD_ADDR;
         addr_cnt_i <= C_VD_ADDR;
      ElsIf NPI_AddrAck = '1' Then
         If burst_cnt_one = '1' Then
            If line_cnt_one = '1' Then
               line_addr <= vd_addr_i;
               addr_cnt_i <= vd_addr_i;
            Else
               line_addr <= line_addr + VD_STRIDE;
               addr_cnt_i <= line_addr + VD_STRIDE;
            End If;
         Else
            addr_cnt_i <= addr_cnt_i + C_NPI_BURST_SIZE;
         End If;
      End If;
   End If;
END PROCESS;
 
DMA_DataReq <= DMA_DREQ;
 
NPI_RST_i <= Not NPI_InitDone Or NPI_RST;
 
PROCESS (NPI_Clk)
BEGIN
   If NPI_Clk'event And NPI_CLK = '1' Then
      If NPI_RST_i = '1' Then
         NPI_AddrReq_i <= '0';
      ElsIf RD_Req = '1' Then
         NPI_AddrReq_i <= '1';
      ElsIf NPI_AddrAck = '1' Then
         NPI_AddrReq_i <= '0';
      End If;
   End If;
END PROCESS;
 
NPI_RNW_i <= NPI_AddrReq_i;
NPI_RNW <= NPI_RNW_i;
NPI_AddrReq <= NPI_AddrReq_i;
 
RD_Req <= '1' When NPI_AddrAck = '0' And DMA_DataReq = '1' Else '0';
 
NPI_RdFIFO_Pop_i <= Not NPI_RdFIFO_Empty;
 
NPI_Addr                <= addr_cnt_i;
NPI_Size                <= get_NPI_Size(C_NPI_DATA_WIDTH, C_NPI_BURST_SIZE);
NPI_WrFIFO_Data         <= (Others => '0');
NPI_WrFIFO_BE           <= (Others => '0');
NPI_WrFIFO_Push         <= '0';
NPI_WrFIFO_Flush        <= '0';
NPI_RdFIFO_Flush        <= NPI_RST_i;
NPI_RdModWr             <= '0';
 
NPI_RdFIFO_Pop <= NPI_RdFIFO_Pop_i;
 
-- Data are fliped
DMA_DATA <= NPI_RdFIFO_Data(31 downto 0) & NPI_RdFIFO_Data(63 downto 32) When C_NPI_DATA_WIDTH = 64
            Else NPI_RdFIFO_Data(31 downto 0);
 
PROCESS (NPI_Clk)
BEGIN
   If NPI_Clk'event And NPI_CLK = '1' Then
      If NPI_RST_i = '1' Then
         dma_dack_d0 <= '0';
         dma_dack_d1 <= '0';
      Else
         dma_dack_d0 <= NPI_RdFIFO_Empty;
         dma_dack_d1 <= dma_dack_d0;
      End If;
   End If;
END PROCESS;
 
DMA_DACK <= Not NPI_RdFIFO_Empty When NPI_RdFIFO_Latency = "00" Else
            Not dma_dack_d0 When NPI_RdFIFO_Latency = "01" Else
            Not dma_dack_d1 When NPI_RdFIFO_Latency = "10" Else '0';
 
DMA_INIT <= NPI_InitDone;
 
X(0) <= NPI_AddrReq_i;
X(1) <= NPI_RNW_i;
X(2) <= NPI_AddrAck;
X(3) <= NPI_RdFIFO_Empty;
X(4) <= NPI_RdFIFO_Pop_i;
 
end arch_npi_eng;
 

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Subversion Repositories npigrctrl

[/] [npigrctrl/] [web_uploads/] [npi_eng.vhd] - Blame information for rev 7

Line No.	Rev	Author	Line
1	7	root	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- NPI DMA Engine ----`
4			`---- ----`
5			`---- Author(s): ----`
6			`---- - Slavek Valach, s.valach@dspfpga.com ----`
7			`---- ----`
8			`----------------------------------------------------------------------`
9			`---- ----`
10			`---- Copyright (C) 2008 Authors and OPENCORES.ORG ----`
11			`---- ----`
12			`---- This source file may be used and distributed without ----`
13			`---- restriction provided that this copyright statement is not ----`
14			`---- removed from the file and that any derivative work contains ----`
15			`---- the original copyright notice and the associated disclaimer. ----`
16			`---- ----`
17			`---- This source file is free software; you can redistribute it ----`
18			`---- and/or modify it under the terms of the GNU General ----`
19			`---- Public License as published by the Free Software Foundation; ----`
20			`---- either version 2.0 of the License, or (at your option) any ----`
21			`---- later version. ----`
22			`---- ----`
23			`---- This source is distributed in the hope that it will be ----`
24			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
25			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
26			`---- PURPOSE. See the GNU General Public License for more details.----`
27			`---- ----`
28			`---- You should have received a copy of the GNU General ----`
29			`---- Public License along with this source; if not, download it ----`
30			`---- from http://www.gnu.org/licenses/gpl.txt ----`
31			`---- ----`
32			`----------------------------------------------------------------------`
33
34			`LIBRARY ieee;`
35			`USE ieee.std_logic_1164.all;`
36			`use ieee.std_logic_unsigned.all;`
37			`use npi_vga_v1_00_b.video_cfg.all;`
38
39			`entity npi_eng is`
40			`generic (`
41			`C_FAMILY : string := "virtex5";`
42			`C_VD_ADDR : std_logic_vector := x"00800000";`
43			`C_VD_PIXEL_D : natural := 32;`
44			`C_VD_STRIDE : natural := 640;`
45			`C_VD_WIDTH : natural := 640;`
46			`C_VD_HEIGHT : natural := 480;`
47			`C_NPI_BURST_SIZE : natural := 256;`
48			`C_NPI_ADDR_WIDTH : natural := 32;`
49			`C_NPI_DATA_WIDTH : natural := 64;`
50			`C_NPI_BE_WIDTH : natural := 8;`
51			`C_NPI_RDWDADDR_WIDTH : natural := 4);`
52			`port(`
53
54			`NPI_Clk : in std_logic;`
55			`Sys_Clk : in std_logic;`
56			`NPI_RST : in std_logic;`
57
58			`NPI_Addr : out std_logic_vector(C_NPI_ADDR_WIDTH - 1 downto 0);`
59			`NPI_AddrReq : out std_logic;`
60			`NPI_AddrAck : in std_logic;`
61			`NPI_RNW : out std_logic;`
62			`NPI_Size : out std_logic_vector(3 downto 0);`
63			`NPI_WrFIFO_Data : out std_logic_vector(C_NPI_DATA_WIDTH - 1 downto 0);`
64			`NPI_WrFIFO_BE : out std_logic_vector(C_NPI_BE_WIDTH - 1 downto 0);`
65			`NPI_WrFIFO_Push : out std_logic;`
66			`NPI_RdFIFO_Data : in std_logic_vector(C_NPI_DATA_WIDTH - 1 downto 0);`
67			`NPI_RdFIFO_Pop : out std_logic;`
68			`NPI_RdFIFO_RdWdAddr : in std_logic_vector(C_NPI_RDWDADDR_WIDTH - 1 downto 0);`
69			`NPI_WrFIFO_Empty : in std_logic;`
70			`NPI_WrFIFO_AlmostFull : in std_logic;`
71			`NPI_WrFIFO_Flush : out std_logic;`
72			`NPI_RdFIFO_Empty : in std_logic;`
73			`NPI_RdFIFO_Flush : out std_logic;`
74			`NPI_RdFIFO_Latency : in std_logic_vector(1 downto 0);`
75			`NPI_RdModWr : out std_logic;`
76			`NPI_InitDone : in std_logic;`
77
78			`GR_DATA_I : in std_logic_vector(31 downto 0);`
79			`GR_DATA_O : out std_logic_vector(31 downto 0);`
80			`GR_ADDR : in std_logic_vector(15 downto 0);`
81			`GR_RNW : in std_logic;`
82			`GR_CS : in std_logic;`
83
84			`DMA_INIT : out std_logic;`
85			`DMA_DREQ : in std_logic; -- Data request`
86			`DMA_DACK : out std_logic; -- Data ack`
87			`DMA_RSYNC : in std_logic; -- Synchronization reset (restarts the channel)`
88			`DMA_TC : out std_logic; -- Terminal count (the signal is generated at the end of the transfer)`
89			`DMA_DATA : out std_logic_vector(C_NPI_DATA_WIDTH - 1 downto 0);`
90
91			`X : out std_logic_vector(7 downto 0));`
92			`end entity;`
93
94			`architecture arch_npi_eng of npi_eng is`
95
96			`constant BYTES_PER_PIXEL : natural := (C_VD_PIXEL_D / 8);`
97			`constant VD_STRIDE : natural := C_VD_STRIDE * BYTES_PER_PIXEL;`
98			`constant BURST_LENGHT : natural := (C_VD_WIDTH * BYTES_PER_PIXEL) / C_NPI_BURST_SIZE;`
99
100			`signal burst_cnt : integer range 0 to BURST_LENGHT;`
101			`signal burst_cnt_one : std_logic;`
102
103			`signal line_cnt : integer range 0 to C_VD_HEIGHT;`
104			`signal line_cnt_one : std_logic;`
105
106			`signal addr_cnt_i : std_logic_vector(C_NPI_ADDR_WIDTH - 1 downto 0);`
107			`signal line_addr : std_logic_vector(C_NPI_ADDR_WIDTH - 1 downto 0);`
108
109			`signal NPI_AddrReq_i : std_logic;`
110			`signal NPI_RNW_i : std_logic;`
111			`signal NPI_RdFIFO_Pop_i : std_logic;`
112
113			`signal NPI_RST_i : std_logic;`
114			`signal RD_Req : std_logic;`
115
116			`signal DMA_DataReq : std_logic;`
117
118			`signal dma_dack_d0 : std_logic;`
119			`signal dma_dack_d1 : std_logic;`
120
121			`signal vd_addr_i : std_logic_vector(C_NPI_ADDR_WIDTH - 1 downto 0);`
122
123			`BEGIN`
124
125			`PROCESS(Sys_Clk)`
126			`BEGIN`
127			`If Sys_Clk'event And Sys_Clk = '1' Then`
128			`If (NPI_RST_i = '1') Then`
129			`vd_addr_i <= C_VD_ADDR;`
130			`Else`
131			`If gr_cs = '1' And gr_rnw = '0' Then`
132			`vd_addr_i <= GR_DATA_I;`
133			`End If;`
134			`End If;`
135			`End If;`
136			`END PROCESS;`
137
138			`PROCESS(NPI_Clk)`
139			`BEGIN`
140			`If NPI_Clk'event And NPI_Clk = '1' Then`
141			`If (NPI_RST_i = '1') Then`
142			`burst_cnt <= BURST_LENGHT;`
143			`ElsIf NPI_AddrAck = '1' Then`
144			`If burst_cnt_one = '1' Then`
145			`burst_cnt <= BURST_LENGHT;`
146			`Else`
147			`burst_cnt <= burst_cnt - 1;`
148			`End If;`
149			`End If;`
150			`End If;`
151			`END PROCESS;`
152
153			`burst_cnt_one <= '1' When burst_cnt = 1 Else '0';`
154
155			`PROCESS(NPI_Clk)`
156			`BEGIN`
157			`If NPI_Clk'event And NPI_Clk = '1' Then`
158			`If (NPI_RST_i = '1') Then`
159			`line_cnt <= C_VD_HEIGHT;`
160			`ElsIf NPI_AddrAck = '1' And burst_cnt_one = '1' Then`
161			`If line_cnt_one = '1' Then`
162			`line_cnt <= C_VD_HEIGHT;`
163			`Else`
164			`line_cnt <= line_cnt - 1;`
165			`End If;`
166			`End If;`
167			`End If;`
168			`END PROCESS;`
169
170			`line_cnt_one <= '1' When line_cnt = 1 Else '0';`
171
172			`PROCESS(NPI_Clk)`
173			`BEGIN`
174			`If NPI_Clk'event And NPI_Clk = '1' Then`
175			`If NPI_RST_i = '1' Then`
176			`line_addr <= C_VD_ADDR;`
177			`addr_cnt_i <= C_VD_ADDR;`
178			`ElsIf NPI_AddrAck = '1' Then`
179			`If burst_cnt_one = '1' Then`
180			`If line_cnt_one = '1' Then`
181			`line_addr <= vd_addr_i;`
182			`addr_cnt_i <= vd_addr_i;`
183			`Else`
184			`line_addr <= line_addr + VD_STRIDE;`
185			`addr_cnt_i <= line_addr + VD_STRIDE;`
186			`End If;`
187			`Else`
188			`addr_cnt_i <= addr_cnt_i + C_NPI_BURST_SIZE;`
189			`End If;`
190			`End If;`
191			`End If;`
192			`END PROCESS;`
193
194			`DMA_DataReq <= DMA_DREQ;`
195
196			`NPI_RST_i <= Not NPI_InitDone Or NPI_RST;`
197
198			`PROCESS (NPI_Clk)`
199			`BEGIN`
200			`If NPI_Clk'event And NPI_CLK = '1' Then`
201			`If NPI_RST_i = '1' Then`
202			`NPI_AddrReq_i <= '0';`
203			`ElsIf RD_Req = '1' Then`
204			`NPI_AddrReq_i <= '1';`
205			`ElsIf NPI_AddrAck = '1' Then`
206			`NPI_AddrReq_i <= '0';`
207			`End If;`
208			`End If;`
209			`END PROCESS;`
210
211			`NPI_RNW_i <= NPI_AddrReq_i;`
212			`NPI_RNW <= NPI_RNW_i;`
213			`NPI_AddrReq <= NPI_AddrReq_i;`
214
215			`RD_Req <= '1' When NPI_AddrAck = '0' And DMA_DataReq = '1' Else '0';`
216
217			`NPI_RdFIFO_Pop_i <= Not NPI_RdFIFO_Empty;`
218
219			`NPI_Addr <= addr_cnt_i;`
220			`NPI_Size <= get_NPI_Size(C_NPI_DATA_WIDTH, C_NPI_BURST_SIZE);`
221			`NPI_WrFIFO_Data <= (Others => '0');`
222			`NPI_WrFIFO_BE <= (Others => '0');`
223			`NPI_WrFIFO_Push <= '0';`
224			`NPI_WrFIFO_Flush <= '0';`
225			`NPI_RdFIFO_Flush <= NPI_RST_i;`
226			`NPI_RdModWr <= '0';`
227
228			`NPI_RdFIFO_Pop <= NPI_RdFIFO_Pop_i;`
229
230			`-- Data are fliped`
231			`DMA_DATA <= NPI_RdFIFO_Data(31 downto 0) & NPI_RdFIFO_Data(63 downto 32) When C_NPI_DATA_WIDTH = 64`
232			`Else NPI_RdFIFO_Data(31 downto 0);`
233
234			`PROCESS (NPI_Clk)`
235			`BEGIN`
236			`If NPI_Clk'event And NPI_CLK = '1' Then`
237			`If NPI_RST_i = '1' Then`
238			`dma_dack_d0 <= '0';`
239			`dma_dack_d1 <= '0';`
240			`Else`
241			`dma_dack_d0 <= NPI_RdFIFO_Empty;`
242			`dma_dack_d1 <= dma_dack_d0;`
243			`End If;`
244			`End If;`
245			`END PROCESS;`
246
247			`DMA_DACK <= Not NPI_RdFIFO_Empty When NPI_RdFIFO_Latency = "00" Else`
248			`Not dma_dack_d0 When NPI_RdFIFO_Latency = "01" Else`
249			`Not dma_dack_d1 When NPI_RdFIFO_Latency = "10" Else '0';`
250
251			`DMA_INIT <= NPI_InitDone;`
252
253			`X(0) <= NPI_AddrReq_i;`
254			`X(1) <= NPI_RNW_i;`
255			`X(2) <= NPI_AddrAck;`
256			`X(3) <= NPI_RdFIFO_Empty;`
257			`X(4) <= NPI_RdFIFO_Pop_i;`
258
259			`end arch_npi_eng;`
260