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[/] [numbert_sort_device/] [trunk/] [main/] [dynamic_tree.sv] - Blame information for rev 6

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module Dyna_Tree ( clk, glob_com, dataIn, dataOut );
 
parameter HBIT= 3;
parameter TREE_LEVEL= 4;
parameter IMRIGHT= 0;
 
input clk;
input [1:0] glob_com;
 
output TPort dataOut;
input  TPort dataIn;
 
 
TPort fromLeft;
TPort fromRight;
 
Cell_DT_Inner #( HBIT, IMRIGHT ) inner ( clk, glob_com, dataIn, fromLeft, fromRight, dataOut );
 
generate
if ( TREE_LEVEL >0 )
begin
        Dyna_Tree #( HBIT, TREE_LEVEL-1, 0 ) leftSubTree  ( clk, glob_com, dataOut, fromLeft );
        Dyna_Tree #( HBIT, TREE_LEVEL-1, 1 ) rightSubTree ( clk, glob_com, dataOut, fromRight );
end
else
begin
        assign fromLeft.msg =VMS_STOP;
        assign fromRight.msg=VMS_STOP;
end
endgenerate
 
 
endmodule
 
 
 
 
 
 
typedef enum bit[3:0] {         VK_EMPTY=4'h0,
                                                VK_EOF,
                                                VK_DUMMY1,
                                                VK_DUMMY2,
                                                VK_DUMMY3,
                                                VK_DUMMY4,
                                                VK_DUMMY5,
                                                VK_APPLY,
                                                VK_K,
                                                VK_DUMMY6,
                                                VK_DUMMY7,
                                                VK_DUMMY8,
                                                VK_DUMMY9
                } VKind;
 
typedef enum bit[3:0] {         VMS_EMPTY=4'h0,
                                                VMS_EOF,
                                                VMS_READY,
                                                VMS_WRITE,
                                                VMS_READ,
                                                VMS_STOP                //      end of tree
                } VMeta;
 
typedef enum bit[1:0]{  TO_PARENT=2'h0,
                                                TO_CHILDREN,
                                                TO_LEFT,
                                                TO_RIGHT
                } VTarget;
 
typedef struct{
bit     [3:0] msg;
bit     [1:0] tgt;
                } TPort;
 
 
 
 
 
 
 
module Cell_DT_Inner ( clk, glob_com, i_fromParent, i_fromLeft, i_fromRight, message );
parameter HBIT= 7;
parameter IMRIGHT= 0;
 
input clk;
input [1:0] glob_com;
 
input  TPort i_fromParent;
input  TPort i_fromLeft;
input  TPort i_fromRight;
 
wire [HBIT:0] fromParent= ((IMRIGHT==0) && ( i_fromParent.tgt == TO_CHILDREN || i_fromParent.tgt == TO_LEFT )) ||
                                                          ((IMRIGHT==1) && ( i_fromParent.tgt == TO_CHILDREN || i_fromParent.tgt == TO_RIGHT ))
                                                          ? i_fromParent.msg : 4'h0;
 
wire [HBIT:0] fromLeft=   ( i_fromLeft.tgt == TO_PARENT  ) ? i_fromLeft.msg  : 4'h0;
wire [HBIT:0] fromRight=  ( i_fromRight.tgt == TO_PARENT ) ? i_fromRight.msg : 4'h0;
 
reg [HBIT:0] value;
output TPort message;
VMeta        state;
reg [3:0] step;
 
always@(posedge clk )
begin
        case( glob_com )
        0:                                                              //      working mode
        begin
                case( state )
                VMS_EMPTY:                                      //      sleeping
                begin
                        value <=  fromParent==VK_APPLY || fromParent==VK_K ? fromParent : VK_DUMMY9;            //      write self
                        case( fromParent )
                        VK_EMPTY:;                                      //      still sleeping
                        VK_APPLY:                                       //      write subtrees
                                state <= VMS_WRITE;
                        default:                                                //      i'm a leaf
                        begin
                                message.msg <= VMS_READY;
                                message.tgt <= TO_PARENT;
                                state       <= VMS_READY;
                        end
                        endcase
                end
 
                VMS_WRITE:
                begin
                        case( step )
                        0:                                                                      //      writing left
                                if ( fromLeft == VMS_EMPTY )
                                begin                                                           //      write left
                                        message.msg <= fromParent;
                                        message.tgt <= TO_LEFT;
                                end
                                else
                                begin                                                           //      begin writing right
                                        message.msg <= fromParent;
                                        message.tgt <= TO_RIGHT;
                                        step        <= step+4'h1;
                                end
                        1:                                                                      //      writing right
                                if ( fromRight == VMS_EMPTY )
                                begin                                                           //      write right
                                        message.msg <= fromParent;
                                        message.tgt <= TO_RIGHT;
                                end
                                else
                                begin                                                           //      job well done, notify parent
                                        message.msg <= VMS_READY;
                                        message.tgt <= TO_PARENT;
                                        state       <= VMS_READY;
                                        step        <= 0;
                                end
                        endcase
                end
 
                VMS_READ:
                begin
                        case( step )
                        0:
                        if ( value != VK_APPLY )
                        begin
                                message.msg <= VK_EOF;          //      leaf's report
                                message.tgt <= TO_PARENT;
                                state       <= VMS_READY;
                        end
                        else if ( fromLeft==VMS_READY )
                        begin
                                message.msg <= VMS_READ;        //      begin read left
                                message.tgt <= TO_LEFT;
                                step        <= 4'h1;
                        end
                        else
                                message.msg <= VK_EMPTY;        //      wait for left
                        1:
                                case( fromLeft )
                                VK_EMPTY:;
                                VK_EOF:
                                begin
                                        step        <= 4'h2;
                                        message.msg <= VK_EMPTY;
                                end
                                default:                                                        //      transfer left
                                begin
                                        message.msg <= fromLeft;
                                        message.tgt <= TO_PARENT;
                                end
                                endcase
                        2:                                                                      //      begin read right
                        if ( fromRight==VMS_READY )
                        begin
                                message.msg <= VMS_READ;
                                message.tgt <= TO_RIGHT;
                                step        <= 4'h3;
                        end
                        else
                                message.msg <= VK_EMPTY;        //      wait for right
                        3:
                                case( fromRight )
                                VK_EMPTY:;
                                VK_EOF:
                                begin
                                        message.msg <= fromRight;
                                        state       <= VMS_READY;
                                        step        <= 0;
                                end
                                default:                                                        //      transfer right
                                begin
                                        message.msg <= fromRight;
                                        message.tgt <= TO_PARENT;
                                end
                                endcase
                        endcase
                end
 
                VMS_READY:
                begin
                        case( fromParent )
                        VMS_READ:                                               //      read self
                        begin
                                message.msg <= value;
                                message.tgt <= TO_PARENT;
                                state       <= VMS_READ;
                        end
                        default:
                        begin
                                message.msg <= VMS_READY;
                                message.tgt <= TO_PARENT;
                        end
                        endcase
                end
                endcase
        end
        default:                                                                //      reset mode
        begin
                state    <= VMS_EMPTY;
                message.msg  <= VMS_EMPTY;
                step            <= 0;
        end
        endcase
end
 
endmodule
 
 
 

Line No.	Rev	Author	Line
1	5	leshabiruk
2	6	leshabiruk
3
4
5
6	5	leshabiruk	`module Dyna_Tree ( clk, glob_com, dataIn, dataOut );`
7
8	6	leshabiruk	`parameter HBIT= 3;`
9	5	leshabiruk	`parameter TREE_LEVEL= 4;`
10	6	leshabiruk	`parameter IMRIGHT= 0;`
11	5	leshabiruk
12			`input clk;`
13			`input [1:0] glob_com;`
14
15	6	leshabiruk	`output TPort dataOut;`
16			`input TPort dataIn;`
17	5	leshabiruk
18
19	6	leshabiruk	`TPort fromLeft;`
20			`TPort fromRight;`
21	5	leshabiruk
22	6	leshabiruk	`Cell_DT_Inner #( HBIT, IMRIGHT ) inner ( clk, glob_com, dataIn, fromLeft, fromRight, dataOut );`
23
24	5	leshabiruk	`generate`
25			`if ( TREE_LEVEL >0 )`
26			`begin`
27	6	leshabiruk	`Dyna_Tree #( HBIT, TREE_LEVEL-1, 0 ) leftSubTree ( clk, glob_com, dataOut, fromLeft );`
28			`Dyna_Tree #( HBIT, TREE_LEVEL-1, 1 ) rightSubTree ( clk, glob_com, dataOut, fromRight );`
29	5	leshabiruk	`end`
30			`else`
31			`begin`
32	6	leshabiruk	`assign fromLeft.msg =VMS_STOP;`
33			`assign fromRight.msg=VMS_STOP;`
34	5	leshabiruk	`end`
35			`endgenerate`
36
37
38			`endmodule`
39
40
41	6	leshabiruk
42
43
44
45			`typedef enum bit[3:0] { VK_EMPTY=4'h0,`
46			`VK_EOF,`
47			`VK_DUMMY1,`
48			`VK_DUMMY2,`
49			`VK_DUMMY3,`
50			`VK_DUMMY4,`
51			`VK_DUMMY5,`
52			`VK_APPLY,`
53			`VK_K,`
54			`VK_DUMMY6,`
55			`VK_DUMMY7,`
56			`VK_DUMMY8,`
57			`VK_DUMMY9`
58			`} VKind;`
59
60			`typedef enum bit[3:0] { VMS_EMPTY=4'h0,`
61			`VMS_EOF,`
62			`VMS_READY,`
63	5	leshabiruk	`VMS_WRITE,`
64	6	leshabiruk	`VMS_READ,`
65			`VMS_STOP // end of tree`
66	5	leshabiruk	`} VMeta;`
67
68	6	leshabiruk	`typedef enum bit[1:0]{ TO_PARENT=2'h0,`
69			`TO_CHILDREN,`
70			`TO_LEFT,`
71			`TO_RIGHT`
72			`} VTarget;`
73
74			`typedef struct{`
75			`bit [3:0] msg;`
76			`bit [1:0] tgt;`
77			`} TPort;`
78
79
80
81
82
83
84
85			`module Cell_DT_Inner ( clk, glob_com, i_fromParent, i_fromLeft, i_fromRight, message );`
86	5	leshabiruk	`parameter HBIT= 7;`
87	6	leshabiruk	`parameter IMRIGHT= 0;`
88	5	leshabiruk
89			`input clk;`
90			`input [1:0] glob_com;`
91
92	6	leshabiruk	`input TPort i_fromParent;`
93			`input TPort i_fromLeft;`
94			`input TPort i_fromRight;`
95	5	leshabiruk
96	6	leshabiruk	`wire [HBIT:0] fromParent= ((IMRIGHT==0) && ( i_fromParent.tgt == TO_CHILDREN \|\| i_fromParent.tgt == TO_LEFT )) \|\|`
97			`((IMRIGHT==1) && ( i_fromParent.tgt == TO_CHILDREN \|\| i_fromParent.tgt == TO_RIGHT ))`
98			`? i_fromParent.msg : 4'h0;`
99	5	leshabiruk
100	6	leshabiruk	`wire [HBIT:0] fromLeft= ( i_fromLeft.tgt == TO_PARENT ) ? i_fromLeft.msg : 4'h0;`
101			`wire [HBIT:0] fromRight= ( i_fromRight.tgt == TO_PARENT ) ? i_fromRight.msg : 4'h0;`
102
103	5	leshabiruk	`reg [HBIT:0] value;`
104	6	leshabiruk	`output TPort message;`
105	5	leshabiruk	`VMeta state;`
106	6	leshabiruk	`reg [3:0] step;`
107	5	leshabiruk
108			`always@(posedge clk )`
109			`begin`
110	6	leshabiruk	`case( glob_com )`
111			`0: // working mode`
112			`begin`
113			`case( state )`
114			`VMS_EMPTY: // sleeping`
115	5	leshabiruk	`begin`
116	6	leshabiruk	`value <= fromParent==VK_APPLY \|\| fromParent==VK_K ? fromParent : VK_DUMMY9; // write self`
117			`case( fromParent )`
118			`VK_EMPTY:; // still sleeping`
119			`VK_APPLY: // write subtrees`
120			`state <= VMS_WRITE;`
121			`default: // i'm a leaf`
122			`begin`
123			`message.msg <= VMS_READY;`
124			`message.tgt <= TO_PARENT;`
125			`state <= VMS_READY;`
126			`end`
127			`endcase`
128	5	leshabiruk	`end`
129	6	leshabiruk
130			`VMS_WRITE:`
131	5	leshabiruk	`begin`
132	6	leshabiruk	`case( step )`
133			`0: // writing left`
134			`if ( fromLeft == VMS_EMPTY )`
135			`begin // write left`
136			`message.msg <= fromParent;`
137			`message.tgt <= TO_LEFT;`
138			`end`
139			`else`
140			`begin // begin writing right`
141			`message.msg <= fromParent;`
142			`message.tgt <= TO_RIGHT;`
143			`step <= step+4'h1;`
144			`end`
145			`1: // writing right`
146			`if ( fromRight == VMS_EMPTY )`
147			`begin // write right`
148			`message.msg <= fromParent;`
149			`message.tgt <= TO_RIGHT;`
150			`end`
151			`else`
152			`begin // job well done, notify parent`
153			`message.msg <= VMS_READY;`
154			`message.tgt <= TO_PARENT;`
155			`state <= VMS_READY;`
156			`step <= 0;`
157			`end`
158			`endcase`
159	5	leshabiruk	`end`
160	6	leshabiruk
161			`VMS_READ:`
162			`begin`
163			`case( step )`
164			`0:`
165			`if ( value != VK_APPLY )`
166			`begin`
167			`message.msg <= VK_EOF; // leaf's report`
168			`message.tgt <= TO_PARENT;`
169			`state <= VMS_READY;`
170			`end`
171			`else if ( fromLeft==VMS_READY )`
172			`begin`
173			`message.msg <= VMS_READ; // begin read left`
174			`message.tgt <= TO_LEFT;`
175			`step <= 4'h1;`
176			`end`
177			`else`
178			`message.msg <= VK_EMPTY; // wait for left`
179			`1:`
180			`case( fromLeft )`
181			`VK_EMPTY:;`
182			`VK_EOF:`
183			`begin`
184			`step <= 4'h2;`
185			`message.msg <= VK_EMPTY;`
186			`end`
187			`default: // transfer left`
188			`begin`
189			`message.msg <= fromLeft;`
190			`message.tgt <= TO_PARENT;`
191			`end`
192			`endcase`
193			`2: // begin read right`
194			`if ( fromRight==VMS_READY )`
195			`begin`
196			`message.msg <= VMS_READ;`
197			`message.tgt <= TO_RIGHT;`
198			`step <= 4'h3;`
199			`end`
200			`else`
201			`message.msg <= VK_EMPTY; // wait for right`
202			`3:`
203			`case( fromRight )`
204			`VK_EMPTY:;`
205			`VK_EOF:`
206			`begin`
207			`message.msg <= fromRight;`
208			`state <= VMS_READY;`
209			`step <= 0;`
210			`end`
211			`default: // transfer right`
212			`begin`
213			`message.msg <= fromRight;`
214			`message.tgt <= TO_PARENT;`
215			`end`
216			`endcase`
217			`endcase`
218			`end`
219
220			`VMS_READY:`
221			`begin`
222			`case( fromParent )`
223			`VMS_READ: // read self`
224			`begin`
225			`message.msg <= value;`
226			`message.tgt <= TO_PARENT;`
227			`state <= VMS_READ;`
228			`end`
229			`default:`
230			`begin`
231			`message.msg <= VMS_READY;`
232			`message.tgt <= TO_PARENT;`
233			`end`
234			`endcase`
235			`end`
236			`endcase`
237			`end`
238			`default: // reset mode`
239			`begin`
240			`state <= VMS_EMPTY;`
241			`message.msg <= VMS_EMPTY;`
242			`step <= 0;`
243			`end`
244	5	leshabiruk	`endcase`
245			`end`
246
247			`endmodule`
248
249
250

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[/] [numbert_sort_device/] [trunk/] [main/] [dynamic_tree.sv] - Blame information for rev 6