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module Dyna_Tree ( clk, glob_com, dataIn, dataOut );
 
parameter HBIT= 3;
parameter TREE_LEVEL= 4;
parameter IMRIGHT= 0;
 
input clk;
input [1:0] glob_com;
 
output TPort dataOut;
input  TPort dataIn;
 
 
TPort fromLeft;
TPort fromRight;
 
Cell_DT_Inner #( HBIT, IMRIGHT ) inner ( clk, glob_com, dataIn, fromLeft, fromRight, dataOut );
 
generate
if ( TREE_LEVEL >0 )
begin
        Dyna_Tree #( HBIT, TREE_LEVEL-1, 0 ) leftSubTree  ( clk, glob_com, dataOut, fromLeft );
        Dyna_Tree #( HBIT, TREE_LEVEL-1, 1 ) rightSubTree ( clk, glob_com, dataOut, fromRight );
end
else
begin
        assign fromLeft.msg =VMS_STOP;
        assign fromRight.msg=VMS_STOP;
end
endgenerate
 
 
endmodule
 
 
 
 
 
 
typedef enum bit[3:0] {         VK_EMPTY=4'h0,
                                                VK_DUMMY1,
                                                VK_DUMMY2,
                                                VK_DUMMY3,
 
                                                VK_DUMMY4,
                                                VK_TRANSIT,
                                                VK_APPLY,
                                                VK_EOF,
 
                                                VK_K[2]= 4'h8,
 
                                                VK_S[3]= 4'd12,
                                                VK_DUMMY5
                } VKind;
 
function logic [1:0] CH_NUM( logic [3:0] k );
CH_NUM = k[1:0];
endfunction
 
typedef enum bit[3:0] {         VMS_EMPTY=4'h0,
                                                VMS_READY,
                                                VMS_PROCESS,
                                                VMS_BOMB,
 
                                                VMS_READ,
                                                VMS_APPLY,
                                                VMS_STOP                //      end of tree
                } VMeta;
 
typedef enum bit[1:0]{  TO_PARENT=2'h0,
                                                TO_CHILDREN,
                                                TO_LEFT,
                                                TO_RIGHT
                } VTarget;
 
typedef struct{
bit     [3:0] msg;
bit     [1:0] tgt;
                } TPort;
 
 
 
 
 
 
 
module Cell_DT_Inner ( clk, glob_com, i_fromParent, i_fromLeft, i_fromRight, message );
parameter HBIT= 7;
parameter IMRIGHT= 0;
 
input clk;
input [1:0] glob_com;
 
input  TPort i_fromParent;
input  TPort i_fromLeft;
input  TPort i_fromRight;
 
wire [HBIT:0] fromParent= ((IMRIGHT==0) && ( i_fromParent.tgt == TO_CHILDREN || i_fromParent.tgt == TO_LEFT )) ||
                                                          ((IMRIGHT==1) && ( i_fromParent.tgt == TO_CHILDREN || i_fromParent.tgt == TO_RIGHT ))
                                                          ? i_fromParent.msg : 4'h0;
 
wire [HBIT:0] fromLeft=   ( i_fromLeft.tgt == TO_PARENT  ) ? i_fromLeft.msg  : 4'h0;
wire [HBIT:0] fromRight=  ( i_fromRight.tgt == TO_PARENT ) ? i_fromRight.msg : 4'h0;
 
reg [HBIT:0] value;
output TPort message;
VMeta        state;
reg [3:0] step;
 
always@(posedge clk )
begin
        case( glob_com )
        0:                                                              //      working mode
        begin
                case( state )
                VMS_EMPTY:                                      //      sleeping
                begin
                        if ( !value )
                        begin   //      writing left
                                value <=  fromParent;//==VK_APPLY || fromParent==VK_EMPTY || fromParent==VK_K0 ? fromParent : VK_DUMMY5;                //      write self
                                if ( fromParent && CH_NUM( fromParent )==0 )
                                begin
                                        message.msg <= VMS_READY;
                                        message.tgt <= TO_PARENT;
                                        state       <= VMS_READY;
                                end
                        end
                        else if ( CH_NUM( value )!=0 && ~fromLeft[0] )
                        begin                                                           //      write left
                                message.msg <= fromParent;
                                message.tgt <= TO_LEFT;
                        end
                        else if ( CH_NUM( value )==2 && ~fromRight[0] )
                        begin                                                           //      begin writing right
                                message.msg <= fromParent;
                                message.tgt <= TO_RIGHT;
                        end
                        else
                        begin
                                message.msg <= VMS_READY;
                                message.tgt <= TO_PARENT;
                                state       <= VMS_READY;
                        end
                end
 
                VMS_READ:
                begin
                        if ( message.msg == VK_EOF )
                        begin
                                message.msg <= VMS_READY;               //      end read 2
                                state       <= VMS_READY;
                        end
//                      else if ( message.msg == VMS_READY && value != VK_TRANSIT )
//                      begin
//                              message.msg <= value;           //      read self
//                              message.tgt <= TO_PARENT;
//                      end
                        else if ( CH_NUM( value )==0 )
                        begin
                                message.msg <= VK_EOF;          //      end read 1.1
                        end
                        else if ( ~step[0] && fromLeft == VMS_READY )
                        begin
                                message.msg <= VMS_READ;                //      command left
                                message.tgt <= TO_LEFT;
                        end
                        else if ( ~step[0] && fromLeft != VK_EOF )
                        begin
                                message.msg <= fromLeft;                //      transfer left
                                message.tgt <= TO_PARENT;
                        end
                        else if ( CH_NUM( value )==1 )
                        begin
                                message.msg <= VK_EOF;          //      end read 1.2
                        end
                        else if ( fromRight == VMS_READY )
                        begin
                                message.msg <= VMS_READ;                //      command right
                                message.tgt <= TO_RIGHT;
                                step[0] <= 1;
                        end
                        else if ( fromRight != VK_EOF )
                        begin
                                message.msg <= fromRight;               //      transfer right
                                message.tgt <= TO_PARENT;
                        end
                        else
                        begin
                                message.msg <= VK_EOF;          //      end read 1.3
                                step[0] <= 0;
                        end
 
 
                end
 
                VMS_READY:
                begin
                        case( fromParent )
                        VMS_BOMB:                                               //      clear
                        begin
                                message.msg <= VMS_BOMB;
                                message.tgt <= TO_CHILDREN;
                                state           <= VMS_EMPTY;
                                value           <= VK_EMPTY;
                        end
                        VMS_READ:                                               //      read self
                        begin
                                if ( value != VK_TRANSIT )
                                begin
                                        message.msg <= value;
                                        message.tgt <= TO_PARENT;
                                end
                                state       <= VMS_READ;
                        end
                        VMS_APPLY:                                              //      apply string from parent to itself
                        begin
                                if ( CH_NUM( value )!=0 )
                                begin
                                        message.msg <= VMS_APPLY;
                                        message.tgt <= TO_CHILDREN;
                                end
                                begin
                                        case( value )
                                        VK_K0,
                                        VK_S0,
                                        VK_S1:
                                        begin                                                                 //        add argument
                                                value[1:0] <= value[1:0] +1;	//	K0 -> K1, S0 -> S1, S1 -> S2
                                                state      <= VMS_EMPTY;                //      WRITE
                                        end
                                        VK_K1:                                                  //      K main
                                        begin
                                                value       <= VK_TRANSIT;
                                                state       <= VMS_READY;
                                                message.msg <= VMS_BOMB;
                                                message.tgt <= TO_RIGHT;
                                        end
                                        VK_S2:                                                  //      S main
                                        begin
                                                state       <= VMS_APPLY;
                                        end
                                        endcase
                                end
                        end
                        default:
                        begin
                                message.msg <= VMS_READY;
                                message.tgt <= TO_PARENT;
                        end
                        endcase
                end
 
                VMS_APPLY:
                if ( fromParent != VK_EOF )
                begin
                        message.msg <= fromParent;	//	Sxyz -> `(_`_xz) (_`_yz)
                        message.tgt <= TO_CHILDREN;
                end
                else
                begin
                        message.msg <= VK_EMPTY;
                        state       <= VMS_READY;
                        value                   <= VK_APPLY;	//	Sxyz -> _`_ (`xz) (`yz)
                end
                endcase
        end
        default:                                                                //      reset mode
        begin
                state    <= VMS_EMPTY;
                value    <= VK_EMPTY;
                message.msg  <= VMS_EMPTY;
                step            <= 0;
        end
        endcase
end
 
endmodule
 
 
 

Line No.	Rev	Author	Line
1	5	leshabiruk
2	6	leshabiruk
3
4
5
6	5	leshabiruk	`module Dyna_Tree ( clk, glob_com, dataIn, dataOut );`
7
8	6	leshabiruk	`parameter HBIT= 3;`
9	5	leshabiruk	`parameter TREE_LEVEL= 4;`
10	6	leshabiruk	`parameter IMRIGHT= 0;`
11	5	leshabiruk
12			`input clk;`
13			`input [1:0] glob_com;`
14
15	6	leshabiruk	`output TPort dataOut;`
16			`input TPort dataIn;`
17	5	leshabiruk
18
19	6	leshabiruk	`TPort fromLeft;`
20			`TPort fromRight;`
21	5	leshabiruk
22	6	leshabiruk	`Cell_DT_Inner #( HBIT, IMRIGHT ) inner ( clk, glob_com, dataIn, fromLeft, fromRight, dataOut );`
23
24	5	leshabiruk	`generate`
25			`if ( TREE_LEVEL >0 )`
26			`begin`
27	6	leshabiruk	`Dyna_Tree #( HBIT, TREE_LEVEL-1, 0 ) leftSubTree ( clk, glob_com, dataOut, fromLeft );`
28			`Dyna_Tree #( HBIT, TREE_LEVEL-1, 1 ) rightSubTree ( clk, glob_com, dataOut, fromRight );`
29	5	leshabiruk	`end`
30			`else`
31			`begin`
32	6	leshabiruk	`assign fromLeft.msg =VMS_STOP;`
33			`assign fromRight.msg=VMS_STOP;`
34	5	leshabiruk	`end`
35			`endgenerate`
36
37
38			`endmodule`
39
40
41	6	leshabiruk
42
43
44
45			`typedef enum bit[3:0] { VK_EMPTY=4'h0,`
46			`VK_DUMMY1,`
47			`VK_DUMMY2,`
48			`VK_DUMMY3,`
49	7	leshabiruk
50	6	leshabiruk	`VK_DUMMY4,`
51	7	leshabiruk	`VK_TRANSIT,`
52	6	leshabiruk	`VK_APPLY,`
53	7	leshabiruk	`VK_EOF,`
54
55			`VK_K[2]= 4'h8,`
56
57			`VK_S[3]= 4'd12,`
58			`VK_DUMMY5`
59	6	leshabiruk	`} VKind;`
60
61	7	leshabiruk	`function logic [1:0] CH_NUM( logic [3:0] k );`
62			`CH_NUM = k[1:0];`
63			`endfunction`
64
65	6	leshabiruk	`typedef enum bit[3:0] { VMS_EMPTY=4'h0,`
66			`VMS_READY,`
67	7	leshabiruk	`VMS_PROCESS,`
68			`VMS_BOMB,`
69
70	6	leshabiruk	`VMS_READ,`
71	7	leshabiruk	`VMS_APPLY,`
72	6	leshabiruk	`VMS_STOP // end of tree`
73	5	leshabiruk	`} VMeta;`
74
75	6	leshabiruk	`typedef enum bit[1:0]{ TO_PARENT=2'h0,`
76			`TO_CHILDREN,`
77			`TO_LEFT,`
78			`TO_RIGHT`
79			`} VTarget;`
80
81			`typedef struct{`
82			`bit [3:0] msg;`
83			`bit [1:0] tgt;`
84			`} TPort;`
85
86
87
88
89
90
91
92			`module Cell_DT_Inner ( clk, glob_com, i_fromParent, i_fromLeft, i_fromRight, message );`
93	5	leshabiruk	`parameter HBIT= 7;`
94	6	leshabiruk	`parameter IMRIGHT= 0;`
95	5	leshabiruk
96			`input clk;`
97			`input [1:0] glob_com;`
98
99	6	leshabiruk	`input TPort i_fromParent;`
100			`input TPort i_fromLeft;`
101			`input TPort i_fromRight;`
102	5	leshabiruk
103	6	leshabiruk	`wire [HBIT:0] fromParent= ((IMRIGHT==0) && ( i_fromParent.tgt == TO_CHILDREN \|\| i_fromParent.tgt == TO_LEFT )) \|\|`
104			`((IMRIGHT==1) && ( i_fromParent.tgt == TO_CHILDREN \|\| i_fromParent.tgt == TO_RIGHT ))`
105			`? i_fromParent.msg : 4'h0;`
106	5	leshabiruk
107	6	leshabiruk	`wire [HBIT:0] fromLeft= ( i_fromLeft.tgt == TO_PARENT ) ? i_fromLeft.msg : 4'h0;`
108			`wire [HBIT:0] fromRight= ( i_fromRight.tgt == TO_PARENT ) ? i_fromRight.msg : 4'h0;`
109
110	5	leshabiruk	`reg [HBIT:0] value;`
111	6	leshabiruk	`output TPort message;`
112	5	leshabiruk	`VMeta state;`
113	6	leshabiruk	`reg [3:0] step;`
114	5	leshabiruk
115			`always@(posedge clk )`
116			`begin`
117	6	leshabiruk	`case( glob_com )`
118			`0: // working mode`
119			`begin`
120			`case( state )`
121			`VMS_EMPTY: // sleeping`
122	5	leshabiruk	`begin`
123	7	leshabiruk	`if ( !value )`
124			`begin // writing left`
125			`value <= fromParent;//==VK_APPLY \|\| fromParent==VK_EMPTY \|\| fromParent==VK_K0 ? fromParent : VK_DUMMY5; // write self`
126			`if ( fromParent && CH_NUM( fromParent )==0 )`
127			`begin`
128			`message.msg <= VMS_READY;`
129			`message.tgt <= TO_PARENT;`
130			`state <= VMS_READY;`
131			`end`
132			`end`
133			`else if ( CH_NUM( value )!=0 && ~fromLeft[0] )`
134			`begin // write left`
135			`message.msg <= fromParent;`
136			`message.tgt <= TO_LEFT;`
137			`end`
138			`else if ( CH_NUM( value )==2 && ~fromRight[0] )`
139			`begin // begin writing right`
140			`message.msg <= fromParent;`
141			`message.tgt <= TO_RIGHT;`
142			`end`
143			`else`
144	6	leshabiruk	`begin`
145			`message.msg <= VMS_READY;`
146			`message.tgt <= TO_PARENT;`
147			`state <= VMS_READY;`
148			`end`
149	5	leshabiruk	`end`
150	6	leshabiruk
151			`VMS_READ:`
152			`begin`
153	7	leshabiruk	`if ( message.msg == VK_EOF )`
154	6	leshabiruk	`begin`
155	7	leshabiruk	`message.msg <= VMS_READY; // end read 2`
156	6	leshabiruk	`state <= VMS_READY;`
157			`end`
158	7	leshabiruk	`// else if ( message.msg == VMS_READY && value != VK_TRANSIT )`
159			`// begin`
160			`// message.msg <= value; // read self`
161			`// message.tgt <= TO_PARENT;`
162			`// end`
163			`else if ( CH_NUM( value )==0 )`
164	6	leshabiruk	`begin`
165	7	leshabiruk	`message.msg <= VK_EOF; // end read 1.1`
166			`end`
167			`else if ( ~step[0] && fromLeft == VMS_READY )`
168			`begin`
169			`message.msg <= VMS_READ; // command left`
170	6	leshabiruk	`message.tgt <= TO_LEFT;`
171			`end`
172	7	leshabiruk	`else if ( ~step[0] && fromLeft != VK_EOF )`
173	6	leshabiruk	`begin`
174	7	leshabiruk	`message.msg <= fromLeft; // transfer left`
175			`message.tgt <= TO_PARENT;`
176			`end`
177			`else if ( CH_NUM( value )==1 )`
178			`begin`
179			`message.msg <= VK_EOF; // end read 1.2`
180			`end`
181			`else if ( fromRight == VMS_READY )`
182			`begin`
183			`message.msg <= VMS_READ; // command right`
184	6	leshabiruk	`message.tgt <= TO_RIGHT;`
185	7	leshabiruk	`step[0] <= 1;`
186	6	leshabiruk	`end`
187	7	leshabiruk	`else if ( fromRight != VK_EOF )`
188			`begin`
189			`message.msg <= fromRight; // transfer right`
190			`message.tgt <= TO_PARENT;`
191			`end`
192	6	leshabiruk	`else`
193	7	leshabiruk	`begin`
194			`message.msg <= VK_EOF; // end read 1.3`
195			`step[0] <= 0;`
196			`end`
197
198
199	6	leshabiruk	`end`
200
201			`VMS_READY:`
202			`begin`
203			`case( fromParent )`
204	7	leshabiruk	`VMS_BOMB: // clear`
205			`begin`
206			`message.msg <= VMS_BOMB;`
207			`message.tgt <= TO_CHILDREN;`
208			`state <= VMS_EMPTY;`
209			`value <= VK_EMPTY;`
210			`end`
211	6	leshabiruk	`VMS_READ: // read self`
212			`begin`
213	7	leshabiruk	`if ( value != VK_TRANSIT )`
214			`begin`
215			`message.msg <= value;`
216			`message.tgt <= TO_PARENT;`
217			`end`
218	6	leshabiruk	`state <= VMS_READ;`
219			`end`
220	7	leshabiruk	`VMS_APPLY: // apply string from parent to itself`
221			`begin`
222			`if ( CH_NUM( value )!=0 )`
223			`begin`
224			`message.msg <= VMS_APPLY;`
225			`message.tgt <= TO_CHILDREN;`
226			`end`
227			`begin`
228			`case( value )`
229			`VK_K0,`
230			`VK_S0,`
231			`VK_S1:`
232			`begin // add argument`
233			`value[1:0] <= value[1:0] +1; // K0 -> K1, S0 -> S1, S1 -> S2`
234			`state <= VMS_EMPTY; // WRITE`
235			`end`
236			`VK_K1: // K main`
237			`begin`
238			`value <= VK_TRANSIT;`
239			`state <= VMS_READY;`
240			`message.msg <= VMS_BOMB;`
241			`message.tgt <= TO_RIGHT;`
242			`end`
243			`VK_S2: // S main`
244			`begin`
245			`state <= VMS_APPLY;`
246			`end`
247			`endcase`
248			`end`
249			`end`
250	6	leshabiruk	`default:`
251			`begin`
252			`message.msg <= VMS_READY;`
253			`message.tgt <= TO_PARENT;`
254			`end`
255			`endcase`
256			`end`
257	7	leshabiruk
258			`VMS_APPLY:`
259			`if ( fromParent != VK_EOF )`
260			`begin`
261			message.msg <= fromParent; // Sxyz -> `(_`_xz) (_`_yz)
262			`message.tgt <= TO_CHILDREN;`
263			`end`
264			`else`
265			`begin`
266			`message.msg <= VK_EMPTY;`
267			`state <= VMS_READY;`
268			value <= VK_APPLY; // Sxyz -> _`_ (`xz) (`yz)
269			`end`
270	6	leshabiruk	`endcase`
271			`end`
272			`default: // reset mode`
273			`begin`
274			`state <= VMS_EMPTY;`
275	7	leshabiruk	`value <= VK_EMPTY;`
276	6	leshabiruk	`message.msg <= VMS_EMPTY;`
277			`step <= 0;`
278			`end`
279	5	leshabiruk	`endcase`
280			`end`
281
282			`endmodule`
283
284
285

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[/] [numbert_sort_device/] [trunk/] [main/] [dynamic_tree.sv] - Blame information for rev 7