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[/] [numbert_sort_device/] [trunk/] [main/] [high_end.sv] - Blame information for rev 2

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1 2 leshabiruk 
 
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module Cell_life ( clk, cell_rst,       in_mm, in_m0, in_mp,
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                                                                                in_0m,        in_0p,
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                                                                                in_pm, in_p0, in_pp, init,
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                                                                                                                                        state );
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input clk;
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input cell_rst;
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input in_mm;
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input in_m0;
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input in_mp;
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input in_0m;
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input in_0p;
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input in_pm;
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input in_p0;
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input in_pp;
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input init;
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output reg state;
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always@(posedge clk )
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begin
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        if ( cell_rst )
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        begin
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                state<= init;
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        end
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        else
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        begin
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                state <= (state |       (  in_mm+ in_m0+ in_mp+
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                                                                                in_0m+        in_0p+
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                                                                                in_pm+ in_p0+ in_pp ))==3;
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        end
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end
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endmodule
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module VGA_HighEnd ( clk, rst,
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                                                                iX_video, iY_video,
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                                                                oR_video, oG_video, oB_video,
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                                                                tumblers, endFrame, dbg_val     );
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parameter RES_X_H= 1240;
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parameter RES_Y_H= 1024;
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parameter XY_STEP_H= 7;
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parameter RES_X_L= 640;
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parameter RES_Y_L= 480;
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parameter XY_STEP_L= 8;
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input clk;
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input rst;
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input signed [11:0] iX_video;
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input signed [11:0] iY_video;
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output reg [7:0] oR_video;
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output reg [7:0] oG_video;
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output reg [7:0] oB_video;
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input   [9:0]                   tumblers;
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input endFrame;
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output wire [63:0] dbg_val= count;
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wire [31:0] V_out2;
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wire high_res= 1;
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reg [31:0] count;
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reg [31:0] count_py;
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parameter R_SZ= 27;
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parameter R_SZp= R_SZ +1;
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wire  cell_out[R_SZ:0][R_SZ:0];
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wire  cell_in_mm[R_SZ:0][R_SZ:0];
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wire  cell_in_m0[R_SZ:0][R_SZ:0];
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wire  cell_in_mp[R_SZ:0][R_SZ:0];
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wire  cell_in_0m[R_SZ:0][R_SZ:0];
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wire  cell_in_0p[R_SZ:0][R_SZ:0];
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wire  cell_in_pm[R_SZ:0][R_SZ:0];
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wire  cell_in_p0[R_SZ:0][R_SZ:0];
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wire  cell_in_pp[R_SZ:0][R_SZ:0];
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wire  ribbon_init[R_SZ:0][R_SZ:0];
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//wire [R_SZ:0] token_in;
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//wire [R_SZ:0] token_out;
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wire cell_rst= (iY_video==1);
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wire cell_clk= (iX_video==1 && iY_video %R_SZp==1);
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Cell_life ribbon[R_SZ:0][R_SZ:0] ( cell_clk, cell_rst, cell_in_mm, cell_in_m0, cell_in_mp,
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                                                                                                                                                cell_in_0m,                     cell_in_0p,
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                                                                                                                                cell_in_pm, cell_in_p0, cell_in_pp, ribbon_init, cell_out );
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generate
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  genvar i,j;
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  for (i=0; i<=R_SZ; i=i+1)
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  begin : block_name01
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          for (j=0; j<=R_SZ; j=j+1)
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          begin : block_name02
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                        if ( i==R_SZp/2 && j>=8 && j<24 )
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                                assign ribbon_init[i][j]= 1;
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                        else if ( i==R_SZp/2 && j>=3 && j<24 )
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                                assign ribbon_init[i][j]= tumblers[j-3];
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                        else
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                                assign ribbon_init[i][j]= 0;
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          end
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  end
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  for (i=0; i<=R_SZ; i=i+1)
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  begin : block_name1
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          for (j=0; j
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          begin : block_name2
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                 assign cell_in_m0[i][j+1]= cell_out[i][j];
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                 assign cell_in_0m[j+1][i]= cell_out[j][i];
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                 assign cell_in_p0[i][j]= cell_out[i][j+1];
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                 assign cell_in_0p[j][i]= cell_out[j+1][i];
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          end
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          assign cell_in_m0[i][0]= 0;
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          assign cell_in_mm[i][0]= 0;
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          assign cell_in_0m[0][i]= 0;
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          assign cell_in_p0[i][R_SZ]= 0;
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          assign cell_in_0p[R_SZ][i]= 0;
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  end
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  for (i=0; i
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  begin : block21
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          for (j=0; j
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          begin : block22
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                 assign cell_in_mm[i+1][j+1]= cell_out[i][j];
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                 assign cell_in_mp[i][j+1]= cell_out[i+1][j];
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                 assign cell_in_pm[i+1][j]= cell_out[i][j+1];
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                 assign cell_in_pp[i][j]= cell_out[i+1][j+1];
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          end
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  end
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//  begin : block_name1
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//  end
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endgenerate
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always@(posedge clk or posedge rst)
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begin
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        if ( rst )
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        begin
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                count= 0;
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        end
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        else
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        begin
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                if ( iX_video==1 && iY_video==1 )
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                begin
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                        count<= count +1;
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                end
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                else if ( iX_video==1 )
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                begin
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                        count_py<= count_py +1;
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                end
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                oR_video= {8{cell_out[ iX_video ][ iY_video % (R_SZ+1) ]}};
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                oG_video= {8{cell_out[ iX_video ][ iY_video % (R_SZ+1) ]}};
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                oB_video= {8{cell_out[ iX_video ][ iY_video % (R_SZ+1) ]}};
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        end
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end
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endmodule
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module Cell_110 ( clk, rst, in_m, in_p, out_0, broad );
180 
 
181 
input clk;
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input rst;
183 
 
184 
input in_m;
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input in_p;
186 
 
187 
output out_0= state;
188 
 
189 
input broad;
190 
 
191 
//input token_in;
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//output reg token_out;
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reg state;
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195 
always@(posedge clk or posedge rst)
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begin
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        if ( rst )
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        begin
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                state<= broad;
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        end
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        else
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        begin
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                case( { in_m, state, in_p })
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                        3'd0: state <= 0;
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                        3'd1: state <= 0;
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                        3'd2: state <= 1;
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                        3'd3: state <= 1;
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                        3'd4: state <= 1;
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                        3'd5: state <= 1;
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                        3'd6: state <= 1;
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                        3'd7: state <= 0;
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                endcase
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        end
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end
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endmodule
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module VGA_HighEnd_2 ( clk, rst,
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                                                                iX_video, iY_video,
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                                                                oR_video, oG_video, oB_video,
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                                                                tumblers, endFrame, dbg_val     );
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parameter RES_X_H= 1240;
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parameter RES_Y_H= 1024;
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parameter XY_STEP_H= 7;
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parameter RES_X_L= 640;
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parameter RES_Y_L= 480;
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parameter XY_STEP_L= 8;
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232 
input clk;
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input rst;
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input signed [11:0] iX_video;
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input signed [11:0] iY_video;
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output reg [7:0] oR_video;
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output reg [7:0] oG_video;
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output reg [7:0] oB_video;
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input   [9:0]                   tumblers;
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input endFrame;
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output wire [63:0] dbg_val= count;
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244 
wire [31:0] V_out2;
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246 
wire high_res= 1;
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248 
reg [31:0] count;
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reg [31:0] count_py;
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wire signed [11:0] x;
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wire signed [11:0] y;
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assign x= (iX_video- (high_res ? RES_X_H/2 :RES_X_L/2 ));
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assign y= (iY_video- (high_res ? RES_Y_H/2 :RES_Y_L/2 ));
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parameter R_SZ= 1280;
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259 
wire [R_SZ:0] cell_out;
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wire [R_SZ:0] cell_in_m;
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wire [R_SZ:0] cell_in_p;
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wire [R_SZ:0] ribbon_init;
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//wire [R_SZ:0] token_in;
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//wire [R_SZ:0] token_out;
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wire cell_rst= (iY_video==1);
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wire cell_clk= (iX_video==1);
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268 
Cell_110 ribbon[R_SZ:0] ( cell_clk, cell_rst, cell_in_m, cell_in_p, cell_out, ribbon_init );
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270 
assign ribbon_init[99:0] =0;
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assign ribbon_init[125:100] =count[31:6];
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assign ribbon_init[R_SZ:126] =0;
273 
//
274 
//assign ribbon_init[99:0] =0;
275 
//assign ribbon_init[125:100] =count[31:6];
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//assign ribbon_init[R_SZ:126] =0;
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278 
generate
279 
  genvar i;
280 
  for (i=0; i
281 
  begin : block_name
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         assign cell_in_m[i+1]= cell_out[i];
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         assign cell_in_p[i]= cell_out[i+1];
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  end
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//  begin : block_name1
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  assign cell_in_m[0]= 0;
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  assign cell_in_p[R_SZ]= 0;
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//  end
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endgenerate
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always@(posedge clk or posedge rst)
292 
begin
293 
        if ( rst )
294 
        begin
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                count= 0;
296 
        end
297 
        else
298 
        begin
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                if ( iX_video==1 && iY_video==1 )
300 
                begin
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                        count<= count +1;
302 
                end
303 
                else if ( iX_video==1 )
304 
                begin
305 
                        count_py<= count_py +1;
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                end
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308 
                oR_video= {8{cell_out[ iX_video ]}};
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                oG_video= {8{cell_out[ iX_video ]}};
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                oB_video= {8{cell_out[ iX_video ]}};
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        end
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end
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endmodule
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