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cospan |
//faux_sata_hd.v
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/*
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Distributed under the MIT license.
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Copyright (c) 2011 Dave McCoy (dave.mccoy@cospandesign.com)
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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this software and associated documentation files (the "Software"), to deal in
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the Software without restriction, including without limitation the rights to
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is furnished to do
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so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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*/
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`include "sata_defines.v"
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module faux_sata_hd (
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//Inputs/Outputs
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input rst, //reset
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input clk,
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//Data Interface
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output [31:0] tx_dout,
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output [3:0] tx_isk,
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output tx_set_elec_idle,
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output rx_byte_is_aligned,
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input [31:0] rx_din,
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input [3:0] rx_isk,
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input rx_is_elec_idle,
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input comm_reset_detect,
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input comm_wake_detect,
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output tx_comm_reset,
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output tx_comm_wake,
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output hd_ready,
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output phy_ready,
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//Debug
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output [3:0] oob_state,
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output [3:0] cl_state,
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//Link Layer
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input dbg_ll_write_start,
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output dbg_ll_write_strobe,
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output dbg_ll_write_finished,
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input [31:0] dbg_ll_write_data,
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input [31:0] dbg_ll_write_size,
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input dbg_ll_write_hold,
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input dbg_ll_write_abort,
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output dbg_ll_xmit_error,
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output dbg_ll_read_start,
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output dbg_ll_read_strobe,
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output [31:0] dbg_ll_read_data,
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input dbg_ll_read_ready,
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output dbg_ll_read_finished,
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output dbg_ll_remote_abort,
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input dbg_data_scrambler_en,
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input dbg_hold,
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//Transport Layer Debug
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input dbg_t_en,
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//Trasport Layer Control/Status
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output dbg_tl_ready,
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input dbg_send_reg_stb,
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input dbg_send_dma_act_stb,
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input dbg_send_data_stb,
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input dbg_send_pio_stb,
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input dbg_send_dev_bits_stb,
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output dbg_remote_abort,
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output dbg_xmit_error,
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output dbg_read_crc_fail,
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output dbg_h2d_reg_stb,
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output dbg_h2d_data_stb,
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output dbg_pio_request,
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input [15:0] dbg_pio_transfer_count,
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input dbg_pio_direction,
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input [7:0] dbg_pio_e_status,
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//FIS Structure
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output [7:0] dbg_h2d_command,
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output [15:0] dbg_h2d_features,
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output dbg_h2d_cmd_bit,
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output [3:0] dbg_h2d_port_mult,
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output [7:0] dbg_h2d_control,
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output [7:0] dbg_h2d_device,
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output [47:0] dbg_h2d_lba,
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output [15:0] dbg_h2d_sector_count,
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input dbg_d2h_interrupt,
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input dbg_d2h_notification,
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input [7:0] dbg_d2h_status,
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input [7:0] dbg_d2h_error,
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input [3:0] dbg_d2h_port_mult,
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input [7:0] dbg_d2h_device,
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input [47:0] dbg_d2h_lba,
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input [15:0] dbg_d2h_sector_count,
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//command layer data interface
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output dbg_cl_if_strobe,
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input [31:0] dbg_cl_if_data,
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input dbg_cl_if_ready,
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output dbg_cl_if_activate,
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input [23:0] dbg_cl_if_size,
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output dbg_cl_of_strobe,
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output [31:0] dbg_cl_of_data,
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input [1:0] dbg_cl_of_ready,
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output [1:0] dbg_cl_of_activate,
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input [23:0] dbg_cl_of_size,
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output command_layer_ready,
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output hd_read_from_host,
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output [31:0] hd_data_from_host,
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output hd_write_to_host,
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input [31:0] hd_data_to_host
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);
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//Parameters
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//Registers/Wires
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wire [31:0] phy_tx_dout;
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wire phy_tx_isk;
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wire [31:0] sll_tx_dout;
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wire sll_tx_isk;
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wire ll_ready;
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wire ll_write_start;
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wire ll_write_finished;
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wire ll_write_strobe;
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wire [31:0] ll_write_data;
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wire [31:0] ll_write_size;
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wire ll_write_hold;
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wire ll_write_abort;
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wire ll_read_start;
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wire ll_read_strobe;
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wire [31:0] ll_read_data;
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wire ll_remote_abort;
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wire ll_read_ready;
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wire ll_read_finished;
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wire ll_read_crc_ok;
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wire data_scrambler_en;
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//Command Layer
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wire cl_send_reg_stb;
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wire cl_send_dma_act_stb;
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wire cl_send_data_stb;
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wire cl_send_pio_stb;
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wire cl_send_dev_bits_stb;
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wire [15:0] cl_pio_transfer_count;
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wire cl_pio_direction;
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wire [7:0] cl_pio_e_status;
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wire cl_d2h_interrupt;
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wire cl_d2h_notification;
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wire [7:0] cl_d2h_status;
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wire [7:0] cl_d2h_error;
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wire [3:0] cl_d2h_port_mult;
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wire [7:0] cl_d2h_device;
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wire [47:0] cl_d2h_lba;
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wire [15:0] cl_d2h_sector_count;
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//Trasport Layer Control/Status
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wire transport_layer_ready;
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wire send_reg_stb;
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wire send_dma_act_stb;
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wire send_data_stb;
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wire send_pio_stb;
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wire send_dev_bits_stb;
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wire remote_abort;
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wire xmit_error;
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wire read_crc_fail;
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wire h2d_reg_stb;
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wire h2d_data_stb;
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wire pio_request;
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wire [15:0] pio_transfer_count;
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wire pio_direction;
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wire [7:0] pio_e_status;
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wire [31:0] if_data;
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wire if_ready;
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wire [23:0] if_size;
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wire [1:0] of_ready;
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wire [23:0] of_size;
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//Host to Device Registers
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wire [7:0] h2d_command;
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wire [15:0] h2d_features;
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wire h2d_cmd_bit;
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wire [7:0] h2d_control;
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wire [3:0] h2d_port_mult;
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wire [7:0] h2d_device;
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wire [47:0] h2d_lba;
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wire [15:0] h2d_sector_count;
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//Device to Host Registers
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wire d2h_interrupt;
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wire d2h_notification;
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wire [3:0] d2h_port_mult;
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wire [7:0] d2h_device;
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wire [47:0] d2h_lba;
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wire [15:0] d2h_sector_count;
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wire [7:0] d2h_status;
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wire [7:0] d2h_error;
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//DMA Specific Control
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//Data Control
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wire cl_if_ready;
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wire cl_if_activate;
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wire [23:0] cl_if_size;
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wire cl_if_strobe;
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wire [31:0] cl_if_data;
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wire [1:0] cl_of_ready;
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wire [1:0] cl_of_activate;
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wire cl_of_strobe;
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wire [31:0] cl_of_data;
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wire [23:0] cl_of_size;
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//Link Layer Interface
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wire t_write_start;
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wire t_write_strobe;
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wire t_write_finished;
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wire [31:0] t_write_data;
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wire [31:0] t_write_size;
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wire t_write_hold;
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wire t_write_abort;
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wire t_xmit_error;
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wire t_read_start;
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wire t_read_ready;
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wire [31:0] t_read_data;
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wire t_read_strobe;
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wire t_read_finished;
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wire t_read_crc_ok;
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wire t_remote_abort;
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//Sub Modules
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faux_sata_hd_phy hd_phy(
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.rst (rst ),
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.clk (clk ),
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//incomming/output data
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.tx_dout (phy_tx_dout ),
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.tx_isk (phy_tx_isk ),
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.tx_set_elec_idle (tx_set_elec_idle ),
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.rx_din (rx_din ),
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.rx_isk (rx_isk ),
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.rx_is_elec_idle (rx_is_elec_idle ),
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.rx_byte_is_aligned (rx_byte_is_aligned ),
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.comm_reset_detect (comm_reset_detect ),
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.comm_wake_detect (comm_wake_detect ),
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.tx_comm_reset (tx_comm_reset ),
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.tx_comm_wake (tx_comm_wake ),
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//Status
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.lax_state (oob_state ),
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.phy_ready (phy_ready ),
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.hd_ready (hd_ready )
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);
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sata_link_layer fsll (
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.rst (rst || !hd_ready ),
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.clk (clk ),
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.prim_scrambler_en (1 ),
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.data_scrambler_en (data_scrambler_en ),
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.link_layer_ready (ll_ready ),
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.sync_escape (0 ),
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.hold (dbg_hold ),
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//Transport Layer Interface
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.write_start (ll_write_start ),
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.write_strobe (ll_write_strobe ),
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.write_data (ll_write_data ),
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.write_size (ll_write_size ),
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.write_hold (ll_write_hold ),
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.write_finished (ll_write_finished ),
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.write_abort (ll_write_abort ),
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.xmit_error (t_xmit_error ),
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.read_strobe (ll_read_strobe ),
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.read_data (ll_read_data ),
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.read_ready (ll_read_ready ),
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.read_start (ll_read_start ),
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.read_finished (ll_read_finished ),
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.read_crc_ok (ll_read_crc_ok ),
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.remote_abort (ll_remote_abort ),
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//Phy Layer
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.phy_ready (phy_ready ),
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.platform_ready (hd_ready ),
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.tx_dout (sll_tx_dout ),
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.tx_isk (sll_tx_isk ),
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.rx_din (rx_din ),
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.rx_isk (rx_isk ),
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.is_device (1 )
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);
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faux_sata_hd_transport ftl (
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.rst (rst || !hd_ready ),
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.clk (clk ),
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//Trasport Layer Control/Status
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.transport_layer_ready(transport_layer_ready ),
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.send_reg_stb (send_reg_stb ),
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.send_dma_act_stb (send_dma_act_stb ),
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.send_data_stb (send_data_stb ),
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.send_pio_stb (send_pio_stb ),
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352 |
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.send_dev_bits_stb (send_dev_bits_stb ),
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.remote_abort (remote_abort ),
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.xmit_error (xmit_error ),
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356 |
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.read_crc_fail (read_crc_fail ),
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357 |
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|
|
358 |
|
|
.h2d_reg_stb (h2d_reg_stb ),
|
359 |
|
|
.h2d_data_stb (h2d_data_stb ),
|
360 |
|
|
|
361 |
|
|
.pio_request (pio_request ),
|
362 |
|
|
.pio_transfer_count (pio_transfer_count ),
|
363 |
|
|
.pio_direction (pio_direction ),
|
364 |
|
|
.pio_e_status (pio_e_status ),
|
365 |
|
|
|
366 |
|
|
//FIS Structure
|
367 |
|
|
.h2d_command (h2d_command ),
|
368 |
|
|
.h2d_features (h2d_features ),
|
369 |
|
|
.h2d_cmd_bit (h2d_cmd_bit ),
|
370 |
|
|
.h2d_port_mult (h2d_port_mult ),
|
371 |
|
|
.h2d_control (h2d_control ),
|
372 |
|
|
.h2d_device (h2d_device ),
|
373 |
|
|
.h2d_lba (h2d_lba ),
|
374 |
|
|
.h2d_sector_count (h2d_sector_count ),
|
375 |
|
|
|
376 |
|
|
.d2h_interrupt (d2h_interrupt ),
|
377 |
|
|
.d2h_notification (d2h_notification ),
|
378 |
|
|
.d2h_status (d2h_status ),
|
379 |
|
|
.d2h_error (d2h_error ),
|
380 |
|
|
.d2h_port_mult (d2h_port_mult ),
|
381 |
|
|
.d2h_device (d2h_device ),
|
382 |
|
|
.d2h_lba (d2h_lba ),
|
383 |
|
|
.d2h_sector_count (d2h_sector_count ),
|
384 |
|
|
|
385 |
|
|
//command layer data interface
|
386 |
|
|
.cl_if_strobe (cl_if_strobe ),
|
387 |
|
|
.cl_if_data (cl_if_data ),
|
388 |
|
|
.cl_if_ready (cl_if_ready ),
|
389 |
|
|
.cl_if_activate (cl_if_activate ),
|
390 |
|
|
.cl_if_size (cl_if_size ),
|
391 |
|
|
|
392 |
|
|
.cl_of_strobe (cl_of_strobe ),
|
393 |
|
|
.cl_of_data (cl_of_data ),
|
394 |
|
|
.cl_of_ready (cl_of_ready ),
|
395 |
|
|
.cl_of_activate (cl_of_activate ),
|
396 |
|
|
.cl_of_size (cl_of_size ),
|
397 |
|
|
|
398 |
|
|
//Link Layer Interface
|
399 |
|
|
.link_layer_ready (ll_ready ),
|
400 |
|
|
|
401 |
|
|
.ll_write_start (t_write_start ),
|
402 |
|
|
.ll_write_strobe (t_write_strobe ),
|
403 |
|
|
.ll_write_finished (t_write_finished ),
|
404 |
|
|
.ll_write_data (t_write_data ),
|
405 |
|
|
.ll_write_size (t_write_size ),
|
406 |
|
|
.ll_write_hold (t_write_hold ),
|
407 |
|
|
.ll_write_abort (t_write_abort ),
|
408 |
|
|
.ll_xmit_error (t_xmit_error ),
|
409 |
|
|
|
410 |
|
|
.ll_read_start (t_read_start ),
|
411 |
|
|
.ll_read_ready (t_read_ready ),
|
412 |
|
|
.ll_read_data (t_read_data ),
|
413 |
|
|
.ll_read_strobe (t_read_strobe ),
|
414 |
|
|
.ll_read_finished (t_read_finished ),
|
415 |
|
|
.ll_read_crc_ok (t_read_crc_ok ),
|
416 |
|
|
.ll_remote_abort (t_remote_abort )
|
417 |
|
|
|
418 |
|
|
|
419 |
|
|
);
|
420 |
|
|
|
421 |
|
|
faux_hd_command_layer fcl(
|
422 |
|
|
.rst (rst ),
|
423 |
|
|
.clk (clk ),
|
424 |
|
|
|
425 |
|
|
.command_layer_ready (command_layer_ready ),
|
426 |
|
|
|
427 |
|
|
.hd_read_from_host (hd_read_from_host ),
|
428 |
|
|
.hd_data_from_host (hd_data_from_host ),
|
429 |
|
|
|
430 |
|
|
.hd_write_to_host (hd_write_to_host ),
|
431 |
|
|
.hd_data_to_host (hd_data_to_host ),
|
432 |
|
|
|
433 |
|
|
|
434 |
|
|
.transport_layer_ready(transport_layer_ready ),
|
435 |
|
|
.send_reg_stb (cl_send_reg_stb ),
|
436 |
|
|
.send_dma_act_stb (cl_send_dma_act_stb ),
|
437 |
|
|
.send_data_stb (cl_send_data_stb ),
|
438 |
|
|
.send_pio_stb (cl_send_pio_stb ),
|
439 |
|
|
.send_dev_bits_stb (cl_send_dev_bits_stb ),
|
440 |
|
|
|
441 |
|
|
.remote_abort (remote_abort ),
|
442 |
|
|
.xmit_error (xmit_error ),
|
443 |
|
|
.read_crc_fail (read_crc_fail ),
|
444 |
|
|
|
445 |
|
|
.h2d_reg_stb (h2d_reg_stb ),
|
446 |
|
|
.h2d_data_stb (h2d_data_stb ),
|
447 |
|
|
|
448 |
|
|
.pio_request (pio_request ),
|
449 |
|
|
.pio_transfer_count (cl_pio_transfer_count ),
|
450 |
|
|
.pio_direction (cl_pio_direction ),
|
451 |
|
|
.pio_e_status (cl_pio_e_status ),
|
452 |
|
|
|
453 |
|
|
//FIS Structure
|
454 |
|
|
.h2d_command (h2d_command ),
|
455 |
|
|
.h2d_features (h2d_features ),
|
456 |
|
|
.h2d_cmd_bit (h2d_cmd_bit ),
|
457 |
|
|
.h2d_port_mult (h2d_port_mult ),
|
458 |
|
|
.h2d_control (h2d_control ),
|
459 |
|
|
.h2d_device (h2d_device ),
|
460 |
|
|
.h2d_lba (h2d_lba ),
|
461 |
|
|
.h2d_sector_count (h2d_sector_count ),
|
462 |
|
|
|
463 |
|
|
.d2h_interrupt (cl_d2h_interrupt ),
|
464 |
|
|
.d2h_notification (cl_d2h_notification ),
|
465 |
|
|
.d2h_status (cl_d2h_status ),
|
466 |
|
|
.d2h_error (cl_d2h_error ),
|
467 |
|
|
.d2h_port_mult (cl_d2h_port_mult ),
|
468 |
|
|
.d2h_device (cl_d2h_device ),
|
469 |
|
|
.d2h_lba (cl_d2h_lba ),
|
470 |
|
|
.d2h_sector_count (cl_d2h_sector_count ),
|
471 |
|
|
|
472 |
|
|
//command layer data interface
|
473 |
|
|
.cl_if_strobe (cl_if_strobe ),
|
474 |
|
|
.cl_if_data (if_data ),
|
475 |
|
|
.cl_if_ready (if_ready ),
|
476 |
|
|
.cl_if_activate (cl_if_activate ),
|
477 |
|
|
.cl_if_size (if_size ),
|
478 |
|
|
|
479 |
|
|
.cl_of_strobe (cl_of_strobe ),
|
480 |
|
|
.cl_of_data (cl_of_data ),
|
481 |
|
|
.cl_of_ready (of_ready ),
|
482 |
|
|
.cl_of_activate (cl_of_activate ),
|
483 |
|
|
.cl_of_size (of_size ),
|
484 |
|
|
.cl_state (cl_state )
|
485 |
|
|
|
486 |
|
|
);
|
487 |
|
|
|
488 |
|
|
assign tx_dout = !phy_ready ? phy_tx_dout : sll_tx_dout;
|
489 |
|
|
assign tx_isk[3:1] = 3'b000;
|
490 |
|
|
assign tx_isk[0] = !phy_ready ? phy_tx_isk : sll_tx_isk;
|
491 |
|
|
|
492 |
|
|
|
493 |
|
|
//Debug
|
494 |
|
|
//assign ll_write_start = (dbg_ll_en) ? dbg_ll_write_start : t_write_start;
|
495 |
|
|
//assign ll_write_data = (dbg_ll_en) ? dbg_ll_write_data : t_write_data;
|
496 |
|
|
//assign ll_write_hold = (dbg_ll_en) ? dbg_ll_write_hold : t_write_hold;
|
497 |
|
|
//assign ll_write_size = (dbg_ll_en) ? dbg_ll_write_size : t_write_size;
|
498 |
|
|
//assign ll_write_abort = (dbg_ll_en) ? dbg_ll_write_abort : t_write_abort;
|
499 |
|
|
//assign data_scrambler_en = (dbg_ll_en) ? dbg_data_scrambler_en : 1;
|
500 |
|
|
//
|
501 |
|
|
//assign ll_read_ready = (dbg_ll_en) ? dbg_ll_read_ready : t_read_ready;
|
502 |
|
|
//
|
503 |
|
|
assign ll_write_start = t_write_start;
|
504 |
|
|
assign ll_write_data = t_write_data;
|
505 |
|
|
assign ll_write_hold = t_write_hold;
|
506 |
|
|
assign ll_write_size = t_write_size;
|
507 |
|
|
assign ll_write_abort = t_write_abort;
|
508 |
|
|
assign data_scrambler_en = 1;
|
509 |
|
|
|
510 |
|
|
assign ll_read_ready = t_read_ready;
|
511 |
|
|
|
512 |
|
|
|
513 |
|
|
assign dbg_ll_write_strobe = ll_write_strobe;
|
514 |
|
|
assign dbg_ll_write_finished = ll_write_finished;
|
515 |
|
|
assign dbg_ll_xmit_error = xmit_error;
|
516 |
|
|
|
517 |
|
|
assign dbg_ll_read_strobe = ll_read_strobe;
|
518 |
|
|
assign dbg_ll_read_start = ll_read_start;
|
519 |
|
|
assign dbg_ll_read_finished = ll_read_finished;
|
520 |
|
|
assign dbg_ll_read_data = ll_read_data;
|
521 |
|
|
assign dbg_ll_remote_abort = ll_remote_abort;
|
522 |
|
|
|
523 |
|
|
|
524 |
|
|
|
525 |
|
|
//Transport Layer Debug Signals
|
526 |
|
|
assign dbg_tl_ready = transport_layer_ready;
|
527 |
|
|
|
528 |
|
|
assign t_read_strobe = ll_read_strobe;
|
529 |
|
|
assign t_read_start = ll_read_start;
|
530 |
|
|
assign t_read_finished = ll_read_finished;
|
531 |
|
|
assign t_read_data = ll_read_data;
|
532 |
|
|
assign t_remote_abort = ll_remote_abort;
|
533 |
|
|
assign t_read_crc_ok = ll_read_crc_ok;
|
534 |
|
|
assign t_write_strobe = ll_write_strobe;
|
535 |
|
|
assign t_write_finished = ll_write_finished;
|
536 |
|
|
|
537 |
|
|
assign send_reg_stb = (dbg_t_en) ? dbg_send_reg_stb : cl_send_reg_stb;
|
538 |
|
|
assign send_dma_act_stb = (dbg_t_en) ? dbg_send_dma_act_stb : cl_send_dma_act_stb;
|
539 |
|
|
assign send_data_stb = (dbg_t_en) ? dbg_send_data_stb : cl_send_data_stb;
|
540 |
|
|
assign send_pio_stb = (dbg_t_en) ? dbg_send_pio_stb : cl_send_pio_stb;
|
541 |
|
|
assign send_dev_bits_stb = (dbg_t_en) ? dbg_send_dev_bits_stb : cl_send_dev_bits_stb;
|
542 |
|
|
|
543 |
|
|
|
544 |
|
|
assign dbg_pio_request = pio_request;
|
545 |
|
|
assign pio_transfer_count = (dbg_t_en) ? dbg_pio_transfer_count : cl_pio_transfer_count;
|
546 |
|
|
assign pio_direction = (dbg_t_en) ? dbg_pio_direction : cl_pio_direction;
|
547 |
|
|
assign pio_e_status = (dbg_t_en) ? dbg_pio_e_status : cl_pio_e_status;
|
548 |
|
|
|
549 |
|
|
|
550 |
|
|
assign d2h_interrupt = (dbg_t_en) ? dbg_d2h_interrupt : cl_d2h_interrupt;
|
551 |
|
|
assign d2h_notification = (dbg_t_en) ? dbg_d2h_notification : cl_d2h_notification;
|
552 |
|
|
assign d2h_status = (dbg_t_en) ? dbg_d2h_status : cl_d2h_status;
|
553 |
|
|
assign d2h_error = (dbg_t_en) ? dbg_d2h_error : cl_d2h_error;
|
554 |
|
|
assign d2h_port_mult = (dbg_t_en) ? dbg_d2h_port_mult : cl_d2h_port_mult;
|
555 |
|
|
assign d2h_device = (dbg_t_en) ? dbg_d2h_device : cl_d2h_device;
|
556 |
|
|
assign d2h_lba = (dbg_t_en) ? dbg_d2h_lba : cl_d2h_lba;
|
557 |
|
|
assign d2h_sector_count = (dbg_t_en) ? dbg_d2h_sector_count : cl_d2h_sector_count;
|
558 |
|
|
|
559 |
|
|
|
560 |
|
|
assign cl_if_data = (dbg_t_en) ? dbg_cl_if_data : if_data;
|
561 |
|
|
assign cl_if_ready = (dbg_t_en) ? dbg_cl_if_ready : if_ready;
|
562 |
|
|
assign cl_if_size = (dbg_t_en) ? dbg_cl_if_size : if_size;
|
563 |
|
|
assign cl_of_ready = (dbg_t_en) ? dbg_cl_of_ready : of_ready;
|
564 |
|
|
assign cl_of_size = (dbg_t_en) ? dbg_cl_of_size : of_size;
|
565 |
|
|
|
566 |
|
|
assign dbg_remote_abort = remote_abort;
|
567 |
|
|
assign dbg_xmit_error = xmit_error;
|
568 |
|
|
assign dbg_read_crc_fail = read_crc_fail;
|
569 |
|
|
|
570 |
|
|
assign dbg_h2d_reg_stb = h2d_reg_stb;
|
571 |
|
|
assign dbg_h2d_data_stb = h2d_data_stb;
|
572 |
|
|
|
573 |
|
|
assign dbg_h2d_command = h2d_command;
|
574 |
|
|
assign dbg_h2d_features = h2d_features;
|
575 |
|
|
assign dbg_h2d_cmd_bit = h2d_cmd_bit;
|
576 |
|
|
assign dbg_h2d_port_mult = h2d_port_mult;
|
577 |
|
|
assign dbg_h2d_control = h2d_control;
|
578 |
|
|
assign dbg_h2d_device = h2d_device;
|
579 |
|
|
assign dbg_h2d_lba = h2d_lba;
|
580 |
|
|
assign dbg_h2d_sector_count = h2d_sector_count;
|
581 |
|
|
|
582 |
|
|
|
583 |
|
|
endmodule
|