URL https://opencores.org/ocsvn/nysa_sata/nysa_sata/trunk

Subversion Repositories nysa_sata

[/] [nysa_sata/] [trunk/] [sim/] [makefile] - Blame information for rev 2

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all:
        iverilog -I../../../../rtl -o design -cfile_list.txt -DSIMULATION
 
strict:
        iverilog -I../../../../rtl -o design -cfile_list.txt -Wall -DSIMULATION
 
clean:
        rm design
        rm *.vcd
sim:
        vvp design
wave:
        vvp design
        gtkwave design.vcd -T wave_script.tcl &
 
 

Line No.	Rev	Author	Line
1	2	cospan	`all:`
2			`iverilog -I../../../../rtl -o design -cfile_list.txt -DSIMULATION`
3
4			`strict:`
5			`iverilog -I../../../../rtl -o design -cfile_list.txt -Wall -DSIMULATION`
6
7			`clean:`
8			`rm design`
9			`rm *.vcd`
10			`sim:`
11			`vvp design`
12			`wave:`
13			`vvp design`
14			`gtkwave design.vcd -T wave_script.tcl &`
15
16

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Subversion Repositories nysa_sata

[/] [nysa_sata/] [trunk/] [sim/] [makefile] - Blame information for rev 2