URL https://opencores.org/ocsvn/nysa_sata/nysa_sata/trunk

Subversion Repositories nysa_sata

[/] [nysa_sata/] [trunk/] [sim/] [simple_tb.v] - Blame information for rev 4

Details | Compare with Previous | View Log


`timescale 1ns/1ps
 
`define SCLK_HALF_PERIOD 3
`define DCLK_HALF_PERIOD 3
//`define DCLK_HALF_PERIOD 2  //Change to any frequency you want
 
`define SCLK_PERIOD (2 * `SCLK_HALF_PERIOD)
`define DCLK_PERIOD (2 * `DCLK_HALF_PERIOD)
 
`define STARTUP_TIMEOUT   32'h00000100
`define ERROR_TIMEOUT     32'h00000100
`define TXRX_TIMEOUT      32'h00001000
 
`include "sata_defines.v"
 
module simple_tb ();
 
//Parameters
//Registers/Wires
reg                 rst           = 0;            //reset
reg                 clk           = 0;
reg                 sata_clk      = 0;
reg                 data_clk      = 0;
 
wire                command_layer_reset;
 
wire                linkup;           //link is finished
wire                sata_ready;
wire                sata_busy;
 
wire                send_sync_escape;
wire                hard_drive_error;
wire                pio_data_ready;
 
reg                 soft_reset_en   = 0;
reg         [15:0]  sector_count    = 8;
reg         [47:0]  sector_address  = 0;
 
reg         [31:0]  user_din;
reg                 user_din_stb;
wire        [1:0]   user_din_ready;
reg         [1:0]   user_din_activate;
wire        [23:0]  user_din_size;
 
wire        [31:0]  user_dout;
wire                user_dout_ready;
reg                 user_dout_activate;
reg                 user_dout_stb;
wire        [23:0]  user_dout_size;
 
 
wire                transport_layer_ready;
wire                link_layer_ready;
wire                phy_ready;
 
wire    [31:0]      tx_dout;
wire                tx_is_k;
wire                tx_comm_reset;
wire                tx_comm_wake;
wire                tx_elec_idle;
 
wire    [31:0]      rx_din;
wire    [3:0]       rx_is_k;
wire                rx_elec_idle;
wire                comm_init_detect;
wire                comm_wake_detect;
 
wire                rx_byte_is_aligned;
 
wire                prim_scrambler_en;
wire                data_scrambler_en;
 
//Data Interface
wire                tx_set_elec_idle;
wire                rx_is_elec_idle;
wire                hd_ready;
wire                platform_ready;
wire                platform_error;
 
//Debug
wire        [31:0]  hd_data_to_host;
 
reg         [23:0]  din_count;
reg         [23:0]  dout_count;
reg                 hold = 0;
 
reg                 single_rdwr = 0;
reg         [7:0]   sata_command = 0;
reg         [15:0]  user_features = 0;
 
 
wire                dma_activate_stb;
wire                d2h_reg_stb;
wire                pio_setup_stb;
wire                d2h_data_stb;
wire                dma_setup_stb;
wire                set_device_bits_stb;
 
wire        [7:0]   d2h_fis;
wire                d2h_interrupt;
wire                d2h_notification;
wire        [3:0]   d2h_port_mult;
wire        [7:0]   d2h_device;
wire        [47:0]  d2h_lba;
wire        [15:0]  d2h_sector_count;
wire        [7:0]   d2h_status;
wire        [7:0]   d2h_error;
 
 
reg                 r_u2h_write_enable = 0;
reg                 r_h2u_read_enable = 0;
 
reg                 sata_execute_command_stb = 0;
wire        [31:0]  hd_data_from_host;
wire                hd_read_from_host;
wire                hd_write_to_host;
 
//hd data reader core
hd_data_reader user_2_hd_reader(
  .clk                   (clk                  ),
  .rst                   (rst                  ),
  .enable                (r_u2h_write_enable   ),
  .error                 (u2h_read_error       ),
 
  .hd_read_from_host     (hd_read_from_host    ),
  .hd_data_from_host     (hd_data_from_host    )
);
 
//hd data writer core
hd_data_writer hd_2_user_generator(
  .clk                   (clk                  ),
  .rst                   (rst                  ),
  .enable                (r_h2u_read_enable    ),
  .data                  (hd_data_to_host      ),
  .strobe                (hd_write_to_host     )
);
 
//Submodules
sata_stack ss (
  .clk                    (sata_clk               ),  //clock used to run the stack
  .rst                    (rst                    ),  //reset
 
  .command_layer_reset    (command_layer_reset    ),  //Reset the command layer and send a software reset to the hard drive
 
  .platform_ready         (platform_ready         ),  //the underlying physical platform is ready
  .platform_error         (platform_error         ),  //some bad thing happend at the transceiver level
  .linkup                 (linkup                 ),  //link is finished
 
  .sata_ready             (sata_ready             ),  //Hard drive is ready for commands
  .sata_busy              (sata_busy              ),  //Hard drive is busy executing commands
 
  .send_sync_escape       (send_sync_escape       ),  //This is a way to escape from a running transaction
  .hard_drive_error       (hard_drive_error       ),
 
 
  .pio_data_ready         (pio_data_ready         ),  //Peripheral IO has some data ready
 
  //Host to Device Control
  .hard_drive_command     (sata_command           ),  //Hard Drive commands EX: DMA Read 0x25, DMA Write 0x35
  .execute_command_stb    (sata_execute_command_stb),
  .user_features          (user_features          ),
  .sector_count           (sector_count           ),
  .sector_address         (sector_address         ),
 
  .dma_activate_stb       (dma_activate_stb       ),
  .d2h_reg_stb            (d2h_reg_stb            ),
  .pio_setup_stb          (pio_setup_stb          ),
  .d2h_data_stb           (d2h_data_stb           ),
  .dma_setup_stb          (dma_setup_stb          ),
  .set_device_bits_stb    (set_device_bits_stb    ),
 
  .d2h_fis                (d2h_fis                ),
  .d2h_interrupt          (d2h_interrupt          ),
  .d2h_notification       (d2h_notification       ),
  .d2h_port_mult          (d2h_port_mult          ),
  .d2h_device             (d2h_device             ),
  .d2h_lba                (d2h_lba                ),
  .d2h_sector_count       (d2h_sector_count       ),
  .d2h_status             (d2h_status             ),
  .d2h_error              (d2h_error              ),
 
  //Data from host to the hard drive path
  .data_in_clk            (data_clk               ),  //Any clock to send data to the hard drive
  .data_in_clk_valid      (1'b1                   ),  //the data in clock is valid
  .user_din               (user_din               ),  //32-bit data to clock into FIFO
  .user_din_stb           (user_din_stb           ),  //Strobe to clock data into FIFO
  .user_din_ready         (user_din_ready         ),  //If one of the 2 in FIFOs are ready
  .user_din_activate      (user_din_activate      ),  //Activate one of the 2 FIFOs
  .user_din_size          (user_din_size          ),  //Number of available spots within the FIFO
  .user_din_empty         (user_din_empty         ),
 
  //Data from hard drive to host path
  .data_out_clk           (data_clk               ),
  .data_out_clk_valid     (1'b1                   ),  //the data out clock is valid
  .user_dout              (user_dout              ),  //Actual data the comes from FIFO
  .user_dout_ready        (user_dout_ready        ),  //The output FIFO is ready (see below for how to use)
  .user_dout_activate     (user_dout_activate     ),  //Activate a FIFO (See below for an example on how to use)
  .user_dout_stb          (user_dout_stb          ),  //Strobe the data out of the FIFO (first word is available before strobe)
  .user_dout_size         (user_dout_size         ),  //Number of 32-bit words available
 
  .transport_layer_ready  (transport_layer_ready  ),
  .link_layer_ready       (link_layer_ready       ),
  .phy_ready              (phy_ready              ),  //sata phy layer has linked up and communication simple comm started
  .phy_error              (1'b0                   ),  //an error on the transcievers has occured
 
  //Interface to the gigabit transcievers
  .tx_dout                (tx_dout              ),
  .tx_is_k                (tx_is_k              ),
  .tx_comm_reset          (tx_comm_reset        ),
  .tx_comm_wake           (tx_comm_wake         ),
  .tx_elec_idle           (tx_elec_idle         ),
  .tx_oob_complete        (1'b1                 ),
 
  .rx_din                 (rx_din               ),
  .rx_is_k                (rx_is_k              ),
  .rx_elec_idle           (1'b0                 ),
  .rx_byte_is_aligned     (rx_byte_is_aligned   ),
  .comm_init_detect       (comm_init_detect     ),
  .comm_wake_detect       (comm_wake_detect     ),
 
  //These should be set to 1 for normal operations, while debugging you can set to 0 to help debug things
  .prim_scrambler_en      (prim_scrambler_en      ),
  .data_scrambler_en      (data_scrambler_en      ),
 
  .dbg_cc_lax_state       (                       ),
  .dbg_cw_lax_state       (command_write_state    ),
 
  .dbg_t_lax_state        (transport_state        ),
 
  .dbg_li_lax_state       (                       ),
  .dbg_lr_lax_state       (                       ),
  .dbg_lw_lax_state       (ll_write_state         ),
  .dbg_lw_lax_fstate      (                       ),
 
 
  .dbg_ll_write_ready     (                       ),
  .dbg_ll_paw             (                       ),
  .dbg_ll_send_crc        (                       ),
 
  .oob_state              (oob_state              ),
 
  .dbg_detect_sync        (                       ),
  .dbg_detect_r_rdy       (                       ),
  .dbg_detect_r_ip        (                       ),
  .dbg_detect_r_ok        (dbg_detect_r_ok        ),
  .dbg_detect_r_err       (dbg_detect_r_err       ),
  .dbg_detect_x_rdy       (                       ),
  .dbg_detect_sof         (                       ),
  .dbg_detect_eof         (                       ),
  .dbg_detect_wtrm        (                       ),
  .dbg_detect_cont        (                       ),
  .dbg_detect_hold        (                       ),
  .dbg_detect_holda       (                       ),
  .dbg_detect_align       (                       ),
  .dbg_detect_preq_s      (                       ),
  .dbg_detect_preq_p      (                       ),
  .dbg_detect_xrdy_xrdy   (                       ),
 
  .dbg_send_holda         (                       ),
 
//  .slw_in_data_addra      (slw_in_data_addra      ),
//  .slw_d_count            (slw_d_count            ),
//  .slw_write_count        (slw_write_count        ),
//  .slw_buffer_pos         (slw_buffer_pos         )
 
  .slw_in_data_addra      (                       ),
  .slw_d_count            (                       ),
  .slw_write_count        (                       ),
  .slw_buffer_pos         (                       )
 
);
 
faux_sata_hd  fshd   (
  .rst                   (rst                     ),
  .clk                   (sata_clk                ),
  .tx_dout               (rx_din                  ),
  .tx_is_k               (rx_is_k                 ),
 
  .rx_din                (tx_dout                 ),
  .rx_is_k               ({3'b000, tx_is_k}       ),
  .rx_is_elec_idle       (tx_elec_idle            ),
  .rx_byte_is_aligned    (rx_byte_is_aligned      ),
 
  .comm_reset_detect     (tx_comm_reset           ),
  .comm_wake_detect      (tx_comm_wake            ),
 
  .tx_comm_reset         (comm_init_detect        ),
  .tx_comm_wake          (comm_wake_detect        ),
 
  .hd_ready              (hd_ready                ),
//  .phy_ready             (phy_ready              ),
 
 
  .dbg_data_scrambler_en (data_scrambler_en       ),
 
  .dbg_hold              (hold                    ),
 
  .dbg_ll_write_start    (0                       ),
  .dbg_ll_write_data     (0                       ),
  .dbg_ll_write_size     (0                       ),
  .dbg_ll_write_hold     (0                       ),
  .dbg_ll_write_abort    (0                       ),
 
  .dbg_ll_read_ready     (0                       ),
  .dbg_t_en              (0                       ),
 
  .dbg_send_reg_stb      (0                       ),
  .dbg_send_dma_act_stb  (0                       ),
  .dbg_send_data_stb     (0                       ),
  .dbg_send_pio_stb      (0                       ),
  .dbg_send_dev_bits_stb (0                       ),
 
  .dbg_pio_transfer_count(0                       ),
  .dbg_pio_direction     (0                       ),
  .dbg_pio_e_status      (0                       ),
 
  .dbg_d2h_interrupt     (0                       ),
  .dbg_d2h_notification  (0                       ),
  .dbg_d2h_status        (0                       ),
  .dbg_d2h_error         (0                       ),
  .dbg_d2h_port_mult     (0                       ),
  .dbg_d2h_device        (0                       ),
  .dbg_d2h_lba           (0                       ),
  .dbg_d2h_sector_count  (0                       ),
 
  .dbg_cl_if_data        (0                       ),
  .dbg_cl_if_ready       (0                       ),
  .dbg_cl_if_size        (0                       ),
  .dbg_cl_of_ready       (0                       ),
  .dbg_cl_of_size        (0                       ),
 
  .hd_read_from_host     (hd_read_from_host       ),
  .hd_data_from_host     (hd_data_from_host       ),
 
  .hd_write_to_host      (hd_write_to_host        ),
  .hd_data_to_host       (hd_data_to_host         )
 
);
 
 
 
//Asynchronous Logic
assign  prim_scrambler_en             = 1;
assign  data_scrambler_en             = 1;
assign  platform_ready                = 1;
//assign  hd_data_to_host               = 32'h01234567;
assign  send_sync_escape              = 1'b0;
assign command_layer_reset            = 1'b0;
 
 
//Synchronous Logic
always #`SCLK_HALF_PERIOD sata_clk    = ~sata_clk;
always #`DCLK_HALF_PERIOD data_clk    = ~data_clk;
always #1 clk                         = ~clk;
 
//Simulation Control
initial begin
  rst <=  1;
  //$dumpfile ("design.vcd");
  //$dumpvars(0, simple_tb);
  #(20 * `SCLK_PERIOD);
  rst <=  0;
  //#(20 * `SCLK_PERIOD);
  //$finish();
end
 
 
//Simulation Conditions
initial begin
  sector_address                    <=  0;
  sector_count                      <=  8;
  single_rdwr                       <=  0;
 
  sata_command                      <=  0;
  user_features                     <=  0;
 
  r_u2h_write_enable                <=  0;
  r_h2u_read_enable                 <=  0;
  sata_execute_command_stb          <=  0;
 
  #(20 * `SCLK_PERIOD);
  while (!linkup) begin
    #(1 * `SCLK_PERIOD);
  end
  while (!sata_ready) begin
    #(1 * `SCLK_PERIOD);
  end
  //Send a command
//  #(700 * `SCLK_PERIOD);
  //#(563 * `SCLK_PERIOD);
  #(100 * `SCLK_PERIOD);
  sata_command                      <=  8'h35;  //Write
  sector_count                      <=  1;
  #(1 * `SCLK_PERIOD);
  sata_execute_command_stb          <=  1;
  #(1 * `SCLK_PERIOD);
  sata_execute_command_stb          <=  0;
  r_u2h_write_enable                <=  1;      //Read Data on the Hard Drive Side
 
 
  #(1000 * `SCLK_PERIOD);
  while (sata_busy) begin
  #(1 * `SCLK_PERIOD);
  end
  #(100 * `SCLK_PERIOD);
  r_u2h_write_enable                <=  0;
 
 
 
 
  //Put some data in the virtual hard drive
  r_h2u_read_enable                 <=  1;
  #(1000 * `SCLK_PERIOD);
  sector_count                      <=  2;
  sata_command                      <=  8'h25;  //Read
  #(1 * `SCLK_PERIOD);
  sata_execute_command_stb          <=  1;
  #(1 * `SCLK_PERIOD);
  sata_execute_command_stb          <=  0;
 
 
  #(1000 * `SCLK_PERIOD);
  #(20 * `SCLK_PERIOD);
  while (sata_busy) begin
    #1;
  end
  r_h2u_read_enable                 <=  0;
 
  //$finish();
end
 
/*
initial begin
  hold                              <=  0;
  #(20 * `SCLK_PERIOD);
  while (!sata_busy) begin
    #1;
 end
  #(800* `SCLK_PERIOD);
  hold                              <=  1;
  #(100 * `SCLK_PERIOD);
  hold                              <=  0;
end
*/
/*
//inject a hold
initial begin
  hold                              <=  0;
  #(20 * `SCLK_PERIOD);
  while (!write_data_en) begin
    #1;
  end
  #(682 * `SCLK_PERIOD);
  hold                              <=  1;
  #(1 * `SCLK_PERIOD);
  hold                              <=  0;
end
*/
 
 
/*
initial begin
  sector_address                    <=  0;
  sector_count                      <=  0;
 
  #(20 * `SCLK_PERIOD);
  while (!linkup) begin
    #1;
  end
  while (busy) begin
    #1;
  end
  //Send a command
  #(824 * `SCLK_PERIOD);
  write_data_en                     <=  1;
  #(20 * `SCLK_PERIOD);
  while (!busy) begin
    #1;
  end
  write_data_en                     <=  0;
end
*/
 
 
 
 
 
 
 
 
 
 
//Buffer Fill/Drain
always @ (posedge data_clk) begin
  if (rst) begin
    user_din                        <=  0;
    user_din_stb                    <=  0;
    user_din_activate               <=  0;
    din_count                       <=  0;
 
    user_dout_activate              <=  0;
    user_dout_stb                   <=  0;
    dout_count                      <=  0;
  end
  else begin
    user_din_stb                    <=  0;
    user_dout_stb                   <=  0;
 
    if ((user_din_ready > 0) && (user_din_activate == 0)) begin
      din_count                     <=  0;
      if (user_din_ready[0]) begin
        user_din_activate[0]        <=  1;
      end
      else begin
        user_din_activate[1]        <=  1;
      end
    end
 
    if (din_count >= user_din_size) begin
      user_din_activate            <=  0;
    end
    else if (user_din_activate > 0) begin
      user_din_stb                  <=  1;
      user_din                      <=  din_count;
      din_count                     <=  din_count + 1;
    end
 
    if (user_dout_ready && !user_dout_activate) begin
      dout_count                    <=  0;
      user_dout_activate            <=  1;
    end
 
    if (dout_count >= user_dout_size) begin
      user_dout_activate             <=  0;
    end
    else if (user_dout_activate) begin
      user_dout_stb                 <=  1;
    end
  end
end
 
 
endmodule

Line No.	Rev	Author	Line
1	2	cospan	`timescale 1ns/1ps
2
3			`define SCLK_HALF_PERIOD 3
4	4	cospan	`define DCLK_HALF_PERIOD 3
5			//`define DCLK_HALF_PERIOD 2 //Change to any frequency you want
6	2	cospan
7			`define SCLK_PERIOD (2 * `SCLK_HALF_PERIOD)
8	4	cospan	`define DCLK_PERIOD (2 * `DCLK_HALF_PERIOD)
9	2	cospan
10			`define STARTUP_TIMEOUT 32'h00000100
11			`define ERROR_TIMEOUT 32'h00000100
12			`define TXRX_TIMEOUT 32'h00001000
13
14			`include "sata_defines.v"
15
16			`module simple_tb ();`
17
18			`//Parameters`
19			`//Registers/Wires`
20			`reg rst = 0; //reset`
21	4	cospan	`reg clk = 0;`
22	2	cospan	`reg sata_clk = 0;`
23	4	cospan	`reg data_clk = 0;`
24	2	cospan
25	4	cospan	`wire command_layer_reset;`
26
27	2	cospan	`wire linkup; //link is finished`
28			`wire sata_ready;`
29	4	cospan	`wire sata_busy;`
30	2	cospan
31	4	cospan	`wire send_sync_escape;`
32			`wire hard_drive_error;`
33			`wire pio_data_ready;`
34	2	cospan
35			`reg soft_reset_en = 0;`
36			`reg [15:0] sector_count = 8;`
37			`reg [47:0] sector_address = 0;`
38
39			`reg [31:0] user_din;`
40			`reg user_din_stb;`
41			`wire [1:0] user_din_ready;`
42			`reg [1:0] user_din_activate;`
43			`wire [23:0] user_din_size;`
44
45			`wire [31:0] user_dout;`
46			`wire user_dout_ready;`
47			`reg user_dout_activate;`
48			`reg user_dout_stb;`
49			`wire [23:0] user_dout_size;`
50
51
52			`wire transport_layer_ready;`
53			`wire link_layer_ready;`
54			`wire phy_ready;`
55
56			`wire [31:0] tx_dout;`
57	4	cospan	`wire tx_is_k;`
58	2	cospan	`wire tx_comm_reset;`
59			`wire tx_comm_wake;`
60			`wire tx_elec_idle;`
61
62			`wire [31:0] rx_din;`
63	4	cospan	`wire [3:0] rx_is_k;`
64	2	cospan	`wire rx_elec_idle;`
65			`wire comm_init_detect;`
66			`wire comm_wake_detect;`
67
68			`wire rx_byte_is_aligned;`
69
70			`wire prim_scrambler_en;`
71			`wire data_scrambler_en;`
72
73			`//Data Interface`
74			`wire tx_set_elec_idle;`
75			`wire rx_is_elec_idle;`
76			`wire hd_ready;`
77			`wire platform_ready;`
78	4	cospan	`wire platform_error;`
79	2	cospan
80			`//Debug`
81			`wire [31:0] hd_data_to_host;`
82
83			`reg [23:0] din_count;`
84			`reg [23:0] dout_count;`
85	4	cospan	`reg hold = 0;`
86	2	cospan
87			`reg single_rdwr = 0;`
88	4	cospan	`reg [7:0] sata_command = 0;`
89			`reg [15:0] user_features = 0;`
90	2	cospan
91
92	4	cospan	`wire dma_activate_stb;`
93			`wire d2h_reg_stb;`
94			`wire pio_setup_stb;`
95			`wire d2h_data_stb;`
96			`wire dma_setup_stb;`
97			`wire set_device_bits_stb;`
98	2	cospan
99	4	cospan	`wire [7:0] d2h_fis;`
100			`wire d2h_interrupt;`
101			`wire d2h_notification;`
102			`wire [3:0] d2h_port_mult;`
103			`wire [7:0] d2h_device;`
104			`wire [47:0] d2h_lba;`
105			`wire [15:0] d2h_sector_count;`
106			`wire [7:0] d2h_status;`
107			`wire [7:0] d2h_error;`
108	2	cospan
109
110	4	cospan	`reg r_u2h_write_enable = 0;`
111			`reg r_h2u_read_enable = 0;`
112	2	cospan
113	4	cospan	`reg sata_execute_command_stb = 0;`
114			`wire [31:0] hd_data_from_host;`
115			`wire hd_read_from_host;`
116			`wire hd_write_to_host;`
117
118			`//hd data reader core`
119			`hd_data_reader user_2_hd_reader(`
120			`.clk (clk ),`
121			`.rst (rst ),`
122			`.enable (r_u2h_write_enable ),`
123			`.error (u2h_read_error ),`
124
125			`.hd_read_from_host (hd_read_from_host ),`
126			`.hd_data_from_host (hd_data_from_host )`
127			`);`
128
129			`//hd data writer core`
130			`hd_data_writer hd_2_user_generator(`
131			`.clk (clk ),`
132			`.rst (rst ),`
133			`.enable (r_h2u_read_enable ),`
134			`.data (hd_data_to_host ),`
135			`.strobe (hd_write_to_host )`
136			`);`
137
138	2	cospan	`//Submodules`
139			`sata_stack ss (`
140	4	cospan	`.clk (sata_clk ), //clock used to run the stack`
141			`.rst (rst ), //reset`
142	2	cospan
143	4	cospan	`.command_layer_reset (command_layer_reset ), //Reset the command layer and send a software reset to the hard drive`
144	2	cospan
145	4	cospan	`.platform_ready (platform_ready ), //the underlying physical platform is ready`
146			`.platform_error (platform_error ), //some bad thing happend at the transceiver level`
147			`.linkup (linkup ), //link is finished`
148	2	cospan
149	4	cospan	`.sata_ready (sata_ready ), //Hard drive is ready for commands`
150			`.sata_busy (sata_busy ), //Hard drive is busy executing commands`
151	2	cospan
152	4	cospan	`.send_sync_escape (send_sync_escape ), //This is a way to escape from a running transaction`
153			`.hard_drive_error (hard_drive_error ),`
154	2	cospan
155
156	4	cospan	`.pio_data_ready (pio_data_ready ), //Peripheral IO has some data ready`
157	2	cospan
158	4	cospan	`//Host to Device Control`
159			`.hard_drive_command (sata_command ), //Hard Drive commands EX: DMA Read 0x25, DMA Write 0x35`
160			`.execute_command_stb (sata_execute_command_stb),`
161			`.user_features (user_features ),`
162			`.sector_count (sector_count ),`
163			`.sector_address (sector_address ),`
164	2	cospan
165	4	cospan	`.dma_activate_stb (dma_activate_stb ),`
166			`.d2h_reg_stb (d2h_reg_stb ),`
167			`.pio_setup_stb (pio_setup_stb ),`
168			`.d2h_data_stb (d2h_data_stb ),`
169			`.dma_setup_stb (dma_setup_stb ),`
170			`.set_device_bits_stb (set_device_bits_stb ),`
171	2	cospan
172	4	cospan	`.d2h_fis (d2h_fis ),`
173			`.d2h_interrupt (d2h_interrupt ),`
174			`.d2h_notification (d2h_notification ),`
175			`.d2h_port_mult (d2h_port_mult ),`
176			`.d2h_device (d2h_device ),`
177			`.d2h_lba (d2h_lba ),`
178			`.d2h_sector_count (d2h_sector_count ),`
179			`.d2h_status (d2h_status ),`
180			`.d2h_error (d2h_error ),`
181	2	cospan
182	4	cospan	`//Data from host to the hard drive path`
183			`.data_in_clk (data_clk ), //Any clock to send data to the hard drive`
184			`.data_in_clk_valid (1'b1 ), //the data in clock is valid`
185			`.user_din (user_din ), //32-bit data to clock into FIFO`
186			`.user_din_stb (user_din_stb ), //Strobe to clock data into FIFO`
187			`.user_din_ready (user_din_ready ), //If one of the 2 in FIFOs are ready`
188			`.user_din_activate (user_din_activate ), //Activate one of the 2 FIFOs`
189			`.user_din_size (user_din_size ), //Number of available spots within the FIFO`
190			`.user_din_empty (user_din_empty ),`
191	2	cospan
192	4	cospan	`//Data from hard drive to host path`
193			`.data_out_clk (data_clk ),`
194			`.data_out_clk_valid (1'b1 ), //the data out clock is valid`
195			`.user_dout (user_dout ), //Actual data the comes from FIFO`
196			`.user_dout_ready (user_dout_ready ), //The output FIFO is ready (see below for how to use)`
197			`.user_dout_activate (user_dout_activate ), //Activate a FIFO (See below for an example on how to use)`
198			`.user_dout_stb (user_dout_stb ), //Strobe the data out of the FIFO (first word is available before strobe)`
199			`.user_dout_size (user_dout_size ), //Number of 32-bit words available`
200	2	cospan
201	4	cospan	`.transport_layer_ready (transport_layer_ready ),`
202			`.link_layer_ready (link_layer_ready ),`
203			`.phy_ready (phy_ready ), //sata phy layer has linked up and communication simple comm started`
204			`.phy_error (1'b0 ), //an error on the transcievers has occured`
205	2	cospan
206	4	cospan	`//Interface to the gigabit transcievers`
207			`.tx_dout (tx_dout ),`
208			`.tx_is_k (tx_is_k ),`
209			`.tx_comm_reset (tx_comm_reset ),`
210			`.tx_comm_wake (tx_comm_wake ),`
211			`.tx_elec_idle (tx_elec_idle ),`
212			`.tx_oob_complete (1'b1 ),`
213	2	cospan
214	4	cospan	`.rx_din (rx_din ),`
215			`.rx_is_k (rx_is_k ),`
216			`.rx_elec_idle (1'b0 ),`
217			`.rx_byte_is_aligned (rx_byte_is_aligned ),`
218			`.comm_init_detect (comm_init_detect ),`
219			`.comm_wake_detect (comm_wake_detect ),`
220	2	cospan
221	4	cospan	`//These should be set to 1 for normal operations, while debugging you can set to 0 to help debug things`
222			`.prim_scrambler_en (prim_scrambler_en ),`
223			`.data_scrambler_en (data_scrambler_en ),`
224
225			`.dbg_cc_lax_state ( ),`
226			`.dbg_cw_lax_state (command_write_state ),`
227
228			`.dbg_t_lax_state (transport_state ),`
229
230			`.dbg_li_lax_state ( ),`
231			`.dbg_lr_lax_state ( ),`
232			`.dbg_lw_lax_state (ll_write_state ),`
233			`.dbg_lw_lax_fstate ( ),`
234
235
236			`.dbg_ll_write_ready ( ),`
237			`.dbg_ll_paw ( ),`
238			`.dbg_ll_send_crc ( ),`
239
240			`.oob_state (oob_state ),`
241
242			`.dbg_detect_sync ( ),`
243			`.dbg_detect_r_rdy ( ),`
244			`.dbg_detect_r_ip ( ),`
245			`.dbg_detect_r_ok (dbg_detect_r_ok ),`
246			`.dbg_detect_r_err (dbg_detect_r_err ),`
247			`.dbg_detect_x_rdy ( ),`
248			`.dbg_detect_sof ( ),`
249			`.dbg_detect_eof ( ),`
250			`.dbg_detect_wtrm ( ),`
251			`.dbg_detect_cont ( ),`
252			`.dbg_detect_hold ( ),`
253			`.dbg_detect_holda ( ),`
254			`.dbg_detect_align ( ),`
255			`.dbg_detect_preq_s ( ),`
256			`.dbg_detect_preq_p ( ),`
257			`.dbg_detect_xrdy_xrdy ( ),`
258
259			`.dbg_send_holda ( ),`
260
261			`// .slw_in_data_addra (slw_in_data_addra ),`
262			`// .slw_d_count (slw_d_count ),`
263			`// .slw_write_count (slw_write_count ),`
264			`// .slw_buffer_pos (slw_buffer_pos )`
265
266			`.slw_in_data_addra ( ),`
267			`.slw_d_count ( ),`
268			`.slw_write_count ( ),`
269			`.slw_buffer_pos ( )`
270
271	2	cospan	`);`
272
273			`faux_sata_hd fshd (`
274	4	cospan	`.rst (rst ),`
275			`.clk (sata_clk ),`
276			`.tx_dout (rx_din ),`
277			`.tx_is_k (rx_is_k ),`
278	2	cospan
279	4	cospan	`.rx_din (tx_dout ),`
280			`.rx_is_k ({3'b000, tx_is_k} ),`
281			`.rx_is_elec_idle (tx_elec_idle ),`
282			`.rx_byte_is_aligned (rx_byte_is_aligned ),`
283	2	cospan
284	4	cospan	`.comm_reset_detect (tx_comm_reset ),`
285			`.comm_wake_detect (tx_comm_wake ),`
286	2	cospan
287	4	cospan	`.tx_comm_reset (comm_init_detect ),`
288			`.tx_comm_wake (comm_wake_detect ),`
289	2	cospan
290	4	cospan	`.hd_ready (hd_ready ),`
291			`// .phy_ready (phy_ready ),`
292	2	cospan
293
294	4	cospan	`.dbg_data_scrambler_en (data_scrambler_en ),`
295	2	cospan
296	4	cospan	`.dbg_hold (hold ),`
297	2	cospan
298	4	cospan	`.dbg_ll_write_start (0 ),`
299			`.dbg_ll_write_data (0 ),`
300			`.dbg_ll_write_size (0 ),`
301			`.dbg_ll_write_hold (0 ),`
302			`.dbg_ll_write_abort (0 ),`
303	2	cospan
304	4	cospan	`.dbg_ll_read_ready (0 ),`
305			`.dbg_t_en (0 ),`
306	2	cospan
307	4	cospan	`.dbg_send_reg_stb (0 ),`
308			`.dbg_send_dma_act_stb (0 ),`
309			`.dbg_send_data_stb (0 ),`
310			`.dbg_send_pio_stb (0 ),`
311			`.dbg_send_dev_bits_stb (0 ),`
312	2	cospan
313	4	cospan	`.dbg_pio_transfer_count(0 ),`
314			`.dbg_pio_direction (0 ),`
315			`.dbg_pio_e_status (0 ),`
316	2	cospan
317	4	cospan	`.dbg_d2h_interrupt (0 ),`
318			`.dbg_d2h_notification (0 ),`
319			`.dbg_d2h_status (0 ),`
320			`.dbg_d2h_error (0 ),`
321			`.dbg_d2h_port_mult (0 ),`
322			`.dbg_d2h_device (0 ),`
323			`.dbg_d2h_lba (0 ),`
324			`.dbg_d2h_sector_count (0 ),`
325	2	cospan
326	4	cospan	`.dbg_cl_if_data (0 ),`
327			`.dbg_cl_if_ready (0 ),`
328			`.dbg_cl_if_size (0 ),`
329			`.dbg_cl_of_ready (0 ),`
330			`.dbg_cl_of_size (0 ),`
331	2	cospan
332	4	cospan	`.hd_read_from_host (hd_read_from_host ),`
333			`.hd_data_from_host (hd_data_from_host ),`
334	2	cospan
335	4	cospan	`.hd_write_to_host (hd_write_to_host ),`
336			`.hd_data_to_host (hd_data_to_host )`
337
338	2	cospan	`);`
339
340
341
342			`//Asynchronous Logic`
343			`assign prim_scrambler_en = 1;`
344			`assign data_scrambler_en = 1;`
345			`assign platform_ready = 1;`
346	4	cospan	`//assign hd_data_to_host = 32'h01234567;`
347			`assign send_sync_escape = 1'b0;`
348			`assign command_layer_reset = 1'b0;`
349	2	cospan
350
351			`//Synchronous Logic`
352			always #`SCLK_HALF_PERIOD sata_clk = ~sata_clk;
353	4	cospan	always #`DCLK_HALF_PERIOD data_clk = ~data_clk;
354	2	cospan	`always #1 clk = ~clk;`
355
356			`//Simulation Control`
357			`initial begin`
358			`rst <= 1;`
359	4	cospan	`//$dumpfile ("design.vcd");`
360			`//$dumpvars(0, simple_tb);`
361	2	cospan	#(20 * `SCLK_PERIOD);
362			`rst <= 0;`
363	4	cospan	//#(20 * `SCLK_PERIOD);
364			`//$finish();`
365	2	cospan	`end`
366
367
368			`//Simulation Conditions`
369			`initial begin`
370			`sector_address <= 0;`
371			`sector_count <= 8;`
372			`single_rdwr <= 0;`
373
374	4	cospan	`sata_command <= 0;`
375			`user_features <= 0;`
376
377			`r_u2h_write_enable <= 0;`
378			`r_h2u_read_enable <= 0;`
379			`sata_execute_command_stb <= 0;`
380
381	2	cospan	#(20 * `SCLK_PERIOD);
382			`while (!linkup) begin`
383	4	cospan	#(1 * `SCLK_PERIOD);
384	2	cospan	`end`
385	4	cospan	`while (!sata_ready) begin`
386			#(1 * `SCLK_PERIOD);
387	2	cospan	`end`
388			`//Send a command`
389			// #(700 * `SCLK_PERIOD);
390	4	cospan	//#(563 * `SCLK_PERIOD);
391			#(100 * `SCLK_PERIOD);
392			`sata_command <= 8'h35; //Write`
393			`sector_count <= 1;`
394			#(1 * `SCLK_PERIOD);
395			`sata_execute_command_stb <= 1;`
396			#(1 * `SCLK_PERIOD);
397			`sata_execute_command_stb <= 0;`
398			`r_u2h_write_enable <= 1; //Read Data on the Hard Drive Side`
399
400
401	2	cospan	#(1000 * `SCLK_PERIOD);
402	4	cospan	`while (sata_busy) begin`
403			#(1 * `SCLK_PERIOD);
404	2	cospan	`end`
405			#(100 * `SCLK_PERIOD);
406	4	cospan	`r_u2h_write_enable <= 0;`
407	2	cospan
408
409
410	4	cospan
411			`//Put some data in the virtual hard drive`
412			`r_h2u_read_enable <= 1;`
413			#(1000 * `SCLK_PERIOD);
414			`sector_count <= 2;`
415			`sata_command <= 8'h25; //Read`
416			#(1 * `SCLK_PERIOD);
417			`sata_execute_command_stb <= 1;`
418			#(1 * `SCLK_PERIOD);
419			`sata_execute_command_stb <= 0;`
420
421
422			#(1000 * `SCLK_PERIOD);
423	2	cospan	#(20 * `SCLK_PERIOD);
424	4	cospan	`while (sata_busy) begin`
425	2	cospan	`#1;`
426			`end`
427	4	cospan	`r_h2u_read_enable <= 0;`
428
429			`//$finish();`
430	2	cospan	`end`
431
432	4	cospan	`/*`
433	2	cospan	`initial begin`
434			`hold <= 0;`
435			#(20 * `SCLK_PERIOD);
436	4	cospan	`while (!sata_busy) begin`
437	2	cospan	`#1;`
438			`end`
439			#(800* `SCLK_PERIOD);
440			`hold <= 1;`
441			#(100 * `SCLK_PERIOD);
442			`hold <= 0;`
443			`end`
444	4	cospan	`*/`
445	2	cospan	`/*`
446			`//inject a hold`
447			`initial begin`
448			`hold <= 0;`
449			#(20 * `SCLK_PERIOD);
450			`while (!write_data_en) begin`
451			`#1;`
452			`end`
453			#(682 * `SCLK_PERIOD);
454			`hold <= 1;`
455			#(1 * `SCLK_PERIOD);
456			`hold <= 0;`
457			`end`
458			`*/`
459
460
461			`/*`
462			`initial begin`
463			`sector_address <= 0;`
464			`sector_count <= 0;`
465
466			#(20 * `SCLK_PERIOD);
467			`while (!linkup) begin`
468			`#1;`
469			`end`
470			`while (busy) begin`
471			`#1;`
472			`end`
473			`//Send a command`
474			#(824 * `SCLK_PERIOD);
475			`write_data_en <= 1;`
476			#(20 * `SCLK_PERIOD);
477			`while (!busy) begin`
478			`#1;`
479			`end`
480			`write_data_en <= 0;`
481			`end`
482			`*/`
483
484	4	cospan
485
486
487
488
489
490
491
492
493	2	cospan	`//Buffer Fill/Drain`
494	4	cospan	`always @ (posedge data_clk) begin`
495	2	cospan	`if (rst) begin`
496			`user_din <= 0;`
497			`user_din_stb <= 0;`
498			`user_din_activate <= 0;`
499			`din_count <= 0;`
500

Browse

Tools

Subversion Repositories nysa_sata

[/] [nysa_sata/] [trunk/] [sim/] [simple_tb.v] - Blame information for rev 4