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supplemental boards.">
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OPENCORES.ORG
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<table border=0 cellspacing=0 cellpadding=0><tr><td valign=top><li> </li></td><td><a href="/OIPC/flow.shtml">Design flow</a></td></tr></table>
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<p><b>Last updated</b>
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<table border=0 cellspacing=0 cellpadding=0><tr><td valign=top><li> </li></td><td><a href="/cores/rs232_syscon/people.shtml">rs232_syscon project</a></td></tr></table>
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<table border=0 cellspacing=0 cellpadding=0><tr><td valign=top><li> </li></td><td><a href="/projects.shtml">Projects page</a></td></tr></table>
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<TABLE CELLPADDING=4 CELLSPACING=1 BORDER=0 width=100%>
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<TR><TD COLSPAN=2 VALIGN=top BGCOLOR=#bbccff><strong><FONT SIZE=-1>Your interest in OpenCores is? </strong></TD></TR>
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<TD BGCOLOR=#ffffff><FONT SIZE=-1>Participation in development</TD>
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<TD BGCOLOR=#ffffff><FONT SIZE=-1>Just passing by</TD>
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<center><table>
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<INPUT TYPE=submit VALUE=" vote ">
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</table></td></tr>
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<TR><TD COLSPAN=2 VALIGN=top BGCOLOR=#ffffff>
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<table width=100% border=0 cellspacing=0 cellpadding=0><tr><td>
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<center><A HREF=/cores/ocrp-1/index.shtml?action=view>Results</A> </center> </td>
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</TD>
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</TABLE>
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</TD></TABLE></form> <p>
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<tr><td><center><a href="http://www.opencores.org/poll_archive/">Past polls</a></center></td></tr></table>
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<p><br><p><br>
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<TD width="10"> </TD>
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<TABLE border=0 cellPadding=5 cellSpacing=0 Valign="TOP" width=100%>
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<TD width="10"> </TD>
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<!-- BODY --><b><font size=+2 face="Helvetica, Arial"
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color=#bf0000>Project Name: </font></b>
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<p><b><font size=+2 face="Helvetica, Arial"
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color=#bf0000>OPENCORES Application Board 1 (OAB1)</font></b></p>
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<h1><font size="4">Introduction</font></h1>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">As
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you know, we have lots of free IP cores here, and we’ll have more coming soon.
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We have to use these cores otherwise they are invaluable. For this reason the
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idea of designing serials and open design boards are going to be available for
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any designers around the world. <o:p>
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</o:p>
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</span></p>
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<h1><span style="mso-bidi-font-size: 12.0pt"><font size="4">Objective<o:p>
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</o:p>
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</font></span></h1>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">This
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project is intended to: <o:p>
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</o:p>
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</span></p>
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<ul>
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<li>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
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design schematic can deal with analog signal and transport through Ethernet.
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<o:p>
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</o:p>
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</span></li>
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<li>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
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implementation CPU core and Ethernet core to one FPGA chip <o:p>
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</o:p>
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</span></li>
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<li>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
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program the necessary operation system and application software to achieve
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the goal.<o:p>
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</o:p>
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</span></li>
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<li>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
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build the prototype board.<o:p>
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</o:p>
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</span></li>
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<li>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
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do the test for all functions.<o:p>
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</o:p>
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</span></li>
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</ul>
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<h1><font size="4"><span style="font-family: Arial; mso-bidi-font-size: 12.0pt"> </span>Design
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Flow</font></h1>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">This
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project can be divided into two parts. The board design and the cores design.
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Anyone can use free or commercial tools to design and implement this project</span></p>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Board
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design flow can be done through four steps: <o:p>
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</o:p>
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</span></p>
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<ul>
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<li>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Block
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Diagram design: I hope we use word 97+ for easy modify and exchange. <o:p>
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</o:p>
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</span></li>
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<li>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Schematic
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entry: I will post schematic using PDF format. Anyone can also send me using
|
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PDF, protel99se or Cadence format. <o:p>
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</o:p>
|
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</span></li>
|
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<li>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Layout
|
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design: The final layout will use Allegro or Protel99se. <o:p>
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</o:p>
|
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</span></li>
|
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<li>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Board
|
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implementation: This is the final step in the design where the designer
|
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should work himself to produce his board unless we get funding or donation
|
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from PCB manufactory.<o:p>
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</o:p>
|
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</span></li>
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</ul>
|
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Cores
|
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|
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design flow can be done through five steps: <o:p>
|
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|
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</o:p>
|
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</span></p>
|
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<ul>
|
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<li>
|
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Design
|
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|
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entry: Doesn’t matter the tools, we exchange only VHDL or Verilog codes. <o:p>
|
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</o:p>
|
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</span></li>
|
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<li>
|
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Simulation:
|
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|
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I hope to use ModelSim or Active-HDL, but other tools also welcome.<o:p>
|
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</o:p>
|
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</span></li>
|
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<li>
|
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Synthesis:
|
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|
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I hope to use FPGA express, but other tools also welcome.<o:p>
|
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|
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</o:p>
|
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|
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</span></li>
|
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|
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<li>
|
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|
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Implementation:
|
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|
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I hope to use Xilinx FPGA.<o:p>
|
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|
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</o:p>
|
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|
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</span></li>
|
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|
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<li>
|
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|
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Programming
|
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|
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Download: Using onboard parallel cable.<o:p>
|
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|
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</o:p>
|
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|
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</span></li>
|
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|
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</ul>
|
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|
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<h1><font size="4"><span style="font-family: Arial; mso-bidi-font-size: 12.0pt"> </span>System
|
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|
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Description</font></h1>
|
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|
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">This
|
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|
|
is the Board block diagram<br style="mso-special-character: line-break">
|
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|
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<br style="mso-special-character: line-break">
|
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|
|
</span><span style="FONT-FAMILY: Verdana"><o:p>
|
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|
|
</o:p>
|
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|
|
</span><span style="FONT-FAMILY: Verdana"><o:p>
|
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|
|
<img border="0" src="ver02.jpg" width="750" height="675"></o:p>
|
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|
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</span></p>
|
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|
|
<p class="MsoNormal"><span style="FONT-FAMILY: Verdana"><span style="mso-spacerun: yes">
|
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|
|
</span>
|
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|
|
</span><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">The
|
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|
|
system is composed of 5 main blocks:<o:p>
|
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|
|
</o:p>
|
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|
|
</span></p>
|
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|
|
<ul>
|
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|
|
<li>
|
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|
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Xilinx
|
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|
|
FPGA, PROM and parallel interface<o:p>
|
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|
|
</o:p>
|
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|
|
</span></li>
|
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|
|
<li>
|
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|
|
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">SRAM
|
346 |
|
|
circuit<o:p>
|
347 |
|
|
</o:p>
|
348 |
|
|
</span></li>
|
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|
|
<li>
|
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|
|
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">ADC
|
351 |
|
|
and DAC interface<o:p>
|
352 |
|
|
</o:p>
|
353 |
|
|
</span></li>
|
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|
|
<li>
|
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|
|
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Ethernet
|
356 |
|
|
interface<o:p>
|
357 |
|
|
</o:p>
|
358 |
|
|
</span></li>
|
359 |
|
|
<li>
|
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|
|
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Power
|
361 |
|
|
and reset circuit<o:p>
|
362 |
|
|
</o:p>
|
363 |
|
|
</span></li>
|
364 |
|
|
</ul>
|
365 |
|
|
<h1><font size="4">Schematic Design</font></h1>
|
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|
|
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">TBD<o:p>
|
367 |
|
|
</o:p>
|
368 |
|
|
</span></p>
|
369 |
|
|
<h1><font size="4">Layout Design</font></h1>
|
370 |
|
|
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">TBD
|
371 |
|
|
<o:p>
|
372 |
|
|
</o:p>
|
373 |
|
|
</span></p>
|
374 |
|
|
<h1><font size="4">Current Status:</font></h1>
|
375 |
|
|
<p style="mso-margin-top-alt: auto; mso-margin-bottom-alt: auto"><span style="font-size: 14pt; font-family: Arial; mso-bidi-font-size: 12.0pt">2001.8.20
|
376 |
|
|
Upload Board block diagram <a href="ver01.JPG">version 0.1</a></span></p>
|
377 |
|
|
<p style="mso-margin-top-alt: auto; mso-margin-bottom-alt: auto"><span style="font-size: 14pt; font-family: Arial; mso-bidi-font-size: 12.0pt">2001.8.21
|
378 |
|
|
Upload Board block diagram <a href="ver02.jpg">version 0.2</a></span></p>
|
379 |
|
|
<h1><font size="4">Maintainer(s):</font></h1>
|
380 |
|
|
<h1><font size="3">Martin Jiang <a href="mailto:martinj@opencores.org"><span style="FONT-FAMILY: 'Times New Roman'; mso-bidi-font-family: Arial">martinj@opencores.org</span></a></font></h1>
|
381 |
|
|
<h1><font size="4">Mailing-list:</font></h1>
|
382 |
|
|
<p class="MsoNormal"><span style="FONT-FAMILY: Verdana"><a href="mailto:cores@opencores.org_NOSPAM">cores@opencores.org_NOSPAM</a><o:p>
|
383 |
|
|
</o:p>
|
384 |
|
|
</span></p>
|
385 |
|
|
<h1><font size="4">References tools and links</font></h1>
|
386 |
|
|
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt"><a href="http://xoscope.sourceforge.net/"><span style="mso-ascii-font-family: Arial; mso-hansi-font-family: Arial">Xscope
|
387 |
|
|
home page</span></a> <o:p>
|
388 |
|
|
</o:p>
|
389 |
|
|
</span></p>
|
390 |
|
|
<p class="MsoNormal"><span style="font-size: 14pt; font-family: Arial; mso-bidi-font-size: 12.0pt">SSM2141
|
391 |
|
|
<a href="http://products.analog.com/products/info.asp?product=SSM2141">Datasheet</a></span></p>
|
392 |
|
|
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">DAC8248
|
393 |
|
|
<a href="http://products.analog.com/products/info.asp?product=DAC8248">Datasheet</a>
|
394 |
|
|
</span></p>
|
395 |
|
|
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">AD7854
|
396 |
|
|
<a href="http://products.analog.com/products/info.asp?product=AD7854">Datasheet</a>
|
397 |
|
|
</span></p>
|
398 |
|
|
<p class="MsoNormal"><span style="font-size: 14pt; font-family: Arial; mso-bidi-font-size: 12.0pt">RTL8201</span><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">
|
399 |
|
|
<a href="http://www.realtek.com.tw/htm/download/cgi/DLd1.cgi?model=rtl8201&type=1"><span style="mso-ascii-font-family: Arial; mso-hansi-font-family: Arial">Datasheet</span></a><o:p></o:p>
|
400 |
|
|
</span></p>
|
401 |
|
|
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">PE68515
|
402 |
|
|
<a href="http://www.pulseeng.com/pdf/H303.pdf">Datasheet</a>
|
403 |
|
|
</span></p>
|
404 |
|
|
<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Xilinx
|
405 |
|
|
Virtex-E <a href="http://www.xilinx.com/partinfo/ds022.htm"><span style="mso-ascii-font-family: Arial; mso-hansi-font-family: Arial">Datasheet</span></a><o:p>
|
406 |
|
|
</o:p>
|
407 |
|
|
</span></p>
|
408 |
|
|
<p>
|
409 |
|
|
<font size=+1><b>Acknowledgment</b></font>
|
410 |
|
|
</TD>
|
411 |
|
|
<TD width="10"> </TD>
|
412 |
|
|
</TR>
|
413 |
|
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</TABLE>
|
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|
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|
415 |
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|
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|
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<TD valign=top width=150 bgcolor=#f0f0f0>
|
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|
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<center>
|
419 |
|
|
<table cellspacing=0 cellpadding=6 border=0><tr><td><a href="mailto:webmaster@opencores.org_NOSPAM">webmaster</a></td></tr></table>
|
420 |
|
|
</center>
|
421 |
|
|
</TD>
|
422 |
|
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<TD bgColor=#000000 height=1 valign=bottom><IMG alt='' height=1 src="dotty.gif" width=1></TD>
|
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<TD align=right bgColor=#ffffff vAlign=top>
|
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<table cellspacing=0 cellpadding=6 border=0><tr><td>
|
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|
426 |
|
|
|
427 |
|
|
<a target="_/cores/ocrp-1/index.shtml" href="http://www.opencores.org/editor?cmd=direct_edit&filename=/cores/ocrp-1/index.shtml">Last modified on
|
428 |
|
|
<!--webbot bot="Timestamp" startspan S-Type="EDITED"
|
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|
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S-Format="%m/%d/%y %I:%M:%S %p" -->08/21/01 03:20:20 PM<!--webbot
|
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|
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bot="Timestamp" i-CheckSum="26672" endspan -->
|
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</a></td></tr></table>
|
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|
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|
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</td>
|
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|
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|
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|
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<TABLE border=0 cellPadding=0 cellSpacing=0 Valign="TOP" width=100%>
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|
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|
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<td>
|
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|
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<center>
|
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|
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<table cellspacing=0 cellpadding=4 border=0><tr><td><center>Administrative contact: <a href="mailto:administration@opencores.org">administration@opencores.org</a></center></td></tr><tr><td>Copyright ©1999-2001 OPENCORES.ORG. All rights reserved.</td></tr></table>
|
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|
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