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[/] [oc54x/] [trunk/] [rtl/] [verilog/] [oc54_bshft.v] - Blame information for rev 5

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  OpenCores54 DSP, Barrel Shifter                            ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2002 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//
// Xilinx Virtex-E WC: 348 CLB slices @ 68MHz
//
 
//  CVS Log                                                                                                                  
//                                                                                                                                   
//  $Id: oc54_bshft.v,v 1.1.1.1 2002-04-10 09:34:40 rherveille Exp $                                                                                                                 
//                                                                                                                                   
//  $Date: 2002-04-10 09:34:40 $                                                                                                                 
//  $Revision: 1.1.1.1 $                                                                                                         
//  $Author: rherveille $                                                                                                            
//  $Locker:  $                                                                                                      
//  $State: Exp $                                                                                                                
//                                                                                                                                   
// Change History:                                                                                                   
//               $Log: not supported by cvs2svn $                                                                                        
 
`include "timescale.v"
 
module oc54_bshft (
        clk, ena,
        a, b, cb, db,
        bp_a, bp_b, bp_ar, bp_br,
        l_na, sxm, seli, selo,
        t, asm, imm,
        result, co
        );
 
//
// parameters
//
 
//
// inputs & outputs
//
input         clk;
input         ena;
input  [39:0] a, b;           // accumulator
input  [15:0] cb, db;         // memory data inputs
input  [39:0] bp_ar, bp_br;   // bypass a register, bypass b register
input         bp_a, bp_b;     // bypass select
input         sxm;            // sign extend mode
input         l_na;           // logical/not arithmetic shift
input  [ 1:0] seli;           // select operand (input)
input  [ 1:0] selo;           // select operator
input  [ 5:0] t;              // TREG, 6lsbs
input  [ 4:0] asm;            // asm bits
input  [ 4:0] imm;            // 5bit immediate value
output [39:0] result;
output        co;             // carry out output
 
reg [39:0] result;
reg        co;
 
//
// variables
//
 
reg [ 5:0] shift_cnt;
reg [39:0] operand;
 
//
// module body
//
 
 
//
// generate shift count
//
always@(selo or t or asm or imm)
        case (selo) // synopsis full_case parallel_case
                2'b00: shift_cnt = t;
                2'b01: shift_cnt = {asm[4], asm};
                2'b10: shift_cnt = {imm[4], imm};
                2'b11: shift_cnt = {imm[4:3], imm[3:0]};
        endcase
 
//
// generate operand
//
always@(seli or bp_a or a or bp_ar or bp_b or b or bp_br or cb or db)
        case (seli) // synopsis full_case parallel_case
                2'b00 : operand = bp_b ? bp_br : b;
                2'b01 : operand = bp_a ? bp_ar : a;
                2'b10 : operand = db;       // 16bit operand databus
                2'b11 : operand = {cb, db}; // 32bit operand
        endcase
 
//
// generate shifter
//
always@(posedge clk)
        if (ena)
                if (l_na) // logical shift
                        if (shift_cnt[5])
                                begin
                                        result[39:32] <= #1 8'h0;
                                        result[31: 0] <= #1 operand[31:0] >> (~shift_cnt[4:0] +1'h1);
                                        co            <= #1 operand[ ~shift_cnt[4:0] ];
                                end
                        else if ( ~|shift_cnt[4:0] )
                                begin
                                        result <= #1 operand;
                                        co     <= #1 1'b0;
                                end
                        else
                                begin
                                        result[39:32] <= #1 8'h0;
                                        result[31: 0] <= #1 operand[31:0] << shift_cnt[4:0];
                                        co            <= #1 operand[ 5'h1f - shift_cnt[4:0] ];
                                end
                else      // arithmetic shift
                        if (shift_cnt[5])
                                begin
                                        if (sxm)
                                                result <= #1 { {16{operand[39]}} ,operand} >> (~shift_cnt[4:0] +1'h1);
                                        else
                                                result <= #1 operand >> (~shift_cnt[4:0] +1'h1);
                                        co     <= #1 operand[ ~shift_cnt[4:0] ];
                                end
                        else
                                begin
                                        result <= #1 operand << shift_cnt[4:0];
                                        co     <= #1 operand[ 6'h27 - shift_cnt[4:0] ];
                                end
 
endmodule
 
 
 

Line No.	Rev	Author	Line
1	2	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OpenCores54 DSP, Barrel Shifter ////`
4			`//// ////`
5			`//// Author: Richard Herveille ////`
6			`//// richard@asics.ws ////`
7			`//// www.asics.ws ////`
8			`//// ////`
9			`/////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2002 Richard Herveille ////`
12			`//// richard@asics.ws ////`
13			`//// ////`
14			`//// This source file may be used and distributed without ////`
15			`//// restriction provided that this copyright statement is not ////`
16			`//// removed from the file and that any derivative work contains ////`
17			`//// the original copyright notice and the associated disclaimer.////`
18			`//// ////`
19			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
20			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
21			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
22			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
23			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
24			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
25			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
26			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
27			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
28			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
29			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
30			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
31			`//// POSSIBILITY OF SUCH DAMAGE. ////`
32			`//// ////`
33			`/////////////////////////////////////////////////////////////////////`
34
35			`//`
36			`// Xilinx Virtex-E WC: 348 CLB slices @ 68MHz`
37			`//`
38
39			`// CVS Log`
40			`//`
41			`// $Id: oc54_bshft.v,v 1.1.1.1 2002-04-10 09:34:40 rherveille Exp $`
42			`//`
43			`// $Date: 2002-04-10 09:34:40 $`
44			`// $Revision: 1.1.1.1 $`
45			`// $Author: rherveille $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51
52			`include "timescale.v"
53
54			`module oc54_bshft (`
55			`clk, ena,`
56			`a, b, cb, db,`
57			`bp_a, bp_b, bp_ar, bp_br,`
58			`l_na, sxm, seli, selo,`
59			`t, asm, imm,`
60			`result, co`
61			`);`
62
63			`//`
64			`// parameters`
65			`//`
66
67			`//`
68			`// inputs & outputs`
69			`//`
70			`input clk;`
71			`input ena;`
72			`input [39:0] a, b; // accumulator`
73			`input [15:0] cb, db; // memory data inputs`
74			`input [39:0] bp_ar, bp_br; // bypass a register, bypass b register`
75			`input bp_a, bp_b; // bypass select`
76			`input sxm; // sign extend mode`
77			`input l_na; // logical/not arithmetic shift`
78			`input [ 1:0] seli; // select operand (input)`
79			`input [ 1:0] selo; // select operator`
80			`input [ 5:0] t; // TREG, 6lsbs`
81			`input [ 4:0] asm; // asm bits`
82			`input [ 4:0] imm; // 5bit immediate value`
83			`output [39:0] result;`
84			`output co; // carry out output`
85
86			`reg [39:0] result;`
87			`reg co;`
88
89			`//`
90			`// variables`
91			`//`
92
93			`reg [ 5:0] shift_cnt;`
94			`reg [39:0] operand;`
95
96			`//`
97			`// module body`
98			`//`
99
100
101			`//`
102			`// generate shift count`
103			`//`
104			`always@(selo or t or asm or imm)`
105			`case (selo) // synopsis full_case parallel_case`
106			`2'b00: shift_cnt = t;`
107			`2'b01: shift_cnt = {asm[4], asm};`
108			`2'b10: shift_cnt = {imm[4], imm};`
109			`2'b11: shift_cnt = {imm[4:3], imm[3:0]};`
110			`endcase`
111
112			`//`
113			`// generate operand`
114			`//`
115			`always@(seli or bp_a or a or bp_ar or bp_b or b or bp_br or cb or db)`
116			`case (seli) // synopsis full_case parallel_case`
117			`2'b00 : operand = bp_b ? bp_br : b;`
118			`2'b01 : operand = bp_a ? bp_ar : a;`
119			`2'b10 : operand = db; // 16bit operand databus`
120			`2'b11 : operand = {cb, db}; // 32bit operand`
121			`endcase`
122
123			`//`
124			`// generate shifter`
125			`//`
126			`always@(posedge clk)`
127			`if (ena)`
128			`if (l_na) // logical shift`
129			`if (shift_cnt[5])`
130			`begin`
131			`result[39:32] <= #1 8'h0;`
132			`result[31: 0] <= #1 operand[31:0] >> (~shift_cnt[4:0] +1'h1);`
133			`co <= #1 operand[ ~shift_cnt[4:0] ];`
134			`end`
135			`else if ( ~\|shift_cnt[4:0] )`
136			`begin`
137			`result <= #1 operand;`
138			`co <= #1 1'b0;`
139			`end`
140			`else`
141			`begin`
142			`result[39:32] <= #1 8'h0;`
143			`result[31: 0] <= #1 operand[31:0] << shift_cnt[4:0];`
144			`co <= #1 operand[ 5'h1f - shift_cnt[4:0] ];`
145			`end`
146			`else // arithmetic shift`
147			`if (shift_cnt[5])`
148			`begin`
149			`if (sxm)`
150			`result <= #1 { {16{operand[39]}} ,operand} >> (~shift_cnt[4:0] +1'h1);`
151			`else`
152			`result <= #1 operand >> (~shift_cnt[4:0] +1'h1);`
153			`co <= #1 operand[ ~shift_cnt[4:0] ];`
154			`end`
155			`else`
156			`begin`
157			`result <= #1 operand << shift_cnt[4:0];`
158			`co <= #1 operand[ 6'h27 - shift_cnt[4:0] ];`
159			`end`
160
161			`endmodule`
162
163
164

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[/] [oc54x/] [trunk/] [rtl/] [verilog/] [oc54_bshft.v] - Blame information for rev 5