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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  OpenCores54 DSP, Compare Select and Store Unit (CSSU)      ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2002 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//
// NOTE: Read the pipeline information for the CMPS instruction
//
 
//
// Xilinx Virtex-E WC: 41 CLB slices @ 130MHz
//
 
//  CVS Log                                                                                                                  
//                                                                                                                                   
//  $Id: oc54_cssu.v,v 1.1.1.1 2002-04-10 09:34:41 rherveille Exp $                                                                                                                  
//                                                                                                                                   
//  $Date: 2002-04-10 09:34:41 $                                                                                                                 
//  $Revision: 1.1.1.1 $                                                                                                         
//  $Author: rherveille $                                                                                                            
//  $Locker:  $                                                                                                      
//  $State: Exp $                                                                                                                
//                                                                                                                                   
// Change History:                                                                                                   
//               $Log: not supported by cvs2svn $                                                                                        
 
`include "timescale.v"
 
module oc54_cssu (
        clk, ena,
        sel_acc, is_cssu,
        a, b, s,
        tco,
        trn, result
        );
 
//
// parameters
//
 
//
// inputs & outputs
//
input         clk;
input         ena;
input         sel_acc;           // select input
input         is_cssu;           // is this a cssu operation ?
input  [39:0] a, b, s;           // accumulators, shifter input
output        tco;               // tc-out
output [15:0] trn, result;
 
reg        tco;
reg [15:0] trn, result;
 
//
// variables
//
 
wire [31:0] acc;      // selected accumulator
wire        acc_cmp;  // acc[31;16]>acc[15:0] ??
//
// module body
//
 
//
// generate input selection
//
 
// input selection
assign acc = sel_acc ? b[31:0] : a[31:0];
 
assign acc_cmp = acc[31:16] > acc[15:0];
 
// result
always@(posedge clk)
        if (ena)
        begin
                if (is_cssu)
                        if (acc_cmp)
                                result <= #1 acc[31:16];
                        else
                                result <= #1 acc[15:0];
                else
                        result <= #1 s[15:0];
 
                if (is_cssu)
                        trn <= #1 {trn[14:0], ~acc_cmp};
 
                tco <= #1 ~acc_cmp;
        end
endmodule
 
 

Line No.	Rev	Author	Line
1	2	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OpenCores54 DSP, Compare Select and Store Unit (CSSU) ////`
4			`//// ////`
5			`//// Author: Richard Herveille ////`
6			`//// richard@asics.ws ////`
7			`//// www.asics.ws ////`
8			`//// ////`
9			`/////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2002 Richard Herveille ////`
12			`//// richard@asics.ws ////`
13			`//// ////`
14			`//// This source file may be used and distributed without ////`
15			`//// restriction provided that this copyright statement is not ////`
16			`//// removed from the file and that any derivative work contains ////`
17			`//// the original copyright notice and the associated disclaimer.////`
18			`//// ////`
19			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
20			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
21			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
22			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
23			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
24			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
25			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
26			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
27			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
28			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
29			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
30			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
31			`//// POSSIBILITY OF SUCH DAMAGE. ////`
32			`//// ////`
33			`/////////////////////////////////////////////////////////////////////`
34
35			`//`
36			`// NOTE: Read the pipeline information for the CMPS instruction`
37			`//`
38
39			`//`
40			`// Xilinx Virtex-E WC: 41 CLB slices @ 130MHz`
41			`//`
42
43			`// CVS Log`
44			`//`
45			`// $Id: oc54_cssu.v,v 1.1.1.1 2002-04-10 09:34:41 rherveille Exp $`
46			`//`
47			`// $Date: 2002-04-10 09:34:41 $`
48			`// $Revision: 1.1.1.1 $`
49			`// $Author: rherveille $`
50			`// $Locker: $`
51			`// $State: Exp $`
52			`//`
53			`// Change History:`
54			`// $Log: not supported by cvs2svn $`
55
56			`include "timescale.v"
57
58			`module oc54_cssu (`
59			`clk, ena,`
60			`sel_acc, is_cssu,`
61			`a, b, s,`
62			`tco,`
63			`trn, result`
64			`);`
65
66			`//`
67			`// parameters`
68			`//`
69
70			`//`
71			`// inputs & outputs`
72			`//`
73			`input clk;`
74			`input ena;`
75			`input sel_acc; // select input`
76			`input is_cssu; // is this a cssu operation ?`
77			`input [39:0] a, b, s; // accumulators, shifter input`
78			`output tco; // tc-out`
79			`output [15:0] trn, result;`
80
81			`reg tco;`
82			`reg [15:0] trn, result;`
83
84			`//`
85			`// variables`
86			`//`
87
88			`wire [31:0] acc; // selected accumulator`
89			`wire acc_cmp; // acc[31;16]>acc[15:0] ??`
90			`//`
91			`// module body`
92			`//`
93
94			`//`
95			`// generate input selection`
96			`//`
97
98			`// input selection`
99			`assign acc = sel_acc ? b[31:0] : a[31:0];`
100
101			`assign acc_cmp = acc[31:16] > acc[15:0];`
102
103			`// result`
104			`always@(posedge clk)`
105			`if (ena)`
106			`begin`
107			`if (is_cssu)`
108			`if (acc_cmp)`
109			`result <= #1 acc[31:16];`
110			`else`
111			`result <= #1 acc[15:0];`
112			`else`
113			`result <= #1 s[15:0];`
114
115			`if (is_cssu)`
116			`trn <= #1 {trn[14:0], ~acc_cmp};`
117
118			`tco <= #1 ~acc_cmp;`
119			`end`
120			`endmodule`
121
122

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[/] [oc54x/] [trunk/] [rtl/] [verilog/] [oc54_cssu.v] - Blame information for rev 5