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[/] [oc54x/] [trunk/] [rtl/] [verilog/] [oc54_mac.v] - Blame information for rev 5

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  OpenCores54 DSP, MAC                                       ////
////                                                             ////
////  Author: Richard Herveille                                  ////
////          richard@asics.ws                                   ////
////          www.asics.ws                                       ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2002 Richard Herveille                        ////
////                    richard@asics.ws                         ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//
// Xilinx Virtex-E WC: 296 CLB slices @ 64MHz
//
 
//  CVS Log                                                                                                                  
//                                                                                                                                   
//  $Id: oc54_mac.v,v 1.1.1.1 2002-04-10 09:34:41 rherveille Exp $                                                                                                                   
//                                                                                                                                   
//  $Date: 2002-04-10 09:34:41 $                                                                                                                 
//  $Revision: 1.1.1.1 $                                                                                                         
//  $Author: rherveille $                                                                                                            
//  $Locker:  $                                                                                                      
//  $State: Exp $                                                                                                                
//                                                                                                                                   
// Change History:                                                                                                   
//               $Log: not supported by cvs2svn $                                                                                        
 
`include "timescale.v"
 
module oc54_mac (
        clk, ena,
        a, b, t, p, c, d,
        sel_xm, sel_ym, sel_ya,
        bp_a, bp_b, bp_ar, bp_br,
        xm_s, ym_s,
        ovm, frct, smul, add_sub,
        result
        );
 
//
// parameters
//
 
//
// inputs & outputs
//
input         clk;
input         ena;
input  [15:0] t, p, c, d;               // TREG, p-bus, c-bus, d-bus inputs
input  [39:0] a, b;                     // accumulator inputs
input  [ 1:0] sel_xm, sel_ym, sel_ya;   // input selects
input  [39:0] bp_ar, bp_br;             // bypass accumulator a / b
input         bp_a, bp_b;               // bypass selects
input         xm_s, ym_s;               // sign extend xm, ym
input         ovm, frct, smul, add_sub;
output [39:0] result;
 
reg [39:0] result;
 
//
// variables
//
reg  [16:0] xm, ym;              // multiplier inputs
reg  [39:0] ya;                  // adder Y-input
 
reg  [33:0] mult_res;            // multiplier result
wire [33:0] imult_res;           // actual multiplier
reg  [39:0] iresult;             // mac-result
 
/////////////////
// module body //
/////////////////
 
//
// generate input selection
//
 
// xm
always@(posedge clk)
        if (ena)
                case(sel_xm) // synopsis full_case parallel_case
                        2'b00 : xm <= #1 {xm_s ? t[15] : 1'b0, t};
                        2'b01 : xm <= #1 {xm_s ? d[15] : 1'b0, d};
                        2'b10 : xm <= #1 bp_a ? bp_ar[32:16] : a[32:16];
                        2'b11 : xm <= #1 17'h0;
                endcase
 
// ym
always@(posedge clk)
        if (ena)
                case(sel_ym) // synopsis full_case parallel_case
                        2'b00 : ym <= #1 {ym_s ? p[15] : 1'b0, p};
                        2'b01 : ym <= #1 bp_a ? bp_ar[32:16] : a[32:16];
                        2'b10 : ym <= #1 {ym_s ? d[15] : 1'b0, d};
                        2'b11 : ym <= #1 {ym_s ? c[15] : 1'b0, c};
                endcase
 
// ya
always@(posedge clk)
        if (ena)
                casex(sel_ya) // synopsis full_case parallel_case
                        2'b00 : ya <= #1 bp_a ? bp_ar : a;
                        2'b01 : ya <= #1 bp_b ? bp_br : b;
                        2'b1? : ya <= #1 40'h0;
                endcase
 
//
// generate multiplier
//
assign imult_res = (xm * ym); // actual multiplier
 
always@(xm or ym or smul or ovm or frct or imult_res)
        if (smul && ovm && frct && (xm[15:0] == 16'h8000) && (ym[15:0] == 16'h8000) )
                mult_res = 34'h7ff_ffff;
        else if (frct)
                mult_res = {imult_res[32:0], 1'b0}; // (imult_res << 1)
        else
                mult_res = imult_res;
 
//
// generate mac-unit
//
always@(mult_res or ya or add_sub)
        if (add_sub)
                iresult = mult_res + ya;
        else
                iresult = mult_res - ya;
 
//
// generate registers
//
 
// result
always@(posedge clk)
        if (ena)
                result <= #1 iresult;
 
endmodule
 
 

Line No.	Rev	Author	Line
1	2	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OpenCores54 DSP, MAC ////`
4			`//// ////`
5			`//// Author: Richard Herveille ////`
6			`//// richard@asics.ws ////`
7			`//// www.asics.ws ////`
8			`//// ////`
9			`/////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2002 Richard Herveille ////`
12			`//// richard@asics.ws ////`
13			`//// ////`
14			`//// This source file may be used and distributed without ////`
15			`//// restriction provided that this copyright statement is not ////`
16			`//// removed from the file and that any derivative work contains ////`
17			`//// the original copyright notice and the associated disclaimer.////`
18			`//// ////`
19			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
20			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
21			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
22			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
23			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
24			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
25			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
26			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
27			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
28			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
29			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
30			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
31			`//// POSSIBILITY OF SUCH DAMAGE. ////`
32			`//// ////`
33			`/////////////////////////////////////////////////////////////////////`
34
35			`//`
36			`// Xilinx Virtex-E WC: 296 CLB slices @ 64MHz`
37			`//`
38
39			`// CVS Log`
40			`//`
41			`// $Id: oc54_mac.v,v 1.1.1.1 2002-04-10 09:34:41 rherveille Exp $`
42			`//`
43			`// $Date: 2002-04-10 09:34:41 $`
44			`// $Revision: 1.1.1.1 $`
45			`// $Author: rherveille $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51
52			`include "timescale.v"
53
54			`module oc54_mac (`
55			`clk, ena,`
56			`a, b, t, p, c, d,`
57			`sel_xm, sel_ym, sel_ya,`
58			`bp_a, bp_b, bp_ar, bp_br,`
59			`xm_s, ym_s,`
60			`ovm, frct, smul, add_sub,`
61			`result`
62			`);`
63
64			`//`
65			`// parameters`
66			`//`
67
68			`//`
69			`// inputs & outputs`
70			`//`
71			`input clk;`
72			`input ena;`
73			`input [15:0] t, p, c, d; // TREG, p-bus, c-bus, d-bus inputs`
74			`input [39:0] a, b; // accumulator inputs`
75			`input [ 1:0] sel_xm, sel_ym, sel_ya; // input selects`
76			`input [39:0] bp_ar, bp_br; // bypass accumulator a / b`
77			`input bp_a, bp_b; // bypass selects`
78			`input xm_s, ym_s; // sign extend xm, ym`
79			`input ovm, frct, smul, add_sub;`
80			`output [39:0] result;`
81
82			`reg [39:0] result;`
83
84			`//`
85			`// variables`
86			`//`
87			`reg [16:0] xm, ym; // multiplier inputs`
88			`reg [39:0] ya; // adder Y-input`
89
90			`reg [33:0] mult_res; // multiplier result`
91			`wire [33:0] imult_res; // actual multiplier`
92			`reg [39:0] iresult; // mac-result`
93
94			`/////////////////`
95			`// module body //`
96			`/////////////////`
97
98			`//`
99			`// generate input selection`
100			`//`
101
102			`// xm`
103			`always@(posedge clk)`
104			`if (ena)`
105			`case(sel_xm) // synopsis full_case parallel_case`
106			`2'b00 : xm <= #1 {xm_s ? t[15] : 1'b0, t};`
107			`2'b01 : xm <= #1 {xm_s ? d[15] : 1'b0, d};`
108			`2'b10 : xm <= #1 bp_a ? bp_ar[32:16] : a[32:16];`
109			`2'b11 : xm <= #1 17'h0;`
110			`endcase`
111
112			`// ym`
113			`always@(posedge clk)`
114			`if (ena)`
115			`case(sel_ym) // synopsis full_case parallel_case`
116			`2'b00 : ym <= #1 {ym_s ? p[15] : 1'b0, p};`
117			`2'b01 : ym <= #1 bp_a ? bp_ar[32:16] : a[32:16];`
118			`2'b10 : ym <= #1 {ym_s ? d[15] : 1'b0, d};`
119			`2'b11 : ym <= #1 {ym_s ? c[15] : 1'b0, c};`
120			`endcase`
121
122			`// ya`
123			`always@(posedge clk)`
124			`if (ena)`
125			`casex(sel_ya) // synopsis full_case parallel_case`
126			`2'b00 : ya <= #1 bp_a ? bp_ar : a;`
127			`2'b01 : ya <= #1 bp_b ? bp_br : b;`
128			`2'b1? : ya <= #1 40'h0;`
129			`endcase`
130
131			`//`
132			`// generate multiplier`
133			`//`
134			`assign imult_res = (xm * ym); // actual multiplier`
135
136			`always@(xm or ym or smul or ovm or frct or imult_res)`
137			`if (smul && ovm && frct && (xm[15:0] == 16'h8000) && (ym[15:0] == 16'h8000) )`
138			`mult_res = 34'h7ff_ffff;`
139			`else if (frct)`
140			`mult_res = {imult_res[32:0], 1'b0}; // (imult_res << 1)`
141			`else`
142			`mult_res = imult_res;`
143
144			`//`
145			`// generate mac-unit`
146			`//`
147			`always@(mult_res or ya or add_sub)`
148			`if (add_sub)`
149			`iresult = mult_res + ya;`
150			`else`
151			`iresult = mult_res - ya;`
152
153			`//`
154			`// generate registers`
155			`//`
156
157			`// result`
158			`always@(posedge clk)`
159			`if (ena)`
160			`result <= #1 iresult;`
161
162			`endmodule`
163
164

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[/] [oc54x/] [trunk/] [rtl/] [verilog/] [oc54_mac.v] - Blame information for rev 5