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rherveille |
/////////////////////////////////////////////////////////////////////
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//// ////
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//// OpenCores54 DSP, Temporary Register (TREG) ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//
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// NOTE: Read the pipeline information for the CMPS instruction
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//
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//
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// Xilinx Virtex-E WC: 41 CLB slices @ 130MHz
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//
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// CVS Log
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//
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// $Id: oc54_treg.v,v 1.1.1.1 2002-04-10 09:34:41 rherveille Exp $
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//
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// $Date: 2002-04-10 09:34:41 $
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// $Revision: 1.1.1.1 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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`include "timescale.v"
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module oc54_treg (
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clk, ena,
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seli, we,
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exp, d,
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result
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);
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//
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// parameters
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//
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//
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// inputs & outputs
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//
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input clk;
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input ena;
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input seli; // select input
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input we; // store result
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input [ 5:0] exp; // exponent encoder input
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input [15:0] d; // DB input
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output [15:0] result;
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reg [15:0] result;
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//
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// variables
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//
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//
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// module body
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//
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//
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// generate input selection
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//
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// result
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always@(posedge clk)
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if (ena)
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if (we)
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result <= #1 seli ? {10'h0, exp} : d;
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endmodule
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