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---------------------------------------------------------------------------------------------------
--
-- Title       : cfft
-- Design      : cfft
-- Author      : ZHAO Ming
-- email        : sradio@opencores.org
--
---------------------------------------------------------------------------------------------------
--
-- File        : cfft.vhd
-- Generated   : Thu Oct  3 03:03:58 2002
--
---------------------------------------------------------------------------------------------------
--
-- Description : radix 4 1024 point FFT input 12 bit Output 14 bit with 
--               limit and overfall processing internal
--
--              The gain is 0.0287 for FFT and 29.4 for IFFT
--
--                              The output is 4-based reversed ordered, it means
--                              a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1
--                              
--
---------------------------------------------------------------------------------------------------
 
 
---------------------------------------------------------------------------------------------------
--
-- port :
--                      clk : main clk          -- I have test 90M with Xilinx virtex600E
--                      rst : globe reset   -- '1' for reset
--                      start : start fft       -- one clock '1' before data input
--                      invert : '0' for fft and '1' for ifft, it is sampled when start is '1' 
--                      Iin,Qin : data input-- following start immediately, input data
--                              -- power should not be too big
--                      inputbusy : if it change to '0' then next fft is enable
--                      outdataen : when it is '1', the valid data is output
--                      Iout,Qout : fft data output when outdataen is '1'                                                                      
--
---------------------------------------------------------------------------------------------------
--
-- Revisions       :    0
-- Revision Number :    1
-- Version         :    1.1.0
-- Date            :    Oct 17 2002
-- Modifier        :    ZHAO Ming 
-- Desccription    :    Data width configurable 
--
---------------------------------------------------------------------------------------------------
--
-- Revisions       :    0
-- Revision Number :    2
-- Version         :    1.2.0
-- Date            :    Oct 18 2002
-- Modifier        :    ZHAO Ming 
-- Desccription    :    Point configurable
--                      FFT Gain                IFFT GAIN
--                               256    0.0698                  17.9
--                              1024    0.0287                  29.4
--                              4096    0.0118                  48.2742
--                   
--
---------------------------------------------------------------------------------------------------
--
-- Revisions       :    0
-- Revision Number :    3
-- Version         :    1.3.0
-- Date            :    Nov 19 2002
-- Modifier        :    ZHAO Ming 
-- Desccription    :    add output data position indication 
--                   
--
---------------------------------------------------------------------------------------------------
 
  library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  use IEEE.STD_LOGIC_ARITH.all;
  use IEEE.STD_LOGIC_UNSIGNED.all;
 
  entity cfft is
    generic (
           Tx_nRx : natural :=1; -- tx = 1, rx = 0
      WIDTH : natural := 12;
      POINT : natural := 64;
      STAGE : natural := 3              -- STAGE=log4(POINT)
      );
    port(
      rst         : in  std_logic;
      Iin         : in  std_logic_vector(WIDTH-1 downto 0);
      Qin         : in  std_logic_vector(WIDTH-1 downto 0);
      Iout        : out std_logic_vector(WIDTH+1 downto 0);
      Qout        : out std_logic_vector(WIDTH+1 downto 0);
      factorstart : in  std_logic;
      cfft4start  : in  std_logic;
 
      ClkIn : in std_logic;
 
      sel_mux     : in std_logic;
      inv         : in std_logic;
 
      wen_in     : in std_logic;
      addrin_in  : in std_logic_vector(2*stage-Tx_nRx downto 0);
      addrout_in : in std_logic_vector(2*stage-Tx_nRx downto 0);
 
      wen_proc     : in std_logic;
      addrin_proc  : in std_logic_vector(2*stage-1 downto 0);
      addrout_proc : in std_logic_vector(2*stage-1 downto 0);
 
      wen_out     : in std_logic;
      addrin_out  : in std_logic_vector(2*stage-1 downto 0);
      addrout_out : in std_logic_vector(2*stage-1 downto 0));
 
  end cfft;
 
 
  architecture cfft of cfft is
 
    component mux
      generic (
        width : natural);
      port (
        inRa : in  std_logic_vector(WIDTH-1 downto 0);
        inIa : in  std_logic_vector(WIDTH-1 downto 0);
        inRb : in  std_logic_vector(WIDTH-1 downto 0);
        inIb : in  std_logic_vector(WIDTH-1 downto 0);
        outR : out std_logic_vector(WIDTH-1 downto 0);
        outI : out std_logic_vector(WIDTH-1 downto 0);
 
                  clk  : in  std_logic;
        sel  : in  std_logic);
    end component;
 
    component conj
      generic (
        width : natural);
      port (
 
                  inR : in  std_logic_vector(WIDTH-1 downto 0);
        inI : in  std_logic_vector(WIDTH-1 downto 0);
        outR : out std_logic_vector(WIDTH-1 downto 0);
        outI : out std_logic_vector(WIDTH-1 downto 0);
 
                  clk  : in  std_logic;
        conj  : in  std_logic);
    end component;
 
    component ram
      generic (
        width      : natural;
        depth      : natural;
        Addr_width : natural);
      port (
        clkin   : in  std_logic;
        wen     : in  std_logic;
        addrin  : in  std_logic_vector(Addr_width-1 downto 0);
        dinR    : in  std_logic_vector(width-1 downto 0);
        dinI    : in  std_logic_vector(width-1 downto 0);
        clkout  : in  std_logic;
        addrout : in  std_logic_vector(Addr_width-1 downto 0);
        doutR   : out std_logic_vector(width-1 downto 0);
        doutI   : out std_logic_vector(width-1 downto 0));
    end component;
 
    component cfft4
      generic (
        width : natural
        );
      port(
        clk   : in  std_logic;
        rst   : in  std_logic;
        start : in  std_logic;
                  invert : in std_logic;
        I     : in  std_logic_vector(WIDTH-1 downto 0);
        Q     : in  std_logic_vector(WIDTH-1 downto 0);
        Iout  : out std_logic_vector(WIDTH+1 downto 0);
        Qout  : out std_logic_vector(WIDTH+1 downto 0)
        );
    end component;
 
    component div4limit
      generic (
        WIDTH : natural
        );
      port(
        clk : in  std_logic;
        D   : in  std_logic_vector(WIDTH+3 downto 0);
        Q   : out std_logic_vector(WIDTH-1 downto 0)
        );
    end component;
 
    component mulfactor
      generic (
        WIDTH : natural;
        STAGE : natural
        );
      port(
        clk   : in  std_logic;
        rst   : in  std_logic;
        angle : in  signed(2*STAGE-1 downto 0);
        I     : in  signed(WIDTH+1 downto 0);
        Q     : in  signed(WIDTH+1 downto 0);
        Iout  : out signed(WIDTH+3 downto 0);
        Qout  : out signed(WIDTH+3 downto 0)
        );
    end component;
 
    component rofactor
      generic (
        POINT : natural;
        STAGE : natural
        );
      port(
        clk   : in  std_logic;
        rst   : in  std_logic;
        start : in  std_logic;
                  invert : in std_logic;
        angle : out std_logic_vector(2*STAGE-1 downto 0)
        );
    end component;
 
 
    component blockdram
      generic (
        depth  : natural;
        Dwidth : natural;
        Awidth : natural);
      port (
        clkin   : in  std_logic;
        wen     : in  std_logic;
        addrin  : in  std_logic_vector(Awidth-1 downto 0);
        din     : in  std_logic_vector(Dwidth-1 downto 0);
        clkout  : in  std_logic;
        addrout : in  std_logic_vector(Awidth-1 downto 0);
        dout    : out std_logic_vector(Dwidth-1 downto 0));
    end component;
 
    signal MuxInRa, MuxInIa, MuxInRb, MuxInIb : std_logic_vector(WIDTH-1 downto 0)    := (others  => '0');
    signal conjInR, conjInI                   : std_logic_vector(WIDTH-1 downto 0)    := (others  => '0');
    signal cfft4InR, cfft4InI                 : std_logic_vector(WIDTH-1 downto 0)    := (others  => '0');
    signal cfft4outR, cfft4outI               : std_logic_vector(WIDTH+1 downto 0)    := (others  => '0');
    signal MulOutR, MulOutI                   : signed(WIDTH+3 downto 0)              := (others  => '0');
    signal fftR, fftI                         : std_logic_vector(WIDTH-1 downto 0)    := (others  => '0');
    signal angle                              : std_logic_vector(2*STAGE-1 downto 0 ) := ( others => '0');
         signal invert : std_logic;
 
  begin
 
TX:if Tx_nRx = 1 generate
    RamIn : ram
      generic map (
        width      => WIDTH,
        depth      => POINT,
        Addr_width => 2*STAGE)
      port map (
        clkin   => ClkIn,
        wen     => wen_in,
        addrin  => addrin_in,
        dinR    => Iin,
        dinI    => Qin,
        clkout  => ClkIn,
        addrout => addrout_in,
        doutR   => MuxInRa,
        doutI   => MuxInIa);
 
         RamOut : ram
      generic map (
        width      => WIDTH+2,
        depth      => POINT,
        Addr_width => 2*STAGE)
      port map (
        clkin   => ClkIn,
        wen     => wen_out,
        addrin  => addrin_out,
        dinR    => cfft4outR,
        dinI    => cfft4outR,
        clkout  => ClkIn,
        addrout => addrout_out,
        doutR   => Iout,
        doutI   => open);
end generate;
 
RX:if Tx_nRx = 0 generate
    RamIn : ram
      generic map (
        width      => WIDTH,
        depth      => 2*POINT,
        Addr_width => 2*STAGE+1)
      port map (
        clkin   => ClkIn,
        wen     => wen_in,
        addrin  => addrin_in,
        dinR    => Iin,
        dinI    => Qin,
        clkout  => ClkIn,
        addrout => addrout_in,
        doutR   => MuxInRa,
        doutI   => open);
 
        MuxinIa <= (others => '0');
 
         RamOut : ram
      generic map (
        width      => WIDTH+2,
        depth      => POINT,
        Addr_width => 2*STAGE)
      port map (
        clkin   => ClkIn,
        wen     => wen_out,
        addrin  => addrin_out,
        dinR    => cfft4outR,
        dinI    => cfft4outR,
        clkout  => ClkIn,
        addrout => addrout_out,
        doutR   => Iout,
        doutI   => Qout);
 
end generate;
 
 
    RamProc : ram
      generic map (
        width      => WIDTH,
        depth      => POINT,
        Addr_width => 2*STAGE)
      port map (
        clkin   => ClkIn,
        wen     => wen_proc,
        addrin  => addrin_proc,
        dinR    => fftR,
        dinI    => fftI,
        clkout  => ClkIn,
        addrout => addrout_proc,
        doutR   => MuxInRb,
        doutI   => MuxInIb);
 
    mux_1 : mux
      generic map (
        width => width)
      port map (
        inRa => MuxInRa,
        inIa => MuxInIa,
        inRb => MuxInRb,
        inIb => MuxInIb,
        outR => conjInR,
        outI => conjInI,
                  clk  => clkin,
        sel  => sel_mux);
 
invert <= (inv and conv_std_logic_vector(Tx_nRx,1)(0));
 
    conj_1: conj
      generic map (
        width => width)
      port map (
 
        inR   => conjInR,
        inI   => conjInI,
        outR  => cfft4InR,
        outI  => cfft4InI,
                  clk   => Clkin,
        conj  => invert);
 
    acfft4 : cfft4
      generic map (
        WIDTH => WIDTH
        )
      port map (
        clk   => ClkIn,
        rst   => rst,
        start => cfft4start,
                  invert => conv_std_logic_vector(Tx_nRx,1)(0),
        I     => cfft4InR,
        Q     => cfft4InI,
        Iout  => cfft4outR,
        Qout  => cfft4outI
        );
 
    amulfactor : mulfactor
      generic map (
        WIDTH => WIDTH,
        STAGE => STAGE
        )
      port map (
        clk   => ClkIn,
        rst   => rst,
        angle => signed(angle),
        I     => signed(cfft4outR),
        Q     => signed(cfft4outI),
        Iout  => MulOutR,
        Qout  => MulOutI
        );
 
    arofactor : rofactor
      generic map (
        POINT => POINT,
        STAGE => STAGE
        )
      port map (
        clk   => ClkIn,
        rst   => rst,
        start => factorstart,
                  invert => conv_std_logic_vector(Tx_nRx,1)(0), -- IFFT
        angle => angle
        );
 
    Rlimit : div4limit
      generic map (
        WIDTH => WIDTH
        )
      port map (
        clk => ClkIn,
        D   => std_logic_vector(MulOutR),
        Q   => fftR
        );
    Ilimit : div4limit
      generic map (
        WIDTH => WIDTH
        )
      port map (
        clk => ClkIn,
        D   => std_logic_vector(MulOutI),
        Q   => fftI
        );
 
  end cfft;

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[/] [ofdm/] [branches/] [avendor/] [cfft.vhd] - Blame information for rev 13

Line No.	Rev	Author	Line
1	4	tmsiqueira	`---------------------------------------------------------------------------------------------------`
2			`--`
3			`-- Title : cfft`
4			`-- Design : cfft`
5			`-- Author : ZHAO Ming`
6			`-- email : sradio@opencores.org`
7			`--`
8			`---------------------------------------------------------------------------------------------------`
9			`--`
10			`-- File : cfft.vhd`
11			`-- Generated : Thu Oct 3 03:03:58 2002`
12			`--`
13			`---------------------------------------------------------------------------------------------------`
14			`--`
15			`-- Description : radix 4 1024 point FFT input 12 bit Output 14 bit with`
16			`-- limit and overfall processing internal`
17			`--`
18			`-- The gain is 0.0287 for FFT and 29.4 for IFFT`
19			`--`
20			`-- The output is 4-based reversed ordered, it means`
21			`-- a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1`
22			`--`
23			`--`
24			`---------------------------------------------------------------------------------------------------`
25
26
27			`---------------------------------------------------------------------------------------------------`
28			`--`
29			`-- port :`
30			`-- clk : main clk -- I have test 90M with Xilinx virtex600E`
31			`-- rst : globe reset -- '1' for reset`
32			`-- start : start fft -- one clock '1' before data input`
33			`-- invert : '0' for fft and '1' for ifft, it is sampled when start is '1'`
34			`-- Iin,Qin : data input-- following start immediately, input data`
35			`-- -- power should not be too big`
36			`-- inputbusy : if it change to '0' then next fft is enable`
37			`-- outdataen : when it is '1', the valid data is output`
38			`-- Iout,Qout : fft data output when outdataen is '1'`
39			`--`
40			`---------------------------------------------------------------------------------------------------`
41			`--`
42			`-- Revisions : 0`
43			`-- Revision Number : 1`
44			`-- Version : 1.1.0`
45			`-- Date : Oct 17 2002`
46			`-- Modifier : ZHAO Ming`
47			`-- Desccription : Data width configurable`
48			`--`
49			`---------------------------------------------------------------------------------------------------`
50			`--`
51			`-- Revisions : 0`
52			`-- Revision Number : 2`
53			`-- Version : 1.2.0`
54			`-- Date : Oct 18 2002`
55			`-- Modifier : ZHAO Ming`
56			`-- Desccription : Point configurable`
57			`-- FFT Gain IFFT GAIN`
58			`-- 256 0.0698 17.9`
59			`-- 1024 0.0287 29.4`
60			`-- 4096 0.0118 48.2742`
61			`--`
62			`--`
63			`---------------------------------------------------------------------------------------------------`
64			`--`
65			`-- Revisions : 0`
66			`-- Revision Number : 3`
67			`-- Version : 1.3.0`
68			`-- Date : Nov 19 2002`
69			`-- Modifier : ZHAO Ming`
70			`-- Desccription : add output data position indication`
71			`--`
72			`--`
73			`---------------------------------------------------------------------------------------------------`
74
75			`library IEEE;`
76			`use IEEE.STD_LOGIC_1164.all;`
77			`use IEEE.STD_LOGIC_ARITH.all;`
78			`use IEEE.STD_LOGIC_UNSIGNED.all;`
79
80			`entity cfft is`
81			`generic (`
82			`Tx_nRx : natural :=1; -- tx = 1, rx = 0`
83			`WIDTH : natural := 12;`
84			`POINT : natural := 64;`
85			`STAGE : natural := 3 -- STAGE=log4(POINT)`
86			`);`
87			`port(`
88			`rst : in std_logic;`
89			`Iin : in std_logic_vector(WIDTH-1 downto 0);`
90			`Qin : in std_logic_vector(WIDTH-1 downto 0);`
91			`Iout : out std_logic_vector(WIDTH+1 downto 0);`
92			`Qout : out std_logic_vector(WIDTH+1 downto 0);`
93			`factorstart : in std_logic;`
94			`cfft4start : in std_logic;`
95
96			`ClkIn : in std_logic;`
97
98			`sel_mux : in std_logic;`
99			`inv : in std_logic;`
100
101			`wen_in : in std_logic;`
102			`addrin_in : in std_logic_vector(2*stage-Tx_nRx downto 0);`
103			`addrout_in : in std_logic_vector(2*stage-Tx_nRx downto 0);`
104
105			`wen_proc : in std_logic;`
106			`addrin_proc : in std_logic_vector(2*stage-1 downto 0);`
107			`addrout_proc : in std_logic_vector(2*stage-1 downto 0);`
108
109			`wen_out : in std_logic;`
110			`addrin_out : in std_logic_vector(2*stage-1 downto 0);`
111			`addrout_out : in std_logic_vector(2*stage-1 downto 0));`
112
113			`end cfft;`
114
115
116			`architecture cfft of cfft is`
117
118			`component mux`
119			`generic (`
120			`width : natural);`
121			`port (`
122			`inRa : in std_logic_vector(WIDTH-1 downto 0);`
123			`inIa : in std_logic_vector(WIDTH-1 downto 0);`
124			`inRb : in std_logic_vector(WIDTH-1 downto 0);`
125			`inIb : in std_logic_vector(WIDTH-1 downto 0);`
126			`outR : out std_logic_vector(WIDTH-1 downto 0);`
127			`outI : out std_logic_vector(WIDTH-1 downto 0);`
128
129			`clk : in std_logic;`
130			`sel : in std_logic);`
131			`end component;`
132
133			`component conj`
134			`generic (`
135			`width : natural);`
136			`port (`
137
138			`inR : in std_logic_vector(WIDTH-1 downto 0);`
139			`inI : in std_logic_vector(WIDTH-1 downto 0);`
140			`outR : out std_logic_vector(WIDTH-1 downto 0);`
141			`outI : out std_logic_vector(WIDTH-1 downto 0);`
142
143			`clk : in std_logic;`
144			`conj : in std_logic);`
145			`end component;`
146
147			`component ram`
148			`generic (`
149			`width : natural;`
150			`depth : natural;`
151			`Addr_width : natural);`
152			`port (`
153			`clkin : in std_logic;`
154			`wen : in std_logic;`
155			`addrin : in std_logic_vector(Addr_width-1 downto 0);`
156			`dinR : in std_logic_vector(width-1 downto 0);`
157			`dinI : in std_logic_vector(width-1 downto 0);`
158			`clkout : in std_logic;`
159			`addrout : in std_logic_vector(Addr_width-1 downto 0);`
160			`doutR : out std_logic_vector(width-1 downto 0);`
161			`doutI : out std_logic_vector(width-1 downto 0));`
162			`end component;`
163
164			`component cfft4`
165			`generic (`
166			`width : natural`
167			`);`
168			`port(`
169			`clk : in std_logic;`
170			`rst : in std_logic;`
171			`start : in std_logic;`
172			`invert : in std_logic;`
173			`I : in std_logic_vector(WIDTH-1 downto 0);`
174			`Q : in std_logic_vector(WIDTH-1 downto 0);`
175			`Iout : out std_logic_vector(WIDTH+1 downto 0);`
176			`Qout : out std_logic_vector(WIDTH+1 downto 0)`
177			`);`
178			`end component;`
179
180			`component div4limit`
181			`generic (`
182			`WIDTH : natural`
183			`);`
184			`port(`
185			`clk : in std_logic;`
186			`D : in std_logic_vector(WIDTH+3 downto 0);`
187			`Q : out std_logic_vector(WIDTH-1 downto 0)`
188			`);`
189			`end component;`
190
191			`component mulfactor`
192			`generic (`
193			`WIDTH : natural;`
194			`STAGE : natural`
195			`);`
196			`port(`
197			`clk : in std_logic;`
198			`rst : in std_logic;`
199			`angle : in signed(2*STAGE-1 downto 0);`
200			`I : in signed(WIDTH+1 downto 0);`
201			`Q : in signed(WIDTH+1 downto 0);`
202			`Iout : out signed(WIDTH+3 downto 0);`
203			`Qout : out signed(WIDTH+3 downto 0)`
204			`);`
205			`end component;`
206
207			`component rofactor`
208			`generic (`
209			`POINT : natural;`
210			`STAGE : natural`
211			`);`
212			`port(`
213			`clk : in std_logic;`
214			`rst : in std_logic;`
215			`start : in std_logic;`
216			`invert : in std_logic;`
217			`angle : out std_logic_vector(2*STAGE-1 downto 0)`
218			`);`
219			`end component;`
220
221
222			`component blockdram`
223			`generic (`
224			`depth : natural;`
225			`Dwidth : natural;`
226			`Awidth : natural);`
227			`port (`
228			`clkin : in std_logic;`
229			`wen : in std_logic;`
230			`addrin : in std_logic_vector(Awidth-1 downto 0);`
231			`din : in std_logic_vector(Dwidth-1 downto 0);`
232			`clkout : in std_logic;`
233			`addrout : in std_logic_vector(Awidth-1 downto 0);`
234			`dout : out std_logic_vector(Dwidth-1 downto 0));`
235			`end component;`
236
237			`signal MuxInRa, MuxInIa, MuxInRb, MuxInIb : std_logic_vector(WIDTH-1 downto 0) := (others => '0');`
238			`signal conjInR, conjInI : std_logic_vector(WIDTH-1 downto 0) := (others => '0');`
239			`signal cfft4InR, cfft4InI : std_logic_vector(WIDTH-1 downto 0) := (others => '0');`
240			`signal cfft4outR, cfft4outI : std_logic_vector(WIDTH+1 downto 0) := (others => '0');`
241			`signal MulOutR, MulOutI : signed(WIDTH+3 downto 0) := (others => '0');`
242			`signal fftR, fftI : std_logic_vector(WIDTH-1 downto 0) := (others => '0');`
243			`signal angle : std_logic_vector(2*STAGE-1 downto 0 ) := ( others => '0');`
244			`signal invert : std_logic;`
245
246			`begin`
247
248			`TX:if Tx_nRx = 1 generate`
249			`RamIn : ram`
250			`generic map (`
251			`width => WIDTH,`
252			`depth => POINT,`
253			`Addr_width => 2*STAGE)`
254			`port map (`
255			`clkin => ClkIn,`
256			`wen => wen_in,`
257			`addrin => addrin_in,`
258			`dinR => Iin,`
259			`dinI => Qin,`
260			`clkout => ClkIn,`
261			`addrout => addrout_in,`
262			`doutR => MuxInRa,`
263			`doutI => MuxInIa);`
264
265			`RamOut : ram`
266			`generic map (`
267			`width => WIDTH+2,`
268			`depth => POINT,`
269			`Addr_width => 2*STAGE)`
270			`port map (`
271			`clkin => ClkIn,`
272			`wen => wen_out,`
273			`addrin => addrin_out,`
274			`dinR => cfft4outR,`
275			`dinI => cfft4outR,`
276			`clkout => ClkIn,`
277			`addrout => addrout_out,`
278			`doutR => Iout,`
279			`doutI => open);`
280			`end generate;`
281
282			`RX:if Tx_nRx = 0 generate`
283			`RamIn : ram`
284			`generic map (`
285			`width => WIDTH,`
286			`depth => 2*POINT,`
287			`Addr_width => 2*STAGE+1)`
288			`port map (`
289			`clkin => ClkIn,`
290			`wen => wen_in,`
291			`addrin => addrin_in,`
292			`dinR => Iin,`
293			`dinI => Qin,`
294			`clkout => ClkIn,`
295			`addrout => addrout_in,`
296			`doutR => MuxInRa,`
297			`doutI => open);`
298
299			`MuxinIa <= (others => '0');`
300
301			`RamOut : ram`
302			`generic map (`
303			`width => WIDTH+2,`
304			`depth => POINT,`
305			`Addr_width => 2*STAGE)`
306			`port map (`
307			`clkin => ClkIn,`
308			`wen => wen_out,`
309			`addrin => addrin_out,`
310			`dinR => cfft4outR,`
311			`dinI => cfft4outR,`
312			`clkout => ClkIn,`
313			`addrout => addrout_out,`
314			`doutR => Iout,`
315			`doutI => Qout);`
316
317			`end generate;`
318
319
320			`RamProc : ram`
321			`generic map (`
322			`width => WIDTH,`
323			`depth => POINT,`
324			`Addr_width => 2*STAGE)`
325			`port map (`
326			`clkin => ClkIn,`
327			`wen => wen_proc,`
328			`addrin => addrin_proc,`
329			`dinR => fftR,`
330			`dinI => fftI,`
331			`clkout => ClkIn,`
332			`addrout => addrout_proc,`
333			`doutR => MuxInRb,`
334			`doutI => MuxInIb);`
335
336			`mux_1 : mux`
337			`generic map (`
338			`width => width)`
339			`port map (`
340			`inRa => MuxInRa,`
341			`inIa => MuxInIa,`
342			`inRb => MuxInRb,`
343			`inIb => MuxInIb,`
344			`outR => conjInR,`
345			`outI => conjInI,`
346			`clk => clkin,`
347			`sel => sel_mux);`
348
349			`invert <= (inv and conv_std_logic_vector(Tx_nRx,1)(0));`
350
351			`conj_1: conj`
352			`generic map (`
353			`width => width)`
354			`port map (`
355
356			`inR => conjInR,`
357			`inI => conjInI,`
358			`outR => cfft4InR,`
359			`outI => cfft4InI,`
360			`clk => Clkin,`
361			`conj => invert);`
362
363			`acfft4 : cfft4`
364			`generic map (`
365			`WIDTH => WIDTH`
366			`)`
367			`port map (`
368			`clk => ClkIn,`
369			`rst => rst,`
370			`start => cfft4start,`
371			`invert => conv_std_logic_vector(Tx_nRx,1)(0),`
372			`I => cfft4InR,`
373			`Q => cfft4InI,`
374			`Iout => cfft4outR,`
375			`Qout => cfft4outI`
376			`);`
377
378			`amulfactor : mulfactor`
379			`generic map (`
380			`WIDTH => WIDTH,`
381			`STAGE => STAGE`
382			`)`
383			`port map (`
384			`clk => ClkIn,`
385			`rst => rst,`
386			`angle => signed(angle),`
387			`I => signed(cfft4outR),`
388			`Q => signed(cfft4outI),`
389			`Iout => MulOutR,`
390			`Qout => MulOutI`
391			`);`
392
393			`arofactor : rofactor`
394			`generic map (`
395			`POINT => POINT,`
396			`STAGE => STAGE`
397			`)`
398			`port map (`
399			`clk => ClkIn,`
400			`rst => rst,`
401			`start => factorstart,`
402			`invert => conv_std_logic_vector(Tx_nRx,1)(0), -- IFFT`
403			`angle => angle`
404			`);`
405
406			`Rlimit : div4limit`
407			`generic map (`
408			`WIDTH => WIDTH`
409			`)`
410			`port map (`
411			`clk => ClkIn,`
412			`D => std_logic_vector(MulOutR),`
413			`Q => fftR`
414			`);`
415			`Ilimit : div4limit`
416			`generic map (`
417			`WIDTH => WIDTH`
418			`)`
419			`port map (`
420			`clk => ClkIn,`
421			`D => std_logic_vector(MulOutI),`
422			`Q => fftI`
423			`);`
424
425			`end cfft;`